Macros
#define	MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL)

#define	MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL)

#define	MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL)

#define	MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL)

#define	MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL)

#define	MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL)

#define	MXC_R_GPIO_OUT ((uint32_t)0x00000018UL)

#define	MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL)

#define	MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL)

#define	MXC_R_GPIO_IN ((uint32_t)0x00000024UL)

#define	MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL)

#define	MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL)

#define	MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL)

#define	MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL)

#define	MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL)

#define	MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL)

#define	MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL)

#define	MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL)

#define	MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL)

#define	MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL)

#define	MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL)

#define	MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL)

#define	MXC_R_GPIO_PDPU_SEL0 ((uint32_t)0x00000060UL)

#define	MXC_R_GPIO_PDPU_SEL1 ((uint32_t)0x00000064UL)

#define	MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL)

#define	MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL)

#define	MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL)

#define	MXC_R_GPIO_DS_SEL0 ((uint32_t)0x000000B0UL)

#define	MXC_R_GPIO_DS_SEL1 ((uint32_t)0x000000B4UL)

#define	MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL)

Detailed Description

GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_GPIO_DS_SEL0

#define MXC_R_GPIO_DS_SEL0 ((uint32_t)0x000000B0UL)

Offset from GPIO Base Address: 0x00B0

◆ MXC_R_GPIO_DS_SEL1

#define MXC_R_GPIO_DS_SEL1 ((uint32_t)0x000000B4UL)

Offset from GPIO Base Address: 0x00B4

◆ MXC_R_GPIO_EN0

#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL)

Offset from GPIO Base Address: 0x0000

◆ MXC_R_GPIO_EN0_CLR

#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL)

Offset from GPIO Base Address: 0x0008

◆ MXC_R_GPIO_EN0_SET

#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL)

Offset from GPIO Base Address: 0x0004

◆ MXC_R_GPIO_EN1

#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL)

Offset from GPIO Base Address: 0x0068

◆ MXC_R_GPIO_EN1_CLR

#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL)

Offset from GPIO Base Address: 0x0070

◆ MXC_R_GPIO_EN1_SET

#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL)

Offset from GPIO Base Address: 0x006C

◆ MXC_R_GPIO_IN

#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL)

Offset from GPIO Base Address: 0x0024

◆ MXC_R_GPIO_IN_EN

#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL)

Offset from GPIO Base Address: 0x0030

◆ MXC_R_GPIO_INT_CLR

#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL)

Offset from GPIO Base Address: 0x0048

◆ MXC_R_GPIO_INT_DUAL_EDGE

#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL)

Offset from GPIO Base Address: 0x005C

◆ MXC_R_GPIO_INT_EN

#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL)

Offset from GPIO Base Address: 0x0034

◆ MXC_R_GPIO_INT_EN_CLR

#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL)

Offset from GPIO Base Address: 0x003C

◆ MXC_R_GPIO_INT_EN_SET

#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL)

Offset from GPIO Base Address: 0x0038

◆ MXC_R_GPIO_INT_MOD

#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL)

Offset from GPIO Base Address: 0x0028

◆ MXC_R_GPIO_INT_POL

#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL)

Offset from GPIO Base Address: 0x002C

◆ MXC_R_GPIO_INT_STAT

#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL)

Offset from GPIO Base Address: 0x0040

◆ MXC_R_GPIO_OUT

#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL)

Offset from GPIO Base Address: 0x0018

◆ MXC_R_GPIO_OUT_CLR

#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL)

Offset from GPIO Base Address: 0x0020

◆ MXC_R_GPIO_OUT_EN

#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL)

Offset from GPIO Base Address: 0x000C

◆ MXC_R_GPIO_OUT_EN_CLR

#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL)

Offset from GPIO Base Address: 0x0014

◆ MXC_R_GPIO_OUT_EN_SET

#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL)

Offset from GPIO Base Address: 0x0010

◆ MXC_R_GPIO_OUT_SET

#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL)

Offset from GPIO Base Address: 0x001C

◆ MXC_R_GPIO_PDPU_SEL0

#define MXC_R_GPIO_PDPU_SEL0 ((uint32_t)0x00000060UL)

Offset from GPIO Base Address: 0x0060

◆ MXC_R_GPIO_PDPU_SEL1

#define MXC_R_GPIO_PDPU_SEL1 ((uint32_t)0x00000064UL)

Offset from GPIO Base Address: 0x0064

◆ MXC_R_GPIO_PSSEL

#define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL)

Offset from GPIO Base Address: 0x00B8

◆ MXC_R_GPIO_WAKE_EN

#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL)

Offset from GPIO Base Address: 0x004C

◆ MXC_R_GPIO_WAKE_EN_CLR

#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL)

Offset from GPIO Base Address: 0x0054

◆ MXC_R_GPIO_WAKE_EN_SET

#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL)

Offset from GPIO Base Address: 0x0050

Macros