sfe_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __R  uint32_t rsv_0x0_0x3ff[256];
    __IO uint32_t cfg;                  
    __R  uint32_t rsv_0x404;
    __IO uint32_t hfsa;                 
    __IO uint32_t hrsa;                 
    __IO uint32_t sfdp_sba;             
    __IO uint32_t flash_sba;            
    __IO uint32_t flash_sta;            
    __IO uint32_t ram_sba;              
    __IO uint32_t ram_sta;              
} mxc_sfe_regs_t;
 
/* Register offsets for module SFE */
#define MXC_R_SFE_CFG                      ((uint32_t)0x00000400UL) 
#define MXC_R_SFE_HFSA                     ((uint32_t)0x00000408UL) 
#define MXC_R_SFE_HRSA                     ((uint32_t)0x0000040CUL) 
#define MXC_R_SFE_SFDP_SBA                 ((uint32_t)0x00000410UL) 
#define MXC_R_SFE_FLASH_SBA                ((uint32_t)0x00000414UL) 
#define MXC_R_SFE_FLASH_STA                ((uint32_t)0x00000418UL) 
#define MXC_R_SFE_RAM_SBA                  ((uint32_t)0x0000041CUL) 
#define MXC_R_SFE_RAM_STA                  ((uint32_t)0x00000420UL) 
#define MXC_F_SFE_CFG_DRLE_POS                         0 
#define MXC_F_SFE_CFG_DRLE                             ((uint32_t)(0x1UL << MXC_F_SFE_CFG_DRLE_POS)) 
#define MXC_F_SFE_CFG_FLOCK_POS                        15 
#define MXC_F_SFE_CFG_FLOCK                            ((uint32_t)(0x1UL << MXC_F_SFE_CFG_FLOCK_POS)) 
#define MXC_F_SFE_CFG_RD_EN_POS                        16 
#define MXC_F_SFE_CFG_RD_EN                            ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RD_EN_POS)) 
#define MXC_F_SFE_CFG_WR_EN_POS                        17 
#define MXC_F_SFE_CFG_WR_EN                            ((uint32_t)(0x1UL << MXC_F_SFE_CFG_WR_EN_POS)) 
#define MXC_F_SFE_CFG_RRLOCK_POS                       22 
#define MXC_F_SFE_CFG_RRLOCK                           ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RRLOCK_POS)) 
#define MXC_F_SFE_CFG_RWLOCK_POS                       23 
#define MXC_F_SFE_CFG_RWLOCK                           ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RWLOCK_POS)) 
#define MXC_F_SFE_HFSA_HFSA_POS                        10 
#define MXC_F_SFE_HFSA_HFSA                            ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_HFSA_HFSA_POS)) 
#define MXC_F_SFE_HRSA_HRSA_POS                        10 
#define MXC_F_SFE_HRSA_HRSA                            ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_HRSA_HRSA_POS)) 
#define MXC_F_SFE_SFDP_SBA_SFDP_SBA_POS                8 
#define MXC_F_SFE_SFDP_SBA_SFDP_SBA                    ((uint32_t)(0xFFFFFFUL << MXC_F_SFE_SFDP_SBA_SFDP_SBA_POS)) 
#define MXC_F_SFE_FLASH_SBA_FLASH_SBA_POS              10 
#define MXC_F_SFE_FLASH_SBA_FLASH_SBA                  ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_FLASH_SBA_FLASH_SBA_POS)) 
#define MXC_F_SFE_FLASH_STA_FLASH_STA_POS              10 
#define MXC_F_SFE_FLASH_STA_FLASH_STA                  ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_FLASH_STA_FLASH_STA_POS)) 
#define MXC_F_SFE_RAM_SBA_RAM_SBA_POS                  10 
#define MXC_F_SFE_RAM_SBA_RAM_SBA                      ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_RAM_SBA_RAM_SBA_POS)) 
#define MXC_F_SFE_RAM_STA_RAM_STA_POS                  10 
#define MXC_F_SFE_RAM_STA_RAM_STA                      ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_RAM_STA_RAM_STA_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_