spi_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SPI_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SPI_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    union {
        __IO uint32_t data32;           
        __IO uint16_t data16[2];        
        __IO uint8_t  data8[4];         
    };
    __IO uint32_t mstr_cntl;            
    __IO uint32_t trnmt_size;           
    __IO uint32_t static_config;        
    __IO uint32_t ss_time;              
    __IO uint32_t clk_config;           
    __R  uint32_t rsv_0x18;
    __IO uint32_t dma;                  
    __IO uint32_t int_fl;               
    __IO uint32_t int_en;               
    __IO uint32_t wake_fl;              
    __IO uint32_t wake_en;              
    __I  uint32_t stat;                 
} mxc_spi_regs_t;
 
/* Register offsets for module SPI */
#define MXC_R_SPI_DATA32                   ((uint32_t)0x00000000UL) 
#define MXC_R_SPI_DATA16                   ((uint32_t)0x00000000UL) 
#define MXC_R_SPI_DATA8                    ((uint32_t)0x00000000UL) 
#define MXC_R_SPI_MSTR_CNTL                ((uint32_t)0x00000004UL) 
#define MXC_R_SPI_TRNMT_SIZE               ((uint32_t)0x00000008UL) 
#define MXC_R_SPI_STATIC_CONFIG            ((uint32_t)0x0000000CUL) 
#define MXC_R_SPI_SS_TIME                  ((uint32_t)0x00000010UL) 
#define MXC_R_SPI_CLK_CONFIG               ((uint32_t)0x00000014UL) 
#define MXC_R_SPI_DMA                      ((uint32_t)0x0000001CUL) 
#define MXC_R_SPI_INT_FL                   ((uint32_t)0x00000020UL) 
#define MXC_R_SPI_INT_EN                   ((uint32_t)0x00000024UL) 
#define MXC_R_SPI_WAKE_FL                  ((uint32_t)0x00000028UL) 
#define MXC_R_SPI_WAKE_EN                  ((uint32_t)0x0000002CUL) 
#define MXC_R_SPI_STAT                     ((uint32_t)0x00000030UL) 
#define MXC_F_SPI_DATA32_DATA_POS                      0 
#define MXC_F_SPI_DATA32_DATA                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_DATA32_DATA_POS)) 
#define MXC_F_SPI_DATA16_DATA_POS                      0 
#define MXC_F_SPI_DATA16_DATA                          ((uint16_t)(0xFFFFUL << MXC_F_SPI_DATA16_DATA_POS)) 
#define MXC_F_SPI_DATA8_DATA_POS                       0 
#define MXC_F_SPI_DATA8_DATA                           ((uint8_t)(0xFFUL << MXC_F_SPI_DATA8_DATA_POS)) 
#define MXC_F_SPI_MSTR_CNTL_SPIEN_POS                  0 
#define MXC_F_SPI_MSTR_CNTL_SPIEN                      ((uint32_t)(0x1UL << MXC_F_SPI_MSTR_CNTL_SPIEN_POS)) 
#define MXC_F_SPI_MSTR_CNTL_MMEN_POS                   1 
#define MXC_F_SPI_MSTR_CNTL_MMEN                       ((uint32_t)(0x1UL << MXC_F_SPI_MSTR_CNTL_MMEN_POS)) 
#define MXC_F_SPI_MSTR_CNTL_SSIO_POS                   4 
#define MXC_F_SPI_MSTR_CNTL_SSIO                       ((uint32_t)(0x1UL << MXC_F_SPI_MSTR_CNTL_SSIO_POS)) 
#define MXC_F_SPI_MSTR_CNTL_START_POS                  5 
#define MXC_F_SPI_MSTR_CNTL_START                      ((uint32_t)(0x1UL << MXC_F_SPI_MSTR_CNTL_START_POS)) 
#define MXC_F_SPI_MSTR_CNTL_SSCTRL_POS                 8 
#define MXC_F_SPI_MSTR_CNTL_SSCTRL                     ((uint32_t)(0x1UL << MXC_F_SPI_MSTR_CNTL_SSCTRL_POS)) 
#define MXC_F_SPI_MSTR_CNTL_SS_POS                     16 
#define MXC_F_SPI_MSTR_CNTL_SS                         ((uint32_t)(0x7UL << MXC_F_SPI_MSTR_CNTL_SS_POS)) 
#define MXC_V_SPI_MSTR_CNTL_SS_SS0                     ((uint32_t)0x1UL) 
#define MXC_S_SPI_MSTR_CNTL_SS_SS0                     (MXC_V_SPI_MSTR_CNTL_SS_SS0 << MXC_F_SPI_MSTR_CNTL_SS_POS) 
#define MXC_V_SPI_MSTR_CNTL_SS_SS1                     ((uint32_t)0x2UL) 
#define MXC_S_SPI_MSTR_CNTL_SS_SS1                     (MXC_V_SPI_MSTR_CNTL_SS_SS1 << MXC_F_SPI_MSTR_CNTL_SS_POS) 
#define MXC_V_SPI_MSTR_CNTL_SS_SS2                     ((uint32_t)0x4UL) 
#define MXC_S_SPI_MSTR_CNTL_SS_SS2                     (MXC_V_SPI_MSTR_CNTL_SS_SS2 << MXC_F_SPI_MSTR_CNTL_SS_POS) 
#define MXC_F_SPI_TRNMT_SIZE_TX_NUM_CHAR_POS           0 
#define MXC_F_SPI_TRNMT_SIZE_TX_NUM_CHAR               ((uint32_t)(0xFFFFUL << MXC_F_SPI_TRNMT_SIZE_TX_NUM_CHAR_POS)) 
#define MXC_F_SPI_TRNMT_SIZE_RX_NUM_CHAR_POS           16 
#define MXC_F_SPI_TRNMT_SIZE_RX_NUM_CHAR               ((uint32_t)(0xFFFFUL << MXC_F_SPI_TRNMT_SIZE_RX_NUM_CHAR_POS)) 
#define MXC_F_SPI_STATIC_CONFIG_PHASE_POS              0 
#define MXC_F_SPI_STATIC_CONFIG_PHASE                  ((uint32_t)(0x1UL << MXC_F_SPI_STATIC_CONFIG_PHASE_POS)) 
#define MXC_F_SPI_STATIC_CONFIG_CLKPOL_POS             1 
#define MXC_F_SPI_STATIC_CONFIG_CLKPOL                 ((uint32_t)(0x1UL << MXC_F_SPI_STATIC_CONFIG_CLKPOL_POS)) 
#define MXC_F_SPI_STATIC_CONFIG_NUMBITS_POS            8 
#define MXC_F_SPI_STATIC_CONFIG_NUMBITS                ((uint32_t)(0xFUL << MXC_F_SPI_STATIC_CONFIG_NUMBITS_POS)) 
#define MXC_V_SPI_STATIC_CONFIG_NUMBITS_0              ((uint32_t)0x0UL) 
#define MXC_S_SPI_STATIC_CONFIG_NUMBITS_0              (MXC_V_SPI_STATIC_CONFIG_NUMBITS_0 << MXC_F_SPI_STATIC_CONFIG_NUMBITS_POS) 
#define MXC_F_SPI_STATIC_CONFIG_DATAWIDTH_POS          12 
#define MXC_F_SPI_STATIC_CONFIG_DATAWIDTH              ((uint32_t)(0x3UL << MXC_F_SPI_STATIC_CONFIG_DATAWIDTH_POS)) 
#define MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_MONO         ((uint32_t)0x0UL) 
#define MXC_S_SPI_STATIC_CONFIG_DATAWIDTH_MONO         (MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_MONO << MXC_F_SPI_STATIC_CONFIG_DATAWIDTH_POS) 
#define MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_DUAL         ((uint32_t)0x1UL) 
#define MXC_S_SPI_STATIC_CONFIG_DATAWIDTH_DUAL         (MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_DUAL << MXC_F_SPI_STATIC_CONFIG_DATAWIDTH_POS) 
#define MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_QUAD         ((uint32_t)0x2UL) 
#define MXC_S_SPI_STATIC_CONFIG_DATAWIDTH_QUAD         (MXC_V_SPI_STATIC_CONFIG_DATAWIDTH_QUAD << MXC_F_SPI_STATIC_CONFIG_DATAWIDTH_POS) 
#define MXC_F_SPI_STATIC_CONFIG_3WIRE_POS              15 
#define MXC_F_SPI_STATIC_CONFIG_3WIRE                  ((uint32_t)(0x1UL << MXC_F_SPI_STATIC_CONFIG_3WIRE_POS)) 
#define MXC_F_SPI_STATIC_CONFIG_SSPOL_POS              16 
#define MXC_F_SPI_STATIC_CONFIG_SSPOL                  ((uint32_t)(0xFFUL << MXC_F_SPI_STATIC_CONFIG_SSPOL_POS)) 
#define MXC_V_SPI_STATIC_CONFIG_SSPOL_SS0_HIGH         ((uint32_t)0x1UL) 
#define MXC_S_SPI_STATIC_CONFIG_SSPOL_SS0_HIGH         (MXC_V_SPI_STATIC_CONFIG_SSPOL_SS0_HIGH << MXC_F_SPI_STATIC_CONFIG_SSPOL_POS) 
#define MXC_V_SPI_STATIC_CONFIG_SSPOL_SS1_HIGH         ((uint32_t)0x2UL) 
#define MXC_S_SPI_STATIC_CONFIG_SSPOL_SS1_HIGH         (MXC_V_SPI_STATIC_CONFIG_SSPOL_SS1_HIGH << MXC_F_SPI_STATIC_CONFIG_SSPOL_POS) 
#define MXC_V_SPI_STATIC_CONFIG_SSPOL_SS2_HIGH         ((uint32_t)0x4UL) 
#define MXC_S_SPI_STATIC_CONFIG_SSPOL_SS2_HIGH         (MXC_V_SPI_STATIC_CONFIG_SSPOL_SS2_HIGH << MXC_F_SPI_STATIC_CONFIG_SSPOL_POS) 
#define MXC_F_SPI_SS_TIME_PRE_POS                      0 
#define MXC_F_SPI_SS_TIME_PRE                          ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_PRE_POS)) 
#define MXC_V_SPI_SS_TIME_PRE_256                      ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_PRE_256                      (MXC_V_SPI_SS_TIME_PRE_256 << MXC_F_SPI_SS_TIME_PRE_POS) 
#define MXC_F_SPI_SS_TIME_POST_POS                     8 
#define MXC_F_SPI_SS_TIME_POST                         ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_POST_POS)) 
#define MXC_V_SPI_SS_TIME_POST_256                     ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_POST_256                     (MXC_V_SPI_SS_TIME_POST_256 << MXC_F_SPI_SS_TIME_POST_POS) 
#define MXC_F_SPI_SS_TIME_INACT_POS                    16 
#define MXC_F_SPI_SS_TIME_INACT                        ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_INACT_POS)) 
#define MXC_V_SPI_SS_TIME_INACT_256                    ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_INACT_256                    (MXC_V_SPI_SS_TIME_INACT_256 << MXC_F_SPI_SS_TIME_INACT_POS) 
#define MXC_F_SPI_CLK_CONFIG_LOW_POS                   0 
#define MXC_F_SPI_CLK_CONFIG_LOW                       ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CONFIG_LOW_POS)) 
#define MXC_V_SPI_CLK_CONFIG_LOW_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_SPI_CLK_CONFIG_LOW_DIS                   (MXC_V_SPI_CLK_CONFIG_LOW_DIS << MXC_F_SPI_CLK_CONFIG_LOW_POS) 
#define MXC_F_SPI_CLK_CONFIG_HIGH_POS                  8 
#define MXC_F_SPI_CLK_CONFIG_HIGH                      ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CONFIG_HIGH_POS)) 
#define MXC_V_SPI_CLK_CONFIG_HIGH_DIS                  ((uint32_t)0x0UL) 
#define MXC_S_SPI_CLK_CONFIG_HIGH_DIS                  (MXC_V_SPI_CLK_CONFIG_HIGH_DIS << MXC_F_SPI_CLK_CONFIG_HIGH_POS) 
#define MXC_F_SPI_CLK_CONFIG_SCALE_POS                 16 
#define MXC_F_SPI_CLK_CONFIG_SCALE                     ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CONFIG_SCALE_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS                0 
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS                   6 
#define MXC_F_SPI_DMA_TX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS                7 
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS                  8 
#define MXC_F_SPI_DMA_TX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) 
#define MXC_F_SPI_DMA_TX_DMA_EN_POS                    15 
#define MXC_F_SPI_DMA_TX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS                16 
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS                   22 
#define MXC_F_SPI_DMA_RX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS                23 
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS                  24 
#define MXC_F_SPI_DMA_RX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) 
#define MXC_F_SPI_DMA_RX_DMA_EN_POS                    31 
#define MXC_F_SPI_DMA_RX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) 
#define MXC_F_SPI_INT_FL_TXTHRLD_POS                   0 
#define MXC_F_SPI_INT_FL_TXTHRLD                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TXTHRLD_POS)) 
#define MXC_F_SPI_INT_FL_TXEMPTY_POS                   1 
#define MXC_F_SPI_INT_FL_TXEMPTY                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TXEMPTY_POS)) 
#define MXC_F_SPI_INT_FL_RXTHRLD_POS                   2 
#define MXC_F_SPI_INT_FL_RXTHRLD                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RXTHRLD_POS)) 
#define MXC_F_SPI_INT_FL_RXFULL_POS                    3 
#define MXC_F_SPI_INT_FL_RXFULL                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RXFULL_POS)) 
#define MXC_F_SPI_INT_FL_SSA_POS                       4 
#define MXC_F_SPI_INT_FL_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) 
#define MXC_F_SPI_INT_FL_SSD_POS                       5 
#define MXC_F_SPI_INT_FL_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) 
#define MXC_F_SPI_INT_FL_FAULT_POS                     8 
#define MXC_F_SPI_INT_FL_FAULT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS)) 
#define MXC_F_SPI_INT_FL_ABORT_POS                     9 
#define MXC_F_SPI_INT_FL_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) 
#define MXC_F_SPI_INT_FL_MSTRDONE_POS                  11 
#define MXC_F_SPI_INT_FL_MSTRDONE                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_MSTRDONE_POS)) 
#define MXC_F_SPI_INT_FL_TXOVR_POS                     12 
#define MXC_F_SPI_INT_FL_TXOVR                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TXOVR_POS)) 
#define MXC_F_SPI_INT_FL_TXUNDR_POS                    13 
#define MXC_F_SPI_INT_FL_TXUNDR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TXUNDR_POS)) 
#define MXC_F_SPI_INT_FL_RXOVR_POS                     14 
#define MXC_F_SPI_INT_FL_RXOVR                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RXOVR_POS)) 
#define MXC_F_SPI_INT_FL_RXUNDR_POS                    15 
#define MXC_F_SPI_INT_FL_RXUNDR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RXUNDR_POS)) 
#define MXC_F_SPI_INT_EN_TXTHRLD_POS                   0 
#define MXC_F_SPI_INT_EN_TXTHRLD                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TXTHRLD_POS)) 
#define MXC_F_SPI_INT_EN_TXEMPTY_POS                   1 
#define MXC_F_SPI_INT_EN_TXEMPTY                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TXEMPTY_POS)) 
#define MXC_F_SPI_INT_EN_RXTHRLD_POS                   2 
#define MXC_F_SPI_INT_EN_RXTHRLD                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RXTHRLD_POS)) 
#define MXC_F_SPI_INT_EN_RXFULL_POS                    3 
#define MXC_F_SPI_INT_EN_RXFULL                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RXFULL_POS)) 
#define MXC_F_SPI_INT_EN_SSA_POS                       4 
#define MXC_F_SPI_INT_EN_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) 
#define MXC_F_SPI_INT_EN_SSD_POS                       5 
#define MXC_F_SPI_INT_EN_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) 
#define MXC_F_SPI_INT_EN_FAULT_POS                     8 
#define MXC_F_SPI_INT_EN_FAULT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) 
#define MXC_F_SPI_INT_EN_ABORT_POS                     9 
#define MXC_F_SPI_INT_EN_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) 
#define MXC_F_SPI_INT_EN_MSTRDONE_POS                  11 
#define MXC_F_SPI_INT_EN_MSTRDONE                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_MSTRDONE_POS)) 
#define MXC_F_SPI_INT_EN_TXOVR_POS                     12 
#define MXC_F_SPI_INT_EN_TXOVR                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TXOVR_POS)) 
#define MXC_F_SPI_INT_EN_TXUNDR_POS                    13 
#define MXC_F_SPI_INT_EN_TXUNDR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TXUNDR_POS)) 
#define MXC_F_SPI_INT_EN_RXOVR_POS                     14 
#define MXC_F_SPI_INT_EN_RXOVR                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RXOVR_POS)) 
#define MXC_F_SPI_INT_EN_RXUNDR_POS                    15 
#define MXC_F_SPI_INT_EN_RXUNDR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RXUNDR_POS)) 
#define MXC_F_SPI_WAKE_FL_TXTHRLD_POS                  0 
#define MXC_F_SPI_WAKE_FL_TXTHRLD                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TXTHRLD_POS)) 
#define MXC_F_SPI_WAKE_FL_TXEMPTY_POS                  1 
#define MXC_F_SPI_WAKE_FL_TXEMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TXEMPTY_POS)) 
#define MXC_F_SPI_WAKE_FL_RXTHRLD_POS                  2 
#define MXC_F_SPI_WAKE_FL_RXTHRLD                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RXTHRLD_POS)) 
#define MXC_F_SPI_WAKE_FL_RXFULL_POS                   3 
#define MXC_F_SPI_WAKE_FL_RXFULL                       ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RXFULL_POS)) 
#define MXC_F_SPI_WAKE_EN_TXTHRLD_POS                  0 
#define MXC_F_SPI_WAKE_EN_TXTHRLD                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TXTHRLD_POS)) 
#define MXC_F_SPI_WAKE_EN_TXEMPTY_POS                  1 
#define MXC_F_SPI_WAKE_EN_TXEMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TXEMPTY_POS)) 
#define MXC_F_SPI_WAKE_EN_RXTHRLD_POS                  2 
#define MXC_F_SPI_WAKE_EN_RXTHRLD                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RXTHRLD_POS)) 
#define MXC_F_SPI_WAKE_EN_RXFULL_POS                   3 
#define MXC_F_SPI_WAKE_EN_RXFULL                       ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RXFULL_POS)) 
#define MXC_F_SPI_STAT_BUSY_POS                        0 
#define MXC_F_SPI_STAT_BUSY                            ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SPI_REGS_H_