Documentation/MAX32650/adc__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    __IO uint32_t ctrl;

    __IO uint32_t status;

    __IO uint32_t data;

    __IO uint32_t intr;

    __IO uint32_t limit[4];

} mxc_adc_regs_t;


/* Register offsets for module ADC */

#define MXC_R_ADC_CTRL                     ((uint32_t)0x00000000UL)

#define MXC_R_ADC_STATUS                   ((uint32_t)0x00000004UL)

#define MXC_R_ADC_DATA                     ((uint32_t)0x00000008UL)

#define MXC_R_ADC_INTR                     ((uint32_t)0x0000000CUL)

#define MXC_R_ADC_LIMIT                    ((uint32_t)0x00000010UL)

#define MXC_F_ADC_CTRL_START_POS                       0

#define MXC_F_ADC_CTRL_START                           ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS))

#define MXC_V_ADC_CTRL_START_INACTIVE                  ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_START_INACTIVE                  (MXC_V_ADC_CTRL_START_INACTIVE << MXC_F_ADC_CTRL_START_POS)

#define MXC_V_ADC_CTRL_START_START                     ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_START_START                     (MXC_V_ADC_CTRL_START_START << MXC_F_ADC_CTRL_START_POS)

#define MXC_F_ADC_CTRL_PWR_POS                         1

#define MXC_F_ADC_CTRL_PWR                             ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS))

#define MXC_V_ADC_CTRL_PWR_ADC_OFF                     ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_PWR_ADC_OFF                     (MXC_V_ADC_CTRL_PWR_ADC_OFF << MXC_F_ADC_CTRL_PWR_POS)

#define MXC_V_ADC_CTRL_PWR_ADC_ON                      ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_PWR_ADC_ON                      (MXC_V_ADC_CTRL_PWR_ADC_ON << MXC_F_ADC_CTRL_PWR_POS)

#define MXC_F_ADC_CTRL_REFBUF_PWR_POS                  3

#define MXC_F_ADC_CTRL_REFBUF_PWR                      ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REFBUF_PWR_POS))

#define MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_OFF           ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_REFBUF_PWR_REFBUF_OFF           (MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_OFF << MXC_F_ADC_CTRL_REFBUF_PWR_POS)

#define MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_ON            ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_REFBUF_PWR_REFBUF_ON            (MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_ON << MXC_F_ADC_CTRL_REFBUF_PWR_POS)

#define MXC_F_ADC_CTRL_REF_SEL_POS                     4

#define MXC_F_ADC_CTRL_REF_SEL                         ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SEL_POS))

#define MXC_V_ADC_CTRL_REF_SEL_BANDGAP                 ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_REF_SEL_BANDGAP                 (MXC_V_ADC_CTRL_REF_SEL_BANDGAP << MXC_F_ADC_CTRL_REF_SEL_POS)

#define MXC_V_ADC_CTRL_REF_SEL_VDD_DIV2                ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_REF_SEL_VDD_DIV2                (MXC_V_ADC_CTRL_REF_SEL_VDD_DIV2 << MXC_F_ADC_CTRL_REF_SEL_POS)

#define MXC_F_ADC_CTRL_REF_SCALE_POS                   8

#define MXC_F_ADC_CTRL_REF_SCALE                       ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS))

#define MXC_V_ADC_CTRL_REF_SCALE_DIV1                  ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_REF_SCALE_DIV1                  (MXC_V_ADC_CTRL_REF_SCALE_DIV1 << MXC_F_ADC_CTRL_REF_SCALE_POS)

#define MXC_V_ADC_CTRL_REF_SCALE_DIV2                  ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_REF_SCALE_DIV2                  (MXC_V_ADC_CTRL_REF_SCALE_DIV2 << MXC_F_ADC_CTRL_REF_SCALE_POS)

#define MXC_F_ADC_CTRL_INPUT_SCALE_POS                 9

#define MXC_F_ADC_CTRL_INPUT_SCALE                     ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_INPUT_SCALE_POS))

#define MXC_V_ADC_CTRL_INPUT_SCALE_DIV1                ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_INPUT_SCALE_DIV1                (MXC_V_ADC_CTRL_INPUT_SCALE_DIV1 << MXC_F_ADC_CTRL_INPUT_SCALE_POS)

#define MXC_V_ADC_CTRL_INPUT_SCALE_DIV2                ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_INPUT_SCALE_DIV2                (MXC_V_ADC_CTRL_INPUT_SCALE_DIV2 << MXC_F_ADC_CTRL_INPUT_SCALE_POS)

#define MXC_F_ADC_CTRL_CLK_EN_POS                      11

#define MXC_F_ADC_CTRL_CLK_EN                          ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS))

#define MXC_V_ADC_CTRL_CLK_EN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_CLK_EN_DIS                      (MXC_V_ADC_CTRL_CLK_EN_DIS << MXC_F_ADC_CTRL_CLK_EN_POS)

#define MXC_V_ADC_CTRL_CLK_EN_EN                       ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_CLK_EN_EN                       (MXC_V_ADC_CTRL_CLK_EN_EN << MXC_F_ADC_CTRL_CLK_EN_POS)

#define MXC_F_ADC_CTRL_CH_SEL_POS                      12

#define MXC_F_ADC_CTRL_CH_SEL                          ((uint32_t)(0xFUL << MXC_F_ADC_CTRL_CH_SEL_POS))

#define MXC_V_ADC_CTRL_CH_SEL_AIN0                     ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN0                     (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_AIN1                     ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN1                     (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_AIN2                     ((uint32_t)0x2UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN2                     (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_AIN3                     ((uint32_t)0x3UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN3                     (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_AIN0_DIV5                ((uint32_t)0x4UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN0_DIV5                (MXC_V_ADC_CTRL_CH_SEL_AIN0_DIV5 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_AIN1_DIV5                ((uint32_t)0x5UL)

#define MXC_S_ADC_CTRL_CH_SEL_AIN1_DIV5                (MXC_V_ADC_CTRL_CH_SEL_AIN1_DIV5 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VDDB_DIV4                ((uint32_t)0x6UL)

#define MXC_S_ADC_CTRL_CH_SEL_VDDB_DIV4                (MXC_V_ADC_CTRL_CH_SEL_VDDB_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VDDA                     ((uint32_t)0x7UL)

#define MXC_S_ADC_CTRL_CH_SEL_VDDA                     (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VCORE                    ((uint32_t)0x8UL)

#define MXC_S_ADC_CTRL_CH_SEL_VCORE                    (MXC_V_ADC_CTRL_CH_SEL_VCORE << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VRTC_DIV2                ((uint32_t)0x9UL)

#define MXC_S_ADC_CTRL_CH_SEL_VRTC_DIV2                (MXC_V_ADC_CTRL_CH_SEL_VRTC_DIV2 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_RSV_0XA                  ((uint32_t)0xAUL)

#define MXC_S_ADC_CTRL_CH_SEL_RSV_0XA                  (MXC_V_ADC_CTRL_CH_SEL_RSV_0XA << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VDDIO_DIV4               ((uint32_t)0xBUL)

#define MXC_S_ADC_CTRL_CH_SEL_VDDIO_DIV4               (MXC_V_ADC_CTRL_CH_SEL_VDDIO_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_V_ADC_CTRL_CH_SEL_VDDIOH_DIV4              ((uint32_t)0xCUL)

#define MXC_S_ADC_CTRL_CH_SEL_VDDIOH_DIV4              (MXC_V_ADC_CTRL_CH_SEL_VDDIOH_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS)

#define MXC_F_ADC_CTRL_DATA_ALIGN_POS                  17

#define MXC_F_ADC_CTRL_DATA_ALIGN                      ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS))

#define MXC_V_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED        ((uint32_t)0x0UL)

#define MXC_S_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED        (MXC_V_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED << MXC_F_ADC_CTRL_DATA_ALIGN_POS)

#define MXC_V_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED        ((uint32_t)0x1UL)

#define MXC_S_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED        (MXC_V_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED << MXC_F_ADC_CTRL_DATA_ALIGN_POS)

#define MXC_F_ADC_STATUS_ACTIVE_POS                    0

#define MXC_F_ADC_STATUS_ACTIVE                        ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS))

#define MXC_V_ADC_STATUS_ACTIVE_IDLE                   ((uint32_t)0x0UL)

#define MXC_S_ADC_STATUS_ACTIVE_IDLE                   (MXC_V_ADC_STATUS_ACTIVE_IDLE << MXC_F_ADC_STATUS_ACTIVE_POS)

#define MXC_V_ADC_STATUS_ACTIVE_ACTIVE                 ((uint32_t)0x1UL)

#define MXC_S_ADC_STATUS_ACTIVE_ACTIVE                 (MXC_V_ADC_STATUS_ACTIVE_ACTIVE << MXC_F_ADC_STATUS_ACTIVE_POS)

#define MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS             2

#define MXC_F_ADC_STATUS_PWR_UP_ACTIVE                 ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS))

#define MXC_V_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY        ((uint32_t)0x0UL)

#define MXC_S_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY        (MXC_V_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS)

#define MXC_V_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE    ((uint32_t)0x1UL)

#define MXC_S_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE    (MXC_V_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS)

#define MXC_F_ADC_STATUS_OVERFLOW_POS                  3

#define MXC_F_ADC_STATUS_OVERFLOW                      ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS))

#define MXC_V_ADC_STATUS_OVERFLOW_UNDERFLOW            ((uint32_t)0x0UL)

#define MXC_S_ADC_STATUS_OVERFLOW_UNDERFLOW            (MXC_V_ADC_STATUS_OVERFLOW_UNDERFLOW << MXC_F_ADC_STATUS_OVERFLOW_POS)

#define MXC_V_ADC_STATUS_OVERFLOW_OVERFLOW             ((uint32_t)0x1UL)

#define MXC_S_ADC_STATUS_OVERFLOW_OVERFLOW             (MXC_V_ADC_STATUS_OVERFLOW_OVERFLOW << MXC_F_ADC_STATUS_OVERFLOW_POS)

#define MXC_F_ADC_DATA_DATA_POS                        0

#define MXC_F_ADC_DATA_DATA                            ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS))

#define MXC_F_ADC_INTR_DONE_IE_POS                     0

#define MXC_F_ADC_INTR_DONE_IE                         ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS))

#define MXC_V_ADC_INTR_DONE_IE_DIS                     ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_DONE_IE_DIS                     (MXC_V_ADC_INTR_DONE_IE_DIS << MXC_F_ADC_INTR_DONE_IE_POS)

#define MXC_V_ADC_INTR_DONE_IE_EN                      ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_DONE_IE_EN                      (MXC_V_ADC_INTR_DONE_IE_EN << MXC_F_ADC_INTR_DONE_IE_POS)

#define MXC_F_ADC_INTR_REF_READY_IE_POS                1

#define MXC_F_ADC_INTR_REF_READY_IE                    ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS))

#define MXC_V_ADC_INTR_REF_READY_IE_DIS                ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_REF_READY_IE_DIS                (MXC_V_ADC_INTR_REF_READY_IE_DIS << MXC_F_ADC_INTR_REF_READY_IE_POS)

#define MXC_V_ADC_INTR_REF_READY_IE_EN                 ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_REF_READY_IE_EN                 (MXC_V_ADC_INTR_REF_READY_IE_EN << MXC_F_ADC_INTR_REF_READY_IE_POS)

#define MXC_F_ADC_INTR_HI_LIMIT_IE_POS                 2

#define MXC_F_ADC_INTR_HI_LIMIT_IE                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS))

#define MXC_V_ADC_INTR_HI_LIMIT_IE_DIS                 ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_HI_LIMIT_IE_DIS                 (MXC_V_ADC_INTR_HI_LIMIT_IE_DIS << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)

#define MXC_V_ADC_INTR_HI_LIMIT_IE_EN                  ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_HI_LIMIT_IE_EN                  (MXC_V_ADC_INTR_HI_LIMIT_IE_EN << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)

#define MXC_F_ADC_INTR_LO_LIMIT_IE_POS                 3

#define MXC_F_ADC_INTR_LO_LIMIT_IE                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS))

#define MXC_V_ADC_INTR_LO_LIMIT_IE_DIS                 ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_LO_LIMIT_IE_DIS                 (MXC_V_ADC_INTR_LO_LIMIT_IE_DIS << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)

#define MXC_V_ADC_INTR_LO_LIMIT_IE_EN                  ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_LO_LIMIT_IE_EN                  (MXC_V_ADC_INTR_LO_LIMIT_IE_EN << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)

#define MXC_F_ADC_INTR_OVERFLOW_IE_POS                 4

#define MXC_F_ADC_INTR_OVERFLOW_IE                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS))

#define MXC_V_ADC_INTR_OVERFLOW_IE_DIS                 ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_OVERFLOW_IE_DIS                 (MXC_V_ADC_INTR_OVERFLOW_IE_DIS << MXC_F_ADC_INTR_OVERFLOW_IE_POS)

#define MXC_V_ADC_INTR_OVERFLOW_IE_EN                  ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_OVERFLOW_IE_EN                  (MXC_V_ADC_INTR_OVERFLOW_IE_EN << MXC_F_ADC_INTR_OVERFLOW_IE_POS)

#define MXC_F_ADC_INTR_DONE_IF_POS                     16

#define MXC_F_ADC_INTR_DONE_IF                         ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS))

#define MXC_V_ADC_INTR_DONE_IF_INACTIVE                ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_DONE_IF_INACTIVE                (MXC_V_ADC_INTR_DONE_IF_INACTIVE << MXC_F_ADC_INTR_DONE_IF_POS)

#define MXC_V_ADC_INTR_DONE_IF_ACTIVE                  ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_DONE_IF_ACTIVE                  (MXC_V_ADC_INTR_DONE_IF_ACTIVE << MXC_F_ADC_INTR_DONE_IF_POS)

#define MXC_F_ADC_INTR_REF_READY_IF_POS                17

#define MXC_F_ADC_INTR_REF_READY_IF                    ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS))

#define MXC_V_ADC_INTR_REF_READY_IF_INACTIVE           ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_REF_READY_IF_INACTIVE           (MXC_V_ADC_INTR_REF_READY_IF_INACTIVE << MXC_F_ADC_INTR_REF_READY_IF_POS)

#define MXC_V_ADC_INTR_REF_READY_IF_ACTIVE             ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_REF_READY_IF_ACTIVE             (MXC_V_ADC_INTR_REF_READY_IF_ACTIVE << MXC_F_ADC_INTR_REF_READY_IF_POS)

#define MXC_F_ADC_INTR_HI_LIMIT_IF_POS                 18

#define MXC_F_ADC_INTR_HI_LIMIT_IF                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS))

#define MXC_V_ADC_INTR_HI_LIMIT_IF_INACTIVE            ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_HI_LIMIT_IF_INACTIVE            (MXC_V_ADC_INTR_HI_LIMIT_IF_INACTIVE << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)

#define MXC_V_ADC_INTR_HI_LIMIT_IF_ACTIVE              ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_HI_LIMIT_IF_ACTIVE              (MXC_V_ADC_INTR_HI_LIMIT_IF_ACTIVE << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)

#define MXC_F_ADC_INTR_LO_LIMIT_IF_POS                 19

#define MXC_F_ADC_INTR_LO_LIMIT_IF                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS))

#define MXC_V_ADC_INTR_LO_LIMIT_IF_INACTIVE            ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_LO_LIMIT_IF_INACTIVE            (MXC_V_ADC_INTR_LO_LIMIT_IF_INACTIVE << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)

#define MXC_V_ADC_INTR_LO_LIMIT_IF_ACTIVE              ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_LO_LIMIT_IF_ACTIVE              (MXC_V_ADC_INTR_LO_LIMIT_IF_ACTIVE << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)

#define MXC_F_ADC_INTR_OVERFLOW_IF_POS                 20

#define MXC_F_ADC_INTR_OVERFLOW_IF                     ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS))

#define MXC_V_ADC_INTR_OVERFLOW_IF_INACTIVE            ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_OVERFLOW_IF_INACTIVE            (MXC_V_ADC_INTR_OVERFLOW_IF_INACTIVE << MXC_F_ADC_INTR_OVERFLOW_IF_POS)

#define MXC_V_ADC_INTR_OVERFLOW_IF_ACTIVE              ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_OVERFLOW_IF_ACTIVE              (MXC_V_ADC_INTR_OVERFLOW_IF_ACTIVE << MXC_F_ADC_INTR_OVERFLOW_IF_POS)

#define MXC_F_ADC_INTR_PENDING_POS                     22

#define MXC_F_ADC_INTR_PENDING                         ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS))

#define MXC_V_ADC_INTR_PENDING_NO_INT                  ((uint32_t)0x0UL)

#define MXC_S_ADC_INTR_PENDING_NO_INT                  (MXC_V_ADC_INTR_PENDING_NO_INT << MXC_F_ADC_INTR_PENDING_POS)

#define MXC_V_ADC_INTR_PENDING_INT_PENDING             ((uint32_t)0x1UL)

#define MXC_S_ADC_INTR_PENDING_INT_PENDING             (MXC_V_ADC_INTR_PENDING_INT_PENDING << MXC_F_ADC_INTR_PENDING_POS)

#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS                0

#define MXC_F_ADC_LIMIT_CH_LO_LIMIT                    ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS))

#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS                12

#define MXC_F_ADC_LIMIT_CH_HI_LIMIT                    ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS))

#define MXC_F_ADC_LIMIT_CH_SEL_POS                     24

#define MXC_F_ADC_LIMIT_CH_SEL                         ((uint32_t)(0xFUL << MXC_F_ADC_LIMIT_CH_SEL_POS))

#define MXC_V_ADC_LIMIT_CH_SEL_AIN0                    ((uint32_t)0x0UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN0                    (MXC_V_ADC_LIMIT_CH_SEL_AIN0 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN1                    ((uint32_t)0x1UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN1                    (MXC_V_ADC_LIMIT_CH_SEL_AIN1 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN2                    ((uint32_t)0x2UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN2                    (MXC_V_ADC_LIMIT_CH_SEL_AIN2 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN3                    ((uint32_t)0x3UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN3                    (MXC_V_ADC_LIMIT_CH_SEL_AIN3 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN4                    ((uint32_t)0x4UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN4                    (MXC_V_ADC_LIMIT_CH_SEL_AIN4 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN5                    ((uint32_t)0x5UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN5                    (MXC_V_ADC_LIMIT_CH_SEL_AIN5 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN6                    ((uint32_t)0x6UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN6                    (MXC_V_ADC_LIMIT_CH_SEL_AIN6 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN7                    ((uint32_t)0x7UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN7                    (MXC_V_ADC_LIMIT_CH_SEL_AIN7 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN8                    ((uint32_t)0x8UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN8                    (MXC_V_ADC_LIMIT_CH_SEL_AIN8 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN9                    ((uint32_t)0x9UL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN9                    (MXC_V_ADC_LIMIT_CH_SEL_AIN9 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN10                   ((uint32_t)0xAUL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN10                   (MXC_V_ADC_LIMIT_CH_SEL_AIN10 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN11                   ((uint32_t)0xBUL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN11                   (MXC_V_ADC_LIMIT_CH_SEL_AIN11 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_V_ADC_LIMIT_CH_SEL_AIN12                   ((uint32_t)0xCUL)

#define MXC_S_ADC_LIMIT_CH_SEL_AIN12                   (MXC_V_ADC_LIMIT_CH_SEL_AIN12 << MXC_F_ADC_LIMIT_CH_SEL_POS)

#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS             28

#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN                 ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS))

#define MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_DIS             ((uint32_t)0x0UL)

#define MXC_S_ADC_LIMIT_CH_LO_LIMIT_EN_DIS             (MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_DIS << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)

#define MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_EN              ((uint32_t)0x1UL)

#define MXC_S_ADC_LIMIT_CH_LO_LIMIT_EN_EN              (MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_EN << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)

#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS             29

#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN                 ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS))

#define MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_DIS             ((uint32_t)0x0UL)

#define MXC_S_ADC_LIMIT_CH_HI_LIMIT_EN_DIS             (MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_DIS << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)

#define MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_EN              ((uint32_t)0x1UL)

#define MXC_S_ADC_LIMIT_CH_HI_LIMIT_EN_EN              (MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_EN << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_

mxc_adc_regs_t::data
__IO uint32_t data
Definition: adc_regs.h:79

mxc_adc_regs_t::ctrl
__IO uint32_t ctrl
Definition: adc_regs.h:77

mxc_adc_regs_t::intr
__IO uint32_t intr
Definition: adc_regs.h:80

mxc_adc_regs_t::status
__IO uint32_t status
Definition: adc_regs.h:78

mxc_adc_regs_t
Definition: adc_regs.h:76