Documentation/MAX32650/clcd__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    __IO uint32_t clk_ctrl;

    __IO uint32_t vtim_0;

    __IO uint32_t vtim_1;

    __IO uint32_t htim;

    __IO uint32_t ctrl;

    __R  uint32_t rsv_0x14;

    __IO uint32_t frbuf;

    __R  uint32_t rsv_0x1c;

    __IO uint32_t int_en;

    __IO uint32_t int_stat;

    __R  uint32_t rsv_0x28_0x3ff[246];

    __IO uint32_t palette_ram[256];

} mxc_clcd_regs_t;


/* Register offsets for module CLCD */

#define MXC_R_CLCD_CLK_CTRL                ((uint32_t)0x00000000UL)

#define MXC_R_CLCD_VTIM_0                  ((uint32_t)0x00000004UL)

#define MXC_R_CLCD_VTIM_1                  ((uint32_t)0x00000008UL)

#define MXC_R_CLCD_HTIM                    ((uint32_t)0x0000000CUL)

#define MXC_R_CLCD_CTRL                    ((uint32_t)0x00000010UL)

#define MXC_R_CLCD_FRBUF                   ((uint32_t)0x00000018UL)

#define MXC_R_CLCD_INT_EN                  ((uint32_t)0x00000020UL)

#define MXC_R_CLCD_INT_STAT                ((uint32_t)0x00000024UL)

#define MXC_R_CLCD_PALETTE_RAM             ((uint32_t)0x00000400UL)

#define MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV_POS             0

#define MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV                 ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_CTRL_LCD_CLKDIV_POS))

#define MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS_POS            8

#define MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS                ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_CTRL_STN_AC_BIAS_POS))

#define MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS               16

#define MXC_F_CLCD_CLK_CTRL_VDEN_POL                   ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS))

#define MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO          ((uint32_t)0x0UL)

#define MXC_S_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO          (MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS)

#define MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI          ((uint32_t)0x1UL)

#define MXC_S_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI          (MXC_V_CLCD_CLK_CTRL_VDEN_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_VDEN_POL_POS)

#define MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS              17

#define MXC_F_CLCD_CLK_CTRL_VSYNC_POL                  ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS))

#define MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO         ((uint32_t)0x0UL)

#define MXC_S_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO         (MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS)

#define MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI         ((uint32_t)0x1UL)

#define MXC_S_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI         (MXC_V_CLCD_CLK_CTRL_VSYNC_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_VSYNC_POL_POS)

#define MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS              18

#define MXC_F_CLCD_CLK_CTRL_HSYNC_POL                  ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS))

#define MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO         ((uint32_t)0x0UL)

#define MXC_S_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO         (MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVELO << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS)

#define MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI         ((uint32_t)0x1UL)

#define MXC_S_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI         (MXC_V_CLCD_CLK_CTRL_HSYNC_POL_ACTIVEHI << MXC_F_CLCD_CLK_CTRL_HSYNC_POL_POS)

#define MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS           19

#define MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL               ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS))

#define MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING        ((uint32_t)0x0UL)

#define MXC_S_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING        (MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_RISING << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS)

#define MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING       ((uint32_t)0x1UL)

#define MXC_S_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING       (MXC_V_CLCD_CLK_CTRL_CLK_EDGE_SEL_FALLING << MXC_F_CLCD_CLK_CTRL_CLK_EDGE_SEL_POS)

#define MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS             20

#define MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE                 ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS))

#define MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS          ((uint32_t)0x0UL)

#define MXC_S_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS          (MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ALWAYS << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS)

#define MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA          ((uint32_t)0x1UL)

#define MXC_S_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA          (MXC_V_CLCD_CLK_CTRL_CLK_ACTIVE_ONDATA << MXC_F_CLCD_CLK_CTRL_CLK_ACTIVE_POS)

#define MXC_F_CLCD_VTIM_0_VLINES_POS                   0

#define MXC_F_CLCD_VTIM_0_VLINES                       ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VLINES_POS))

#define MXC_F_CLCD_VTIM_0_VBP_WIDTH_POS                16

#define MXC_F_CLCD_VTIM_0_VBP_WIDTH                    ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VBP_WIDTH_POS))

#define MXC_F_CLCD_VTIM_1_VSYNC_WIDTH_POS              0

#define MXC_F_CLCD_VTIM_1_VSYNC_WIDTH                  ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VSYNC_WIDTH_POS))

#define MXC_F_CLCD_VTIM_1_VFP_WIDTH_POS                16

#define MXC_F_CLCD_VTIM_1_VFP_WIDTH                    ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VFP_WIDTH_POS))

#define MXC_F_CLCD_HTIM_HSYNC_WIDTH_POS                0

#define MXC_F_CLCD_HTIM_HSYNC_WIDTH                    ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSYNC_WIDTH_POS))

#define MXC_F_CLCD_HTIM_HFP_WIDTH_POS                  8

#define MXC_F_CLCD_HTIM_HFP_WIDTH                      ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HFP_WIDTH_POS))

#define MXC_F_CLCD_HTIM_HSIZE_INDEX_POS                16

#define MXC_F_CLCD_HTIM_HSIZE_INDEX                    ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSIZE_INDEX_POS))

#define MXC_F_CLCD_HTIM_HBP_WIDTH_POS                  24

#define MXC_F_CLCD_HTIM_HBP_WIDTH                      ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HBP_WIDTH_POS))

#define MXC_F_CLCD_CTRL_CLCD_ENABLE_POS                0

#define MXC_F_CLCD_CTRL_CLCD_ENABLE                    ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS))

#define MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS                ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_CLCD_ENABLE_DIS                (MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS)

#define MXC_V_CLCD_CTRL_CLCD_ENABLE_EN                 ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_CLCD_ENABLE_EN                 (MXC_V_CLCD_CTRL_CLCD_ENABLE_EN << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS)

#define MXC_F_CLCD_CTRL_VCI_SEL_POS                    1

#define MXC_F_CLCD_CTRL_VCI_SEL                        ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_VCI_SEL_POS))

#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC               ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VSYNC               (MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC << MXC_F_CLCD_CTRL_VCI_SEL_POS)

#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP                 ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VBP                 (MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP << MXC_F_CLCD_CTRL_VCI_SEL_POS)

#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN                ((uint32_t)0x2UL)

#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VDEN                (MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN << MXC_F_CLCD_CTRL_VCI_SEL_POS)

#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP                 ((uint32_t)0x3UL)

#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VFP                 (MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP << MXC_F_CLCD_CTRL_VCI_SEL_POS)

#define MXC_F_CLCD_CTRL_DISPTYPE_POS                   4

#define MXC_F_CLCD_CTRL_DISPTYPE                       ((uint32_t)(0xFUL << MXC_F_CLCD_CTRL_DISPTYPE_POS))

#define MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN          ((uint32_t)0x4UL)

#define MXC_S_CLCD_CTRL_DISPTYPE_8BITCOLORSTN          (MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN << MXC_F_CLCD_CTRL_DISPTYPE_POS)

#define MXC_V_CLCD_CTRL_DISPTYPE_TFT                   ((uint32_t)0x8UL)

#define MXC_S_CLCD_CTRL_DISPTYPE_TFT                   (MXC_V_CLCD_CTRL_DISPTYPE_TFT << MXC_F_CLCD_CTRL_DISPTYPE_POS)

#define MXC_F_CLCD_CTRL_BPP_POS                        8

#define MXC_F_CLCD_CTRL_BPP                            ((uint32_t)(0x7UL << MXC_F_CLCD_CTRL_BPP_POS))

#define MXC_V_CLCD_CTRL_BPP_BPP1                       ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_BPP_BPP1                       (MXC_V_CLCD_CTRL_BPP_BPP1 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_V_CLCD_CTRL_BPP_BPP2                       ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_BPP_BPP2                       (MXC_V_CLCD_CTRL_BPP_BPP2 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_V_CLCD_CTRL_BPP_BPP4                       ((uint32_t)0x2UL)

#define MXC_S_CLCD_CTRL_BPP_BPP4                       (MXC_V_CLCD_CTRL_BPP_BPP4 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_V_CLCD_CTRL_BPP_BPP8                       ((uint32_t)0x3UL)

#define MXC_S_CLCD_CTRL_BPP_BPP8                       (MXC_V_CLCD_CTRL_BPP_BPP8 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_V_CLCD_CTRL_BPP_BPP16                      ((uint32_t)0x4UL)

#define MXC_S_CLCD_CTRL_BPP_BPP16                      (MXC_V_CLCD_CTRL_BPP_BPP16 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_V_CLCD_CTRL_BPP_BPP24                      ((uint32_t)0x5UL)

#define MXC_S_CLCD_CTRL_BPP_BPP24                      (MXC_V_CLCD_CTRL_BPP_BPP24 << MXC_F_CLCD_CTRL_BPP_POS)

#define MXC_F_CLCD_CTRL_MODE565_POS                    11

#define MXC_F_CLCD_CTRL_MODE565                        ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_MODE565_POS))

#define MXC_V_CLCD_CTRL_MODE565_BGR556                 ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_MODE565_BGR556                 (MXC_V_CLCD_CTRL_MODE565_BGR556 << MXC_F_CLCD_CTRL_MODE565_POS)

#define MXC_V_CLCD_CTRL_MODE565_RGB565                 ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_MODE565_RGB565                 (MXC_V_CLCD_CTRL_MODE565_RGB565 << MXC_F_CLCD_CTRL_MODE565_POS)

#define MXC_F_CLCD_CTRL_ENDIAN_POS                     12

#define MXC_F_CLCD_CTRL_ENDIAN                         ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_ENDIAN_POS))

#define MXC_V_CLCD_CTRL_ENDIAN_LBLP                    ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_ENDIAN_LBLP                    (MXC_V_CLCD_CTRL_ENDIAN_LBLP << MXC_F_CLCD_CTRL_ENDIAN_POS)

#define MXC_V_CLCD_CTRL_ENDIAN_BBBP                    ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_ENDIAN_BBBP                    (MXC_V_CLCD_CTRL_ENDIAN_BBBP << MXC_F_CLCD_CTRL_ENDIAN_POS)

#define MXC_V_CLCD_CTRL_ENDIAN_LBBP                    ((uint32_t)0x2UL)

#define MXC_S_CLCD_CTRL_ENDIAN_LBBP                    (MXC_V_CLCD_CTRL_ENDIAN_LBBP << MXC_F_CLCD_CTRL_ENDIAN_POS)

#define MXC_V_CLCD_CTRL_ENDIAN_RFU                     ((uint32_t)0x3UL)

#define MXC_S_CLCD_CTRL_ENDIAN_RFU                     (MXC_V_CLCD_CTRL_ENDIAN_RFU << MXC_F_CLCD_CTRL_ENDIAN_POS)

#define MXC_F_CLCD_CTRL_COMPACT_24B_POS                15

#define MXC_F_CLCD_CTRL_COMPACT_24B                    ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_COMPACT_24B_POS))

#define MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR              ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_COMPACT_24B_1_PFR              (MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS)

#define MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR       ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR       (MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS)

#define MXC_F_CLCD_CTRL_BURST_SIZE_POS                 19

#define MXC_F_CLCD_CTRL_BURST_SIZE                     ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_BURST_SIZE_POS))

#define MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS              ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_BURST_SIZE_4WORDS              (MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS)

#define MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS              ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_BURST_SIZE_8WORDS              (MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS)

#define MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS             ((uint32_t)0x2UL)

#define MXC_S_CLCD_CTRL_BURST_SIZE_16WORDS             (MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS)

#define MXC_F_CLCD_CTRL_LEND_POL_POS                   21

#define MXC_F_CLCD_CTRL_LEND_POL                       ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_LEND_POL_POS))

#define MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO              ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_LEND_POL_ACTIVELO              (MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO << MXC_F_CLCD_CTRL_LEND_POL_POS)

#define MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI              ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_LEND_POL_ACTIVEHI              (MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI << MXC_F_CLCD_CTRL_LEND_POL_POS)

#define MXC_F_CLCD_CTRL_PWR_ENABLE_POS                 22

#define MXC_F_CLCD_CTRL_PWR_ENABLE                     ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_PWR_ENABLE_POS))

#define MXC_V_CLCD_CTRL_PWR_ENABLE_LO                  ((uint32_t)0x0UL)

#define MXC_S_CLCD_CTRL_PWR_ENABLE_LO                  (MXC_V_CLCD_CTRL_PWR_ENABLE_LO << MXC_F_CLCD_CTRL_PWR_ENABLE_POS)

#define MXC_V_CLCD_CTRL_PWR_ENABLE_HI                  ((uint32_t)0x1UL)

#define MXC_S_CLCD_CTRL_PWR_ENABLE_HI                  (MXC_V_CLCD_CTRL_PWR_ENABLE_HI << MXC_F_CLCD_CTRL_PWR_ENABLE_POS)

#define MXC_F_CLCD_FRBUF_FRAME_ADDR_POS                0

#define MXC_F_CLCD_FRBUF_FRAME_ADDR                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLCD_FRBUF_FRAME_ADDR_POS))

#define MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS             0

#define MXC_F_CLCD_INT_EN_UNDERFLOW_IE                 ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS))

#define MXC_V_CLCD_INT_EN_UNDERFLOW_IE_DIS             ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_EN_UNDERFLOW_IE_DIS             (MXC_V_CLCD_INT_EN_UNDERFLOW_IE_DIS << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS)

#define MXC_V_CLCD_INT_EN_UNDERFLOW_IE_EN              ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_EN_UNDERFLOW_IE_EN              (MXC_V_CLCD_INT_EN_UNDERFLOW_IE_EN << MXC_F_CLCD_INT_EN_UNDERFLOW_IE_POS)

#define MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS              1

#define MXC_F_CLCD_INT_EN_ADDR_RDY_IE                  ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS))

#define MXC_V_CLCD_INT_EN_ADDR_RDY_IE_DIS              ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_EN_ADDR_RDY_IE_DIS              (MXC_V_CLCD_INT_EN_ADDR_RDY_IE_DIS << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS)

#define MXC_V_CLCD_INT_EN_ADDR_RDY_IE_EN               ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_EN_ADDR_RDY_IE_EN               (MXC_V_CLCD_INT_EN_ADDR_RDY_IE_EN << MXC_F_CLCD_INT_EN_ADDR_RDY_IE_POS)

#define MXC_F_CLCD_INT_EN_VCI_IE_POS                   2

#define MXC_F_CLCD_INT_EN_VCI_IE                       ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_VCI_IE_POS))

#define MXC_V_CLCD_INT_EN_VCI_IE_DIS                   ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_EN_VCI_IE_DIS                   (MXC_V_CLCD_INT_EN_VCI_IE_DIS << MXC_F_CLCD_INT_EN_VCI_IE_POS)

#define MXC_V_CLCD_INT_EN_VCI_IE_EN                    ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_EN_VCI_IE_EN                    (MXC_V_CLCD_INT_EN_VCI_IE_EN << MXC_F_CLCD_INT_EN_VCI_IE_POS)

#define MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS             3

#define MXC_F_CLCD_INT_EN_BUS_ERROR_IE                 ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS))

#define MXC_V_CLCD_INT_EN_BUS_ERROR_IE_DIS             ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_EN_BUS_ERROR_IE_DIS             (MXC_V_CLCD_INT_EN_BUS_ERROR_IE_DIS << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS)

#define MXC_V_CLCD_INT_EN_BUS_ERROR_IE_EN              ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_EN_BUS_ERROR_IE_EN              (MXC_V_CLCD_INT_EN_BUS_ERROR_IE_EN << MXC_F_CLCD_INT_EN_BUS_ERROR_IE_POS)

#define MXC_F_CLCD_INT_STAT_UNDERFLOW_POS              0

#define MXC_F_CLCD_INT_STAT_UNDERFLOW                  ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS))

#define MXC_V_CLCD_INT_STAT_UNDERFLOW_INACTIVE         ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_STAT_UNDERFLOW_INACTIVE         (MXC_V_CLCD_INT_STAT_UNDERFLOW_INACTIVE << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS)

#define MXC_V_CLCD_INT_STAT_UNDERFLOW_PEND             ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_UNDERFLOW_PEND             (MXC_V_CLCD_INT_STAT_UNDERFLOW_PEND << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS)

#define MXC_V_CLCD_INT_STAT_UNDERFLOW_CLEAR            ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_UNDERFLOW_CLEAR            (MXC_V_CLCD_INT_STAT_UNDERFLOW_CLEAR << MXC_F_CLCD_INT_STAT_UNDERFLOW_POS)

#define MXC_F_CLCD_INT_STAT_ADDR_RDY_POS               1

#define MXC_F_CLCD_INT_STAT_ADDR_RDY                   ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS))

#define MXC_V_CLCD_INT_STAT_ADDR_RDY_INACTIVE          ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_STAT_ADDR_RDY_INACTIVE          (MXC_V_CLCD_INT_STAT_ADDR_RDY_INACTIVE << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS)

#define MXC_V_CLCD_INT_STAT_ADDR_RDY_PEND              ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_ADDR_RDY_PEND              (MXC_V_CLCD_INT_STAT_ADDR_RDY_PEND << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS)

#define MXC_V_CLCD_INT_STAT_ADDR_RDY_CLEAR             ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_ADDR_RDY_CLEAR             (MXC_V_CLCD_INT_STAT_ADDR_RDY_CLEAR << MXC_F_CLCD_INT_STAT_ADDR_RDY_POS)

#define MXC_F_CLCD_INT_STAT_VCI_POS                    2

#define MXC_F_CLCD_INT_STAT_VCI                        ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_VCI_POS))

#define MXC_V_CLCD_INT_STAT_VCI_INACTIVE               ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_STAT_VCI_INACTIVE               (MXC_V_CLCD_INT_STAT_VCI_INACTIVE << MXC_F_CLCD_INT_STAT_VCI_POS)

#define MXC_V_CLCD_INT_STAT_VCI_PEND                   ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_VCI_PEND                   (MXC_V_CLCD_INT_STAT_VCI_PEND << MXC_F_CLCD_INT_STAT_VCI_POS)

#define MXC_V_CLCD_INT_STAT_VCI_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_VCI_CLEAR                  (MXC_V_CLCD_INT_STAT_VCI_CLEAR << MXC_F_CLCD_INT_STAT_VCI_POS)

#define MXC_F_CLCD_INT_STAT_BUS_ERROR_POS              3

#define MXC_F_CLCD_INT_STAT_BUS_ERROR                  ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS))

#define MXC_V_CLCD_INT_STAT_BUS_ERROR_INACTIVE         ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_STAT_BUS_ERROR_INACTIVE         (MXC_V_CLCD_INT_STAT_BUS_ERROR_INACTIVE << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS)

#define MXC_V_CLCD_INT_STAT_BUS_ERROR_PEND             ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_BUS_ERROR_PEND             (MXC_V_CLCD_INT_STAT_BUS_ERROR_PEND << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS)

#define MXC_V_CLCD_INT_STAT_BUS_ERROR_CLEAR            ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_BUS_ERROR_CLEAR            (MXC_V_CLCD_INT_STAT_BUS_ERROR_CLEAR << MXC_F_CLCD_INT_STAT_BUS_ERROR_POS)

#define MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS              8

#define MXC_F_CLCD_INT_STAT_CLCD_IDLE                  ((uint32_t)(0x1UL << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS))

#define MXC_V_CLCD_INT_STAT_CLCD_IDLE_IDLE             ((uint32_t)0x0UL)

#define MXC_S_CLCD_INT_STAT_CLCD_IDLE_IDLE             (MXC_V_CLCD_INT_STAT_CLCD_IDLE_IDLE << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS)

#define MXC_V_CLCD_INT_STAT_CLCD_IDLE_BUSY             ((uint32_t)0x1UL)

#define MXC_S_CLCD_INT_STAT_CLCD_IDLE_BUSY             (MXC_V_CLCD_INT_STAT_CLCD_IDLE_BUSY << MXC_F_CLCD_INT_STAT_CLCD_IDLE_POS)

#define MXC_F_CLCD_PALETTE_RAM_RED_POS                 0

#define MXC_F_CLCD_PALETTE_RAM_RED                     ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_RED_POS))

#define MXC_F_CLCD_PALETTE_RAM_GREEN_POS               8

#define MXC_F_CLCD_PALETTE_RAM_GREEN                   ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_GREEN_POS))

#define MXC_F_CLCD_PALETTE_RAM_BLUE_POS                16

#define MXC_F_CLCD_PALETTE_RAM_BLUE                    ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RAM_BLUE_POS))

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_CLCD_REGS_H_

mxc_clcd_regs_t::int_en
__IO uint32_t int_en
Definition: clcd_regs.h:85

mxc_clcd_regs_t::ctrl
__IO uint32_t ctrl
Definition: clcd_regs.h:81

mxc_clcd_regs_t::vtim_0
__IO uint32_t vtim_0
Definition: clcd_regs.h:78

mxc_clcd_regs_t::frbuf
__IO uint32_t frbuf
Definition: clcd_regs.h:83

mxc_clcd_regs_t::vtim_1
__IO uint32_t vtim_1
Definition: clcd_regs.h:79

mxc_clcd_regs_t::clk_ctrl
__IO uint32_t clk_ctrl
Definition: clcd_regs.h:77

mxc_clcd_regs_t::int_stat
__IO uint32_t int_stat
Definition: clcd_regs.h:86

mxc_clcd_regs_t::htim
__IO uint32_t htim
Definition: clcd_regs.h:80

mxc_clcd_regs_t
Definition: clcd_regs.h:76