MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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SPI_CTRL2
SPI » SPI_Registers

Macros

#define MXC_F_SPI_CTRL2_CLK_PHA_POS   0
 
#define MXC_F_SPI_CTRL2_CLK_PHA   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS))
 
#define MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE   ((uint32_t)0x0UL)
 
#define MXC_S_SPI_CTRL2_CLK_PHA_RISINGEDGE   (MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)
 
#define MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_CLK_PHA_FALLINGEDGE   (MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)
 
#define MXC_F_SPI_CTRL2_CLK_POL_POS   1
 
#define MXC_F_SPI_CTRL2_CLK_POL   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS))
 
#define MXC_V_SPI_CTRL2_CLK_POL_NORMAL   ((uint32_t)0x0UL)
 
#define MXC_S_SPI_CTRL2_CLK_POL_NORMAL   (MXC_V_SPI_CTRL2_CLK_POL_NORMAL << MXC_F_SPI_CTRL2_CLK_POL_POS)
 
#define MXC_V_SPI_CTRL2_CLK_POL_INVERTED   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_CLK_POL_INVERTED   (MXC_V_SPI_CTRL2_CLK_POL_INVERTED << MXC_F_SPI_CTRL2_CLK_POL_POS)
 
#define MXC_F_SPI_CTRL2_NUM_BITS_POS   8
 
#define MXC_F_SPI_CTRL2_NUM_BITS   ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS))
 
#define MXC_V_SPI_CTRL2_NUM_BITS_16BITS   ((uint32_t)0x0UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_16BITS   (MXC_V_SPI_CTRL2_NUM_BITS_16BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_1BITS   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_1BITS   (MXC_V_SPI_CTRL2_NUM_BITS_1BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_2BITS   ((uint32_t)0x2UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_2BITS   (MXC_V_SPI_CTRL2_NUM_BITS_2BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_3BITS   ((uint32_t)0x3UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_3BITS   (MXC_V_SPI_CTRL2_NUM_BITS_3BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_4BITS   ((uint32_t)0x4UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_4BITS   (MXC_V_SPI_CTRL2_NUM_BITS_4BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_5BITS   ((uint32_t)0x5UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_5BITS   (MXC_V_SPI_CTRL2_NUM_BITS_5BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_6BITS   ((uint32_t)0x6UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_6BITS   (MXC_V_SPI_CTRL2_NUM_BITS_6BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_7BITS   ((uint32_t)0x7UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_7BITS   (MXC_V_SPI_CTRL2_NUM_BITS_7BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_8BITS   ((uint32_t)0x8UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_8BITS   (MXC_V_SPI_CTRL2_NUM_BITS_8BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_9BITS   ((uint32_t)0x9UL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_9BITS   (MXC_V_SPI_CTRL2_NUM_BITS_9BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_10BITS   ((uint32_t)0xAUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_10BITS   (MXC_V_SPI_CTRL2_NUM_BITS_10BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_11BITS   ((uint32_t)0xBUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_11BITS   (MXC_V_SPI_CTRL2_NUM_BITS_11BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_12BITS   ((uint32_t)0xCUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_12BITS   (MXC_V_SPI_CTRL2_NUM_BITS_12BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_13BITS   ((uint32_t)0xDUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_13BITS   (MXC_V_SPI_CTRL2_NUM_BITS_13BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_14BITS   ((uint32_t)0xEUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_14BITS   (MXC_V_SPI_CTRL2_NUM_BITS_14BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_V_SPI_CTRL2_NUM_BITS_15BITS   ((uint32_t)0xFUL)
 
#define MXC_S_SPI_CTRL2_NUM_BITS_15BITS   (MXC_V_SPI_CTRL2_NUM_BITS_15BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)
 
#define MXC_F_SPI_CTRL2_BUS_WIDTH_POS   12
 
#define MXC_F_SPI_CTRL2_BUS_WIDTH   ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS))
 
#define MXC_V_SPI_CTRL2_BUS_WIDTH_MONO   ((uint32_t)0x0UL)
 
#define MXC_S_SPI_CTRL2_BUS_WIDTH_MONO   (MXC_V_SPI_CTRL2_BUS_WIDTH_MONO << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)
 
#define MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_BUS_WIDTH_DUAL   (MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)
 
#define MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD   ((uint32_t)0x2UL)
 
#define MXC_S_SPI_CTRL2_BUS_WIDTH_QUAD   (MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)
 
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS   15
 
#define MXC_F_SPI_CTRL2_THREE_WIRE   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS))
 
#define MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE   ((uint32_t)0x0UL)
 
#define MXC_S_SPI_CTRL2_THREE_WIRE_4WIRE   (MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)
 
#define MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_THREE_WIRE_3WIRE   (MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)
 
#define MXC_F_SPI_CTRL2_SS_POL_POS   16
 
#define MXC_F_SPI_CTRL2_SS_POL   ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS))
 
#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH   ((uint32_t)0x1UL)
 
#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
 
#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH   ((uint32_t)0x2UL)
 
#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
 
#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH   ((uint32_t)0x4UL)
 
#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
 
#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH   ((uint32_t)0x8UL)
 
#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)
 

Detailed Description

Register for controlling SPI peripheral.

Macro Definition Documentation

◆ MXC_F_SPI_CTRL2_BUS_WIDTH

#define MXC_F_SPI_CTRL2_BUS_WIDTH   ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS))

CTRL2_BUS_WIDTH Mask

◆ MXC_F_SPI_CTRL2_BUS_WIDTH_POS

#define MXC_F_SPI_CTRL2_BUS_WIDTH_POS   12

CTRL2_BUS_WIDTH Position

◆ MXC_F_SPI_CTRL2_CLK_PHA

#define MXC_F_SPI_CTRL2_CLK_PHA   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS))

CTRL2_CLK_PHA Mask

◆ MXC_F_SPI_CTRL2_CLK_PHA_POS

#define MXC_F_SPI_CTRL2_CLK_PHA_POS   0

CTRL2_CLK_PHA Position

◆ MXC_F_SPI_CTRL2_CLK_POL

#define MXC_F_SPI_CTRL2_CLK_POL   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS))

CTRL2_CLK_POL Mask

◆ MXC_F_SPI_CTRL2_CLK_POL_POS

#define MXC_F_SPI_CTRL2_CLK_POL_POS   1

CTRL2_CLK_POL Position

◆ MXC_F_SPI_CTRL2_NUM_BITS

#define MXC_F_SPI_CTRL2_NUM_BITS   ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS))

CTRL2_NUM_BITS Mask

◆ MXC_F_SPI_CTRL2_NUM_BITS_POS

#define MXC_F_SPI_CTRL2_NUM_BITS_POS   8

CTRL2_NUM_BITS Position

◆ MXC_F_SPI_CTRL2_SS_POL

#define MXC_F_SPI_CTRL2_SS_POL   ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS))

CTRL2_SS_POL Mask

◆ MXC_F_SPI_CTRL2_SS_POL_POS

#define MXC_F_SPI_CTRL2_SS_POL_POS   16

CTRL2_SS_POL Position

◆ MXC_F_SPI_CTRL2_THREE_WIRE

#define MXC_F_SPI_CTRL2_THREE_WIRE   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS))

CTRL2_THREE_WIRE Mask

◆ MXC_F_SPI_CTRL2_THREE_WIRE_POS

#define MXC_F_SPI_CTRL2_THREE_WIRE_POS   15

CTRL2_THREE_WIRE Position

◆ MXC_S_SPI_CTRL2_BUS_WIDTH_DUAL

#define MXC_S_SPI_CTRL2_BUS_WIDTH_DUAL   (MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

CTRL2_BUS_WIDTH_DUAL Setting

◆ MXC_S_SPI_CTRL2_BUS_WIDTH_MONO

#define MXC_S_SPI_CTRL2_BUS_WIDTH_MONO   (MXC_V_SPI_CTRL2_BUS_WIDTH_MONO << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

CTRL2_BUS_WIDTH_MONO Setting

◆ MXC_S_SPI_CTRL2_BUS_WIDTH_QUAD

#define MXC_S_SPI_CTRL2_BUS_WIDTH_QUAD   (MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

CTRL2_BUS_WIDTH_QUAD Setting

◆ MXC_S_SPI_CTRL2_CLK_PHA_FALLINGEDGE

#define MXC_S_SPI_CTRL2_CLK_PHA_FALLINGEDGE   (MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)

CTRL2_CLK_PHA_FALLINGEDGE Setting

◆ MXC_S_SPI_CTRL2_CLK_PHA_RISINGEDGE

#define MXC_S_SPI_CTRL2_CLK_PHA_RISINGEDGE   (MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)

CTRL2_CLK_PHA_RISINGEDGE Setting

◆ MXC_S_SPI_CTRL2_CLK_POL_INVERTED

#define MXC_S_SPI_CTRL2_CLK_POL_INVERTED   (MXC_V_SPI_CTRL2_CLK_POL_INVERTED << MXC_F_SPI_CTRL2_CLK_POL_POS)

CTRL2_CLK_POL_INVERTED Setting

◆ MXC_S_SPI_CTRL2_CLK_POL_NORMAL

#define MXC_S_SPI_CTRL2_CLK_POL_NORMAL   (MXC_V_SPI_CTRL2_CLK_POL_NORMAL << MXC_F_SPI_CTRL2_CLK_POL_POS)

CTRL2_CLK_POL_NORMAL Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_10BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_10BITS   (MXC_V_SPI_CTRL2_NUM_BITS_10BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_10BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_11BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_11BITS   (MXC_V_SPI_CTRL2_NUM_BITS_11BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_11BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_12BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_12BITS   (MXC_V_SPI_CTRL2_NUM_BITS_12BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_12BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_13BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_13BITS   (MXC_V_SPI_CTRL2_NUM_BITS_13BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_13BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_14BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_14BITS   (MXC_V_SPI_CTRL2_NUM_BITS_14BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_14BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_15BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_15BITS   (MXC_V_SPI_CTRL2_NUM_BITS_15BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_15BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_16BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_16BITS   (MXC_V_SPI_CTRL2_NUM_BITS_16BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_16BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_1BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_1BITS   (MXC_V_SPI_CTRL2_NUM_BITS_1BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_1BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_2BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_2BITS   (MXC_V_SPI_CTRL2_NUM_BITS_2BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_2BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_3BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_3BITS   (MXC_V_SPI_CTRL2_NUM_BITS_3BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_3BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_4BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_4BITS   (MXC_V_SPI_CTRL2_NUM_BITS_4BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_4BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_5BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_5BITS   (MXC_V_SPI_CTRL2_NUM_BITS_5BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_5BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_6BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_6BITS   (MXC_V_SPI_CTRL2_NUM_BITS_6BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_6BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_7BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_7BITS   (MXC_V_SPI_CTRL2_NUM_BITS_7BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_7BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_8BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_8BITS   (MXC_V_SPI_CTRL2_NUM_BITS_8BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_8BITS Setting

◆ MXC_S_SPI_CTRL2_NUM_BITS_9BITS

#define MXC_S_SPI_CTRL2_NUM_BITS_9BITS   (MXC_V_SPI_CTRL2_NUM_BITS_9BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

CTRL2_NUM_BITS_9BITS Setting

◆ MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH

#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

CTRL2_SS_POL_SS0_HIGH Setting

◆ MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH

#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

CTRL2_SS_POL_SS1_HIGH Setting

◆ MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH

#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

CTRL2_SS_POL_SS2_HIGH Setting

◆ MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH

#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH   (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

CTRL2_SS_POL_SS3_HIGH Setting

◆ MXC_S_SPI_CTRL2_THREE_WIRE_3WIRE

#define MXC_S_SPI_CTRL2_THREE_WIRE_3WIRE   (MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)

CTRL2_THREE_WIRE_3WIRE Setting

◆ MXC_S_SPI_CTRL2_THREE_WIRE_4WIRE

#define MXC_S_SPI_CTRL2_THREE_WIRE_4WIRE   (MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)

CTRL2_THREE_WIRE_4WIRE Setting

◆ MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL

#define MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL   ((uint32_t)0x1UL)

CTRL2_BUS_WIDTH_DUAL Value

◆ MXC_V_SPI_CTRL2_BUS_WIDTH_MONO

#define MXC_V_SPI_CTRL2_BUS_WIDTH_MONO   ((uint32_t)0x0UL)

CTRL2_BUS_WIDTH_MONO Value

◆ MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD

#define MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD   ((uint32_t)0x2UL)

CTRL2_BUS_WIDTH_QUAD Value

◆ MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE

#define MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE   ((uint32_t)0x1UL)

CTRL2_CLK_PHA_FALLINGEDGE Value

◆ MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE

#define MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE   ((uint32_t)0x0UL)

CTRL2_CLK_PHA_RISINGEDGE Value

◆ MXC_V_SPI_CTRL2_CLK_POL_INVERTED

#define MXC_V_SPI_CTRL2_CLK_POL_INVERTED   ((uint32_t)0x1UL)

CTRL2_CLK_POL_INVERTED Value

◆ MXC_V_SPI_CTRL2_CLK_POL_NORMAL

#define MXC_V_SPI_CTRL2_CLK_POL_NORMAL   ((uint32_t)0x0UL)

CTRL2_CLK_POL_NORMAL Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_10BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_10BITS   ((uint32_t)0xAUL)

CTRL2_NUM_BITS_10BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_11BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_11BITS   ((uint32_t)0xBUL)

CTRL2_NUM_BITS_11BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_12BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_12BITS   ((uint32_t)0xCUL)

CTRL2_NUM_BITS_12BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_13BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_13BITS   ((uint32_t)0xDUL)

CTRL2_NUM_BITS_13BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_14BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_14BITS   ((uint32_t)0xEUL)

CTRL2_NUM_BITS_14BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_15BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_15BITS   ((uint32_t)0xFUL)

CTRL2_NUM_BITS_15BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_16BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_16BITS   ((uint32_t)0x0UL)

CTRL2_NUM_BITS_16BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_1BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_1BITS   ((uint32_t)0x1UL)

CTRL2_NUM_BITS_1BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_2BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_2BITS   ((uint32_t)0x2UL)

CTRL2_NUM_BITS_2BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_3BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_3BITS   ((uint32_t)0x3UL)

CTRL2_NUM_BITS_3BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_4BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_4BITS   ((uint32_t)0x4UL)

CTRL2_NUM_BITS_4BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_5BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_5BITS   ((uint32_t)0x5UL)

CTRL2_NUM_BITS_5BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_6BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_6BITS   ((uint32_t)0x6UL)

CTRL2_NUM_BITS_6BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_7BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_7BITS   ((uint32_t)0x7UL)

CTRL2_NUM_BITS_7BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_8BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_8BITS   ((uint32_t)0x8UL)

CTRL2_NUM_BITS_8BITS Value

◆ MXC_V_SPI_CTRL2_NUM_BITS_9BITS

#define MXC_V_SPI_CTRL2_NUM_BITS_9BITS   ((uint32_t)0x9UL)

CTRL2_NUM_BITS_9BITS Value

◆ MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH

#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH   ((uint32_t)0x1UL)

CTRL2_SS_POL_SS0_HIGH Value

◆ MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH

#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH   ((uint32_t)0x2UL)

CTRL2_SS_POL_SS1_HIGH Value

◆ MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH

#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH   ((uint32_t)0x4UL)

CTRL2_SS_POL_SS2_HIGH Value

◆ MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH

#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH   ((uint32_t)0x8UL)

CTRL2_SS_POL_SS3_HIGH Value

◆ MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE

#define MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE   ((uint32_t)0x1UL)

CTRL2_THREE_WIRE_3WIRE Value

◆ MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE

#define MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE   ((uint32_t)0x0UL)

CTRL2_THREE_WIRE_4WIRE Value