Register Offsets

Macros
#define	MXC_R_TPU_CRYPTO_CTRL   ((uint32_t)0x00000000UL)
#define	MXC_R_TPU_CIPHER_CTRL   ((uint32_t)0x00000004UL)
#define	MXC_R_TPU_HASH_CTRL   ((uint32_t)0x00000008UL)
#define	MXC_R_TPU_CRC_CTRL   ((uint32_t)0x0000000CUL)
#define	MXC_R_TPU_DMA_SRC   ((uint32_t)0x00000010UL)
#define	MXC_R_TPU_DMA_DEST   ((uint32_t)0x00000014UL)
#define	MXC_R_TPU_DMA_CNT   ((uint32_t)0x00000018UL)
#define	MXC_R_TPU_MAA_CTRL   ((uint32_t)0x0000001CUL)
#define	MXC_R_TPU_CRYPTO_DIN   ((uint32_t)0x00000020UL)
#define	MXC_R_TPU_CRYPTO_DOUT   ((uint32_t)0x00000030UL)
#define	MXC_R_TPU_CRC_POLY   ((uint32_t)0x00000040UL)
#define	MXC_R_TPU_CRC_VAL   ((uint32_t)0x00000044UL)
#define	MXC_R_TPU_CRC_PRNG   ((uint32_t)0x00000048UL)
#define	MXC_R_TPU_HAM_ECC   ((uint32_t)0x0000004CUL)
#define	MXC_R_TPU_CIPHER_INIT   ((uint32_t)0x00000050UL)
#define	MXC_R_TPU_CIPHER_KEY   ((uint32_t)0x00000060UL)
#define	MXC_R_TPU_HASH_DIGEST   ((uint32_t)0x00000080UL)
#define	MXC_R_TPU_HASH_MSG_SZ   ((uint32_t)0x000000C0UL)
#define	MXC_R_TPU_MAA_MAWS   ((uint32_t)0x000000D0UL)

Detailed Description

TPU Peripheral Register Offsets from the TPU Base Peripheral Address.

Macro Definition Documentation

MXC_R_TPU_CIPHER_CTRL

#define MXC_R_TPU_CIPHER_CTRL   ((uint32_t)0x00000004UL)

Offset from TPU Base Address: 0x0004

MXC_R_TPU_CIPHER_INIT

#define MXC_R_TPU_CIPHER_INIT   ((uint32_t)0x00000050UL)

Offset from TPU Base Address: 0x0050

MXC_R_TPU_CIPHER_KEY

#define MXC_R_TPU_CIPHER_KEY   ((uint32_t)0x00000060UL)

Offset from TPU Base Address: 0x0060

MXC_R_TPU_CRC_CTRL

#define MXC_R_TPU_CRC_CTRL   ((uint32_t)0x0000000CUL)

Offset from TPU Base Address: 0x000C

MXC_R_TPU_CRC_POLY

#define MXC_R_TPU_CRC_POLY   ((uint32_t)0x00000040UL)

Offset from TPU Base Address: 0x0040

MXC_R_TPU_CRC_PRNG

#define MXC_R_TPU_CRC_PRNG   ((uint32_t)0x00000048UL)

Offset from TPU Base Address: 0x0048

MXC_R_TPU_CRC_VAL

#define MXC_R_TPU_CRC_VAL   ((uint32_t)0x00000044UL)

Offset from TPU Base Address: 0x0044

MXC_R_TPU_CRYPTO_CTRL

#define MXC_R_TPU_CRYPTO_CTRL   ((uint32_t)0x00000000UL)

Offset from TPU Base Address: 0x0000

MXC_R_TPU_CRYPTO_DIN

#define MXC_R_TPU_CRYPTO_DIN   ((uint32_t)0x00000020UL)

Offset from TPU Base Address: 0x0020

MXC_R_TPU_CRYPTO_DOUT

#define MXC_R_TPU_CRYPTO_DOUT   ((uint32_t)0x00000030UL)

Offset from TPU Base Address: 0x0030

MXC_R_TPU_DMA_CNT

#define MXC_R_TPU_DMA_CNT   ((uint32_t)0x00000018UL)

Offset from TPU Base Address: 0x0018

MXC_R_TPU_DMA_DEST

#define MXC_R_TPU_DMA_DEST   ((uint32_t)0x00000014UL)

Offset from TPU Base Address: 0x0014

MXC_R_TPU_DMA_SRC

#define MXC_R_TPU_DMA_SRC   ((uint32_t)0x00000010UL)

Offset from TPU Base Address: 0x0010

MXC_R_TPU_HAM_ECC

#define MXC_R_TPU_HAM_ECC   ((uint32_t)0x0000004CUL)

Offset from TPU Base Address: 0x004C

MXC_R_TPU_HASH_CTRL

#define MXC_R_TPU_HASH_CTRL   ((uint32_t)0x00000008UL)

Offset from TPU Base Address: 0x0008

MXC_R_TPU_HASH_DIGEST

#define MXC_R_TPU_HASH_DIGEST   ((uint32_t)0x00000080UL)

Offset from TPU Base Address: 0x0080

MXC_R_TPU_HASH_MSG_SZ

#define MXC_R_TPU_HASH_MSG_SZ   ((uint32_t)0x000000C0UL)

Offset from TPU Base Address: 0x00C0

MXC_R_TPU_MAA_CTRL

#define MXC_R_TPU_MAA_CTRL   ((uint32_t)0x0000001CUL)

Offset from TPU Base Address: 0x001C

MXC_R_TPU_MAA_MAWS

#define MXC_R_TPU_MAA_MAWS   ((uint32_t)0x000000D0UL)

Offset from TPU Base Address: 0x00D0