Macros
#define	MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL)

#define	MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL)

#define	MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL)

#define	MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL)

#define	MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL)

#define	MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL)

#define	MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL)

#define	MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL)

#define	MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL)

#define	MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL)

#define	MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL)

#define	MXC_R_PWRSEQ_VBTLEPD ((uint32_t)0x00000044UL)

#define	MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL)

#define	MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL)

Detailed Description

PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_PWRSEQ_GP0

#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL)

Offset from PWRSEQ Base Address: 0x0048

◆ MXC_R_PWRSEQ_GP1

#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL)

Offset from PWRSEQ Base Address: 0x004C

◆ MXC_R_PWRSEQ_LPCN

#define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL)

Offset from PWRSEQ Base Address: 0x0000

◆ MXC_R_PWRSEQ_LPPWEN

#define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL)

Offset from PWRSEQ Base Address: 0x0034

◆ MXC_R_PWRSEQ_LPPWST

#define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL)

Offset from PWRSEQ Base Address: 0x0030

◆ MXC_R_PWRSEQ_LPWKEN0

#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL)

Offset from PWRSEQ Base Address: 0x0008

◆ MXC_R_PWRSEQ_LPWKEN1

#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL)

Offset from PWRSEQ Base Address: 0x0010

◆ MXC_R_PWRSEQ_LPWKEN2

#define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL)

Offset from PWRSEQ Base Address: 0x0018

◆ MXC_R_PWRSEQ_LPWKEN3

#define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL)

Offset from PWRSEQ Base Address: 0x0020

◆ MXC_R_PWRSEQ_LPWKST0

#define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL)

Offset from PWRSEQ Base Address: 0x0004

◆ MXC_R_PWRSEQ_LPWKST1

#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL)

Offset from PWRSEQ Base Address: 0x000C

◆ MXC_R_PWRSEQ_LPWKST2

#define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL)

Offset from PWRSEQ Base Address: 0x0014

◆ MXC_R_PWRSEQ_LPWKST3

#define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL)

Offset from PWRSEQ Base Address: 0x001C

◆ MXC_R_PWRSEQ_VBTLEPD

#define MXC_R_PWRSEQ_VBTLEPD ((uint32_t)0x00000044UL)

Offset from PWRSEQ Base Address: 0x0044

Macros