spi_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t data;                 
    __IO uint32_t ctrl0;                
    __IO uint32_t ctrl1;                
    __IO uint32_t ctrl2;                
    __IO uint32_t ss_time;              
    __IO uint32_t clk_cfg;              
    __R  uint32_t rsv_0x18;
    __IO uint32_t dma;                  
    __IO uint32_t int_fl;               
    __IO uint32_t int_en;               
    __IO uint32_t wake_fl;              
    __IO uint32_t wake_en;              
    __I  uint32_t stat;                 
} mxc_spi_regs_t;
 
/* Register offsets for module SPI */
#define MXC_R_SPI_DATA                     ((uint32_t)0x00000000UL) 
#define MXC_R_SPI_CTRL0                    ((uint32_t)0x00000004UL) 
#define MXC_R_SPI_CTRL1                    ((uint32_t)0x00000008UL) 
#define MXC_R_SPI_CTRL2                    ((uint32_t)0x0000000CUL) 
#define MXC_R_SPI_SS_TIME                  ((uint32_t)0x00000010UL) 
#define MXC_R_SPI_CLK_CFG                  ((uint32_t)0x00000014UL) 
#define MXC_R_SPI_DMA                      ((uint32_t)0x0000001CUL) 
#define MXC_R_SPI_INT_FL                   ((uint32_t)0x00000020UL) 
#define MXC_R_SPI_INT_EN                   ((uint32_t)0x00000024UL) 
#define MXC_R_SPI_WAKE_FL                  ((uint32_t)0x00000028UL) 
#define MXC_R_SPI_WAKE_EN                  ((uint32_t)0x0000002CUL) 
#define MXC_R_SPI_STAT                     ((uint32_t)0x00000030UL) 
#define MXC_F_SPI_CTRL0_SPI_EN_POS                     0 
#define MXC_F_SPI_CTRL0_SPI_EN                         ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) 
#define MXC_F_SPI_CTRL0_MM_EN_POS                      1 
#define MXC_F_SPI_CTRL0_MM_EN                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) 
#define MXC_F_SPI_CTRL0_SS_IO_POS                      4 
#define MXC_F_SPI_CTRL0_SS_IO                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) 
#define MXC_F_SPI_CTRL0_START_POS                      5 
#define MXC_F_SPI_CTRL0_START                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) 
#define MXC_F_SPI_CTRL0_SS_CTRL_POS                    8 
#define MXC_F_SPI_CTRL0_SS_CTRL                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) 
#define MXC_F_SPI_CTRL0_SS_SEL_POS                     16 
#define MXC_F_SPI_CTRL0_SS_SEL                         ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) 
#define MXC_V_SPI_CTRL0_SS_SEL_SS0                     ((uint32_t)0x1UL) 
#define MXC_S_SPI_CTRL0_SS_SEL_SS0                     (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) 
#define MXC_V_SPI_CTRL0_SS_SEL_SS1                     ((uint32_t)0x2UL) 
#define MXC_S_SPI_CTRL0_SS_SEL_SS1                     (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) 
#define MXC_V_SPI_CTRL0_SS_SEL_SS2                     ((uint32_t)0x4UL) 
#define MXC_S_SPI_CTRL0_SS_SEL_SS2                     (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) 
#define MXC_V_SPI_CTRL0_SS_SEL_SS3                     ((uint32_t)0x8UL) 
#define MXC_S_SPI_CTRL0_SS_SEL_SS3                     (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) 
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS                0 
#define MXC_F_SPI_CTRL1_TX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) 
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS                16 
#define MXC_F_SPI_CTRL1_RX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) 
#define MXC_F_SPI_CTRL2_CLK_PHA_POS                    0 
#define MXC_F_SPI_CTRL2_CLK_PHA                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) 
#define MXC_F_SPI_CTRL2_CLK_POL_POS                    1 
#define MXC_F_SPI_CTRL2_CLK_POL                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) 
#define MXC_F_SPI_CTRL2_NUM_BITS_POS                   8 
#define MXC_F_SPI_CTRL2_NUM_BITS                       ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) 
#define MXC_V_SPI_CTRL2_NUM_BITS_0                     ((uint32_t)0x0UL) 
#define MXC_S_SPI_CTRL2_NUM_BITS_0                     (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) 
#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS                 12 
#define MXC_F_SPI_CTRL2_DATA_WIDTH                     ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) 
#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO                ((uint32_t)0x0UL) 
#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO                (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) 
#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL                ((uint32_t)0x1UL) 
#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL                (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) 
#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD                ((uint32_t)0x2UL) 
#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD                (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) 
#define MXC_F_SPI_CTRL2_THREE_WIRE_POS                 15 
#define MXC_F_SPI_CTRL2_THREE_WIRE                     ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) 
#define MXC_F_SPI_CTRL2_SS_POL_POS                     16 
#define MXC_F_SPI_CTRL2_SS_POL                         ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) 
#define MXC_F_SPI_SS_TIME_SSACT1_POS                   0 
#define MXC_F_SPI_SS_TIME_SSACT1                       ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) 
#define MXC_V_SPI_SS_TIME_SSACT1_256                   ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_SSACT1_256                   (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) 
#define MXC_F_SPI_SS_TIME_SSACT2_POS                   8 
#define MXC_F_SPI_SS_TIME_SSACT2                       ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) 
#define MXC_V_SPI_SS_TIME_SSACT2_256                   ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_SSACT2_256                   (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) 
#define MXC_F_SPI_SS_TIME_SSINACT_POS                  16 
#define MXC_F_SPI_SS_TIME_SSINACT                      ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) 
#define MXC_V_SPI_SS_TIME_SSINACT_256                  ((uint32_t)0x0UL) 
#define MXC_S_SPI_SS_TIME_SSINACT_256                  (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) 
#define MXC_F_SPI_CLK_CFG_LO_POS                       0 
#define MXC_F_SPI_CLK_CFG_LO                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) 
#define MXC_V_SPI_CLK_CFG_LO_DIS                       ((uint32_t)0x0UL) 
#define MXC_S_SPI_CLK_CFG_LO_DIS                       (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) 
#define MXC_F_SPI_CLK_CFG_HI_POS                       8 
#define MXC_F_SPI_CLK_CFG_HI                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) 
#define MXC_V_SPI_CLK_CFG_HI_DIS                       ((uint32_t)0x0UL) 
#define MXC_S_SPI_CLK_CFG_HI_DIS                       (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) 
#define MXC_F_SPI_CLK_CFG_SCALE_POS                    16 
#define MXC_F_SPI_CLK_CFG_SCALE                        ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS                0 
#define MXC_F_SPI_DMA_TX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_EN_POS                   6 
#define MXC_F_SPI_DMA_TX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS                7 
#define MXC_F_SPI_DMA_TX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) 
#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS                  8 
#define MXC_F_SPI_DMA_TX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) 
#define MXC_F_SPI_DMA_TX_DMA_EN_POS                    15 
#define MXC_F_SPI_DMA_TX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS                16 
#define MXC_F_SPI_DMA_RX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_EN_POS                   22 
#define MXC_F_SPI_DMA_RX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS                23 
#define MXC_F_SPI_DMA_RX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) 
#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS                  24 
#define MXC_F_SPI_DMA_RX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) 
#define MXC_F_SPI_DMA_RX_DMA_EN_POS                    31 
#define MXC_F_SPI_DMA_RX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) 
#define MXC_F_SPI_INT_FL_TX_LEVEL_POS                  0 
#define MXC_F_SPI_INT_FL_TX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) 
#define MXC_F_SPI_INT_FL_TX_EMPTY_POS                  1 
#define MXC_F_SPI_INT_FL_TX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) 
#define MXC_F_SPI_INT_FL_RX_LEVEL_POS                  2 
#define MXC_F_SPI_INT_FL_RX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) 
#define MXC_F_SPI_INT_FL_RX_FULL_POS                   3 
#define MXC_F_SPI_INT_FL_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) 
#define MXC_F_SPI_INT_FL_SSA_POS                       4 
#define MXC_F_SPI_INT_FL_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) 
#define MXC_F_SPI_INT_FL_SSD_POS                       5 
#define MXC_F_SPI_INT_FL_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) 
#define MXC_F_SPI_INT_FL_ABORT_POS                     9 
#define MXC_F_SPI_INT_FL_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) 
#define MXC_F_SPI_INT_FL_M_DONE_POS                    11 
#define MXC_F_SPI_INT_FL_M_DONE                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) 
#define MXC_F_SPI_INT_FL_TX_OVR_POS                    12 
#define MXC_F_SPI_INT_FL_TX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) 
#define MXC_F_SPI_INT_FL_TX_UND_POS                    13 
#define MXC_F_SPI_INT_FL_TX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) 
#define MXC_F_SPI_INT_FL_RX_OVR_POS                    14 
#define MXC_F_SPI_INT_FL_RX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) 
#define MXC_F_SPI_INT_FL_RX_UND_POS                    15 
#define MXC_F_SPI_INT_FL_RX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) 
#define MXC_F_SPI_INT_EN_TX_LEVEL_POS                  0 
#define MXC_F_SPI_INT_EN_TX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) 
#define MXC_F_SPI_INT_EN_TX_EMPTY_POS                  1 
#define MXC_F_SPI_INT_EN_TX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) 
#define MXC_F_SPI_INT_EN_RX_LEVEL_POS                  2 
#define MXC_F_SPI_INT_EN_RX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) 
#define MXC_F_SPI_INT_EN_RX_FULL_POS                   3 
#define MXC_F_SPI_INT_EN_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) 
#define MXC_F_SPI_INT_EN_SSA_POS                       4 
#define MXC_F_SPI_INT_EN_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) 
#define MXC_F_SPI_INT_EN_SSD_POS                       5 
#define MXC_F_SPI_INT_EN_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) 
#define MXC_F_SPI_INT_EN_FAULT_POS                     8 
#define MXC_F_SPI_INT_EN_FAULT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) 
#define MXC_F_SPI_INT_EN_ABORT_POS                     9 
#define MXC_F_SPI_INT_EN_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) 
#define MXC_F_SPI_INT_EN_M_DONE_POS                    11 
#define MXC_F_SPI_INT_EN_M_DONE                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) 
#define MXC_F_SPI_INT_EN_TX_OVR_POS                    12 
#define MXC_F_SPI_INT_EN_TX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) 
#define MXC_F_SPI_INT_EN_TX_UND_POS                    13 
#define MXC_F_SPI_INT_EN_TX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) 
#define MXC_F_SPI_INT_EN_RX_OVR_POS                    14 
#define MXC_F_SPI_INT_EN_RX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) 
#define MXC_F_SPI_INT_EN_RX_UND_POS                    15 
#define MXC_F_SPI_INT_EN_RX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) 
#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS                 0 
#define MXC_F_SPI_WAKE_FL_TX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) 
#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS                 1 
#define MXC_F_SPI_WAKE_FL_TX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) 
#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS                 2 
#define MXC_F_SPI_WAKE_FL_RX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) 
#define MXC_F_SPI_WAKE_FL_RX_FULL_POS                  3 
#define MXC_F_SPI_WAKE_FL_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) 
#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS                 0 
#define MXC_F_SPI_WAKE_EN_TX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) 
#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS                 1 
#define MXC_F_SPI_WAKE_EN_TX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) 
#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS                 2 
#define MXC_F_SPI_WAKE_EN_RX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) 
#define MXC_F_SPI_WAKE_EN_RX_FULL_POS                  3 
#define MXC_F_SPI_WAKE_EN_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) 
#define MXC_F_SPI_STAT_BUSY_POS                        0 
#define MXC_F_SPI_STAT_BUSY                            ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_SPI_REGS_H_