MAX32660 Peripheral Driver API
Peripheral Driver API for the MAX32660
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Data Structures | Macros
spimss_regs.h File Reference
SPIMSS » SPIMSS_Registers
#include <stdint.h>

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Data Structures

struct  mxc_spimss_regs_t
 

Macros

#define MXC_R_SPIMSS_DATA   ((uint32_t)0x00000000UL)
 
#define MXC_R_SPIMSS_CTRL   ((uint32_t)0x00000004UL)
 
#define MXC_R_SPIMSS_INT_FL   ((uint32_t)0x00000008UL)
 
#define MXC_R_SPIMSS_MODE   ((uint32_t)0x0000000CUL)
 
#define MXC_R_SPIMSS_BRG   ((uint32_t)0x00000014UL)
 
#define MXC_R_SPIMSS_DMA   ((uint32_t)0x00000018UL)
 
#define MXC_R_SPIMSS_I2S_CTRL   ((uint32_t)0x0000001CUL)
 
#define MXC_F_SPIMSS_DATA_DATA_POS   0
 
#define MXC_F_SPIMSS_DATA_DATA   ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS))
 
#define MXC_F_SPIMSS_CTRL_ENABLE_POS   0
 
#define MXC_F_SPIMSS_CTRL_ENABLE   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS))
 
#define MXC_F_SPIMSS_CTRL_MMEN_POS   1
 
#define MXC_F_SPIMSS_CTRL_MMEN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS))
 
#define MXC_F_SPIMSS_CTRL_WOR_POS   2
 
#define MXC_F_SPIMSS_CTRL_WOR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS))
 
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS   3
 
#define MXC_F_SPIMSS_CTRL_CLKPOL   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS))
 
#define MXC_F_SPIMSS_CTRL_PHASE_POS   4
 
#define MXC_F_SPIMSS_CTRL_PHASE   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS))
 
#define MXC_F_SPIMSS_CTRL_BIRQ_POS   5
 
#define MXC_F_SPIMSS_CTRL_BIRQ   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS))
 
#define MXC_F_SPIMSS_CTRL_STR_POS   6
 
#define MXC_F_SPIMSS_CTRL_STR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS))
 
#define MXC_F_SPIMSS_CTRL_IRQE_POS   7
 
#define MXC_F_SPIMSS_CTRL_IRQE   ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS))
 
#define MXC_F_SPIMSS_INT_FL_SLAS_POS   0
 
#define MXC_F_SPIMSS_INT_FL_SLAS   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS))
 
#define MXC_F_SPIMSS_INT_FL_TXST_POS   1
 
#define MXC_F_SPIMSS_INT_FL_TXST   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS))
 
#define MXC_F_SPIMSS_INT_FL_TUND_POS   2
 
#define MXC_F_SPIMSS_INT_FL_TUND   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS))
 
#define MXC_F_SPIMSS_INT_FL_ROVR_POS   3
 
#define MXC_F_SPIMSS_INT_FL_ROVR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS))
 
#define MXC_F_SPIMSS_INT_FL_ABT_POS   4
 
#define MXC_F_SPIMSS_INT_FL_ABT   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS))
 
#define MXC_F_SPIMSS_INT_FL_COL_POS   5
 
#define MXC_F_SPIMSS_INT_FL_COL   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS))
 
#define MXC_F_SPIMSS_INT_FL_TOVR_POS   6
 
#define MXC_F_SPIMSS_INT_FL_TOVR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS))
 
#define MXC_F_SPIMSS_INT_FL_IRQ_POS   7
 
#define MXC_F_SPIMSS_INT_FL_IRQ   ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS))
 
#define MXC_F_SPIMSS_MODE_SSV_POS   0
 
#define MXC_F_SPIMSS_MODE_SSV   ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS))
 
#define MXC_F_SPIMSS_MODE_SS_IO_POS   1
 
#define MXC_F_SPIMSS_MODE_SS_IO   ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS))
 
#define MXC_F_SPIMSS_MODE_NUMBITS_POS   2
 
#define MXC_F_SPIMSS_MODE_NUMBITS   ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS))
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS16   ((uint32_t)0x0UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS16   (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS1   ((uint32_t)0x1UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS1   (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS2   ((uint32_t)0x2UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS2   (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS3   ((uint32_t)0x3UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS3   (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS4   ((uint32_t)0x4UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS4   (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS5   ((uint32_t)0x5UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS5   (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS6   ((uint32_t)0x6UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS6   (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS7   ((uint32_t)0x7UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS7   (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS8   ((uint32_t)0x8UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS8   (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS9   ((uint32_t)0x9UL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS9   (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS10   ((uint32_t)0xAUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS10   (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS11   ((uint32_t)0xBUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS11   (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS12   ((uint32_t)0xCUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS12   (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS13   ((uint32_t)0xDUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS13   (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS14   ((uint32_t)0xEUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS14   (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_V_SPIMSS_MODE_NUMBITS_BITS15   ((uint32_t)0xFUL)
 
#define MXC_S_SPIMSS_MODE_NUMBITS_BITS15   (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS)
 
#define MXC_F_SPIMSS_MODE_TX_LJ_POS   7
 
#define MXC_F_SPIMSS_MODE_TX_LJ   ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS))
 
#define MXC_F_SPIMSS_BRG_DIV_POS   0
 
#define MXC_F_SPIMSS_BRG_DIV   ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS))
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS   0
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS))
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)
 
#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS   4
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS))
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS   8
 
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS))
 
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS   15
 
#define MXC_F_SPIMSS_DMA_TX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS))
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS   16
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS))
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)
 
#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS   20
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS))
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS   24
 
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS))
 
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS   31
 
#define MXC_F_SPIMSS_DMA_RX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS))
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS   0
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS))
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS   1
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS))
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS   2
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS))
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS   3
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS))
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS   4
 
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS))
 

Detailed Description

Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.

Note
This file is @generated.