Modules
	Register Offsets

	SDMA_INT_MUX_CTRL0

	SDMA_INT_MUX_CTRL1

	SDMA_INT_MUX_CTRL2

	SDMA_INT_MUX_CTRL3

	SDMA_IP_ADDR

	SDMA_CTRL

	SDMA_INT_IN_CTRL

	SDMA_INT_IN_FLAG

	SDMA_INT_IN_IE

	SDMA_IRQ_FLAG

	SDMA_IRQ_IE

Data Structures
struct	mxc_sdma_regs_t

Detailed Description

Registers, Bit Masks and Bit Positions for the SDMA Peripheral Module.

Smart DMA

Data Structure Documentation

◆ mxc_sdma_regs_t

struct mxc_sdma_regs_t

Structure type to access the SDMA Registers.

Data Fields
__I uint32_t	ip

__I uint32_t	sp

__I uint32_t	dp0

__I uint32_t	dp1

__I uint32_t	bp

__I uint32_t	offs

__I uint32_t	lc0

__I uint32_t	lc1

__I uint32_t	a0

__I uint32_t	a1

__I uint32_t	a2

__I uint32_t	a3

__I uint32_t	wdcn

__IO uint32_t	int_mux_ctrl0

__IO uint32_t	int_mux_ctrl1

__IO uint32_t	int_mux_ctrl2

__IO uint32_t	int_mux_ctrl3

__IO uint32_t	ip_addr

__IO uint32_t	ctrl

__IO uint32_t	int_in_ctrl

__IO uint32_t	int_in_flag

__IO uint32_t	int_in_ie

__IO uint32_t	irq_flag

__IO uint32_t	irq_ie

Field Documentation

◆ a0

__I uint32_t a0

0x20: SDMA A0 Register

◆ a1

__I uint32_t a1

0x24: SDMA A1 Register

◆ a2

__I uint32_t a2

0x28: SDMA A2 Register

◆ a3

__I uint32_t a3

0x2C: SDMA A3 Register

◆ bp

__I uint32_t bp

0x10: SDMA BP Register

◆ ctrl

__IO uint32_t ctrl

0x94: SDMA CTRL Register

◆ dp0

__I uint32_t dp0

0x08: SDMA DP0 Register

◆ dp1

__I uint32_t dp1

0x0C: SDMA DP1 Register

◆ int_in_ctrl

__IO uint32_t int_in_ctrl

0xA0: SDMA INT_IN_CTRL Register

◆ int_in_flag

__IO uint32_t int_in_flag

0xA4: SDMA INT_IN_FLAG Register

◆ int_in_ie

__IO uint32_t int_in_ie

0xA8: SDMA INT_IN_IE Register

◆ int_mux_ctrl0

__IO uint32_t int_mux_ctrl0

0x80: SDMA INT_MUX_CTRL0 Register

◆ int_mux_ctrl1

__IO uint32_t int_mux_ctrl1

0x84: SDMA INT_MUX_CTRL1 Register

◆ int_mux_ctrl2

__IO uint32_t int_mux_ctrl2

0x88: SDMA INT_MUX_CTRL2 Register

◆ int_mux_ctrl3

__IO uint32_t int_mux_ctrl3

0x8C: SDMA INT_MUX_CTRL3 Register

◆ ip

__I uint32_t ip

0x00: SDMA IP Register

◆ ip_addr

__IO uint32_t ip_addr

0x90: SDMA IP_ADDR Register

◆ irq_flag

__IO uint32_t irq_flag

0xB0: SDMA IRQ_FLAG Register

◆ irq_ie

__IO uint32_t irq_ie

0xB4: SDMA IRQ_IE Register

◆ lc0

__I uint32_t lc0

0x18: SDMA LC0 Register

◆ lc1

__I uint32_t lc1

0x1C: SDMA LC1 Register

◆ offs

__I uint32_t offs

0x14: SDMA OFFS Register

◆ sp

__I uint32_t sp

0x04: SDMA SP Register

◆ wdcn

__I uint32_t wdcn

0x30: SDMA WDCN Register

Modules

Data Structures