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#define | MXC_R_DVS_CTL ((uint32_t)0x00000000UL) |
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#define | MXC_R_DVS_STAT ((uint32_t)0x00000004UL) |
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#define | MXC_R_DVS_DIRECT ((uint32_t)0x00000008UL) |
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#define | MXC_R_DVS_MON ((uint32_t)0x0000000CUL) |
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#define | MXC_R_DVS_ADJ_UP ((uint32_t)0x00000010UL) |
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#define | MXC_R_DVS_ADJ_DWN ((uint32_t)0x00000014UL) |
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#define | MXC_R_DVS_THRES_CMP ((uint32_t)0x00000018UL) |
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#define | MXC_R_DVS_TAP_SEL ((uint32_t)0x0000001CUL) |
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#define | MXC_F_DVS_CTL_MON_ENA_POS 0 |
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#define | MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS)) |
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#define | MXC_F_DVS_CTL_ADJ_ENA_POS 1 |
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#define | MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS)) |
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#define | MXC_F_DVS_CTL_PS_FB_DIS_POS 2 |
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#define | MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS)) |
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#define | MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3 |
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#define | MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS)) |
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#define | MXC_F_DVS_CTL_PROP_DLY_POS 4 |
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#define | MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS)) |
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#define | MXC_F_DVS_CTL_MON_ONESHOT_POS 6 |
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#define | MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS)) |
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#define | MXC_F_DVS_CTL_GO_DIRECT_POS 7 |
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#define | MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS)) |
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#define | MXC_F_DVS_CTL_DIRECT_REG_POS 8 |
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#define | MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS)) |
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#define | MXC_F_DVS_CTL_PRIME_ENA_POS 9 |
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#define | MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS)) |
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#define | MXC_F_DVS_CTL_LIMIT_IE_POS 10 |
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#define | MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS)) |
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#define | MXC_F_DVS_CTL_RANGE_IE_POS 11 |
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#define | MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS)) |
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#define | MXC_F_DVS_CTL_ADJ_IE_POS 12 |
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#define | MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS)) |
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#define | MXC_F_DVS_CTL_REF_SEL_POS 13 |
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#define | MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS)) |
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#define | MXC_F_DVS_CTL_INC_VAL_POS 17 |
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#define | MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS)) |
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#define | MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20 |
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#define | MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS)) |
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#define | MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21 |
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#define | MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS)) |
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#define | MXC_F_DVS_CTL_FB_TO_IE_POS 22 |
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#define | MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS)) |
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#define | MXC_F_DVS_CTL_FC_LV_IE_POS 23 |
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#define | MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS)) |
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#define | MXC_F_DVS_CTL_PD_ACK_ENA_POS 24 |
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#define | MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS)) |
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#define | MXC_F_DVS_CTL_ADJ_ABORT_POS 25 |
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#define | MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS)) |
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#define | MXC_F_DVS_STAT_DVS_STATE_POS 0 |
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#define | MXC_F_DVS_STAT_DVS_STATE ((uint32_t)(0xFUL << MXC_F_DVS_STAT_DVS_STATE_POS)) |
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#define | MXC_F_DVS_STAT_ADJ_UP_ENA_POS 4 |
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#define | MXC_F_DVS_STAT_ADJ_UP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_UP_ENA_POS)) |
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#define | MXC_F_DVS_STAT_ADJ_DWN_ENA_POS 5 |
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#define | MXC_F_DVS_STAT_ADJ_DWN_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DWN_ENA_POS)) |
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#define | MXC_F_DVS_STAT_ADJ_ACTIVE_POS 6 |
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#define | MXC_F_DVS_STAT_ADJ_ACTIVE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ACTIVE_POS)) |
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#define | MXC_F_DVS_STAT_CTR_TAP_OK_POS 7 |
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#define | MXC_F_DVS_STAT_CTR_TAP_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_OK_POS)) |
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#define | MXC_F_DVS_STAT_CTR_TAP_SEL_POS 8 |
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#define | MXC_F_DVS_STAT_CTR_TAP_SEL ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_SEL_POS)) |
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#define | MXC_F_DVS_STAT_SLOW_TRIP_DET_POS 9 |
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#define | MXC_F_DVS_STAT_SLOW_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_SLOW_TRIP_DET_POS)) |
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#define | MXC_F_DVS_STAT_FAST_TRIP_DET_POS 10 |
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#define | MXC_F_DVS_STAT_FAST_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FAST_TRIP_DET_POS)) |
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#define | MXC_F_DVS_STAT_PS_IN_RANGE_POS 11 |
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#define | MXC_F_DVS_STAT_PS_IN_RANGE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_PS_IN_RANGE_POS)) |
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#define | MXC_F_DVS_STAT_PS_VCNTR_POS 12 |
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#define | MXC_F_DVS_STAT_PS_VCNTR ((uint32_t)(0x7FUL << MXC_F_DVS_STAT_PS_VCNTR_POS)) |
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#define | MXC_F_DVS_STAT_MON_DLY_OK_POS 19 |
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#define | MXC_F_DVS_STAT_MON_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_MON_DLY_OK_POS)) |
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#define | MXC_F_DVS_STAT_ADJ_DLY_OK_POS 20 |
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#define | MXC_F_DVS_STAT_ADJ_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DLY_OK_POS)) |
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#define | MXC_F_DVS_STAT_LO_LIMIT_DET_POS 21 |
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#define | MXC_F_DVS_STAT_LO_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LO_LIMIT_DET_POS)) |
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#define | MXC_F_DVS_STAT_HI_LIMIT_DET_POS 22 |
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#define | MXC_F_DVS_STAT_HI_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_HI_LIMIT_DET_POS)) |
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#define | MXC_F_DVS_STAT_VALID_TAP_POS 23 |
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#define | MXC_F_DVS_STAT_VALID_TAP ((uint32_t)(0x1UL << MXC_F_DVS_STAT_VALID_TAP_POS)) |
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#define | MXC_F_DVS_STAT_LIMIT_ERR_POS 24 |
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#define | MXC_F_DVS_STAT_LIMIT_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LIMIT_ERR_POS)) |
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#define | MXC_F_DVS_STAT_RANGE_ERR_POS 25 |
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#define | MXC_F_DVS_STAT_RANGE_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_RANGE_ERR_POS)) |
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#define | MXC_F_DVS_STAT_ADJ_ERR_POS 26 |
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#define | MXC_F_DVS_STAT_ADJ_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ERR_POS)) |
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#define | MXC_F_DVS_STAT_REF_SEL_ERR_POS 27 |
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#define | MXC_F_DVS_STAT_REF_SEL_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_REF_SEL_ERR_POS)) |
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#define | MXC_F_DVS_STAT_FB_TO_ERR_POS 28 |
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#define | MXC_F_DVS_STAT_FB_TO_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_POS)) |
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#define | MXC_F_DVS_STAT_FB_TO_ERR_S_POS 29 |
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#define | MXC_F_DVS_STAT_FB_TO_ERR_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_S_POS)) |
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#define | MXC_F_DVS_STAT_FC_LV_DET_INT_POS 30 |
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#define | MXC_F_DVS_STAT_FC_LV_DET_INT ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_INT_POS)) |
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#define | MXC_F_DVS_STAT_FC_LV_DET_S_POS 31 |
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#define | MXC_F_DVS_STAT_FC_LV_DET_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_S_POS)) |
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#define | MXC_F_DVS_DIRECT_VOLTAGE_POS 0 |
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#define | MXC_F_DVS_DIRECT_VOLTAGE ((uint32_t)(0x7FUL << MXC_F_DVS_DIRECT_VOLTAGE_POS)) |
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#define | MXC_F_DVS_MON_DLY_POS 0 |
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#define | MXC_F_DVS_MON_DLY ((uint32_t)(0xFFFFFFUL << MXC_F_DVS_MON_DLY_POS)) |
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#define | MXC_F_DVS_MON_PRE_POS 24 |
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#define | MXC_F_DVS_MON_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_MON_PRE_POS)) |
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#define | MXC_F_DVS_ADJ_UP_DLY_POS 0 |
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#define | MXC_F_DVS_ADJ_UP_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_UP_DLY_POS)) |
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#define | MXC_F_DVS_ADJ_UP_PRE_POS 16 |
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#define | MXC_F_DVS_ADJ_UP_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_UP_PRE_POS)) |
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#define | MXC_F_DVS_ADJ_DWN_DLY_POS 0 |
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#define | MXC_F_DVS_ADJ_DWN_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_DWN_DLY_POS)) |
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#define | MXC_F_DVS_ADJ_DWN_PRE_POS 16 |
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#define | MXC_F_DVS_ADJ_DWN_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_DWN_PRE_POS)) |
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#define | MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS 0 |
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#define | MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS)) |
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#define | MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS 8 |
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#define | MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS)) |
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#define | MXC_F_DVS_TAP_SEL_LO_POS 0 |
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#define | MXC_F_DVS_TAP_SEL_LO ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_LO_POS)) |
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#define | MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS 5 |
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#define | MXC_F_DVS_TAP_SEL_LO_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS)) |
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#define | MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS 6 |
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#define | MXC_F_DVS_TAP_SEL_CTR_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS)) |
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#define | MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS 7 |
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#define | MXC_F_DVS_TAP_SEL_HI_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS)) |
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#define | MXC_F_DVS_TAP_SEL_HI_POS 8 |
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#define | MXC_F_DVS_TAP_SEL_HI ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_HI_POS)) |
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#define | MXC_F_DVS_TAP_SEL_CTR_POS 16 |
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#define | MXC_F_DVS_TAP_SEL_CTR ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_CTR_POS)) |
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#define | MXC_F_DVS_TAP_SEL_COARSE_POS 24 |
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#define | MXC_F_DVS_TAP_SEL_COARSE ((uint32_t)(0x7UL << MXC_F_DVS_TAP_SEL_COARSE_POS)) |
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#define | MXC_F_DVS_TAP_SEL_DET_DLY_POS 29 |
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#define | MXC_F_DVS_TAP_SEL_DET_DLY ((uint32_t)(0x3UL << MXC_F_DVS_TAP_SEL_DET_DLY_POS)) |
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#define | MXC_F_DVS_TAP_SEL_DELAY_ACT_POS 31 |
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#define | MXC_F_DVS_TAP_SEL_DELAY_ACT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_DELAY_ACT_POS)) |
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