GCR_RSTR1

Macros
#define	MXC_F_GCR_RSTR1_I2C1_POS   0
#define	MXC_F_GCR_RSTR1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS))
#define	MXC_F_GCR_RSTR1_PT_POS   1
#define	MXC_F_GCR_RSTR1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PT_POS))
#define	MXC_F_GCR_RSTR1_SPIXIP_POS   3
#define	MXC_F_GCR_RSTR1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXIP_POS))
#define	MXC_F_GCR_RSTR1_XSPIM_POS   4
#define	MXC_F_GCR_RSTR1_XSPIM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_XSPIM_POS))
#define	MXC_F_GCR_RSTR1_SDHC_POS   6
#define	MXC_F_GCR_RSTR1_SDHC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SDHC_POS))
#define	MXC_F_GCR_RSTR1_OWIRE_POS   7
#define	MXC_F_GCR_RSTR1_OWIRE   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_OWIRE_POS))
#define	MXC_F_GCR_RSTR1_WDT1_POS   8
#define	MXC_F_GCR_RSTR1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS))
#define	MXC_F_GCR_RSTR1_SPI0_POS   9
#define	MXC_F_GCR_RSTR1_SPI0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPI0_POS))
#define	MXC_F_GCR_RSTR1_SPIXMEM_POS   15
#define	MXC_F_GCR_RSTR1_SPIXMEM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXMEM_POS))
#define	MXC_F_GCR_RSTR1_SMPHR_POS   16
#define	MXC_F_GCR_RSTR1_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SMPHR_POS))
#define	MXC_F_GCR_RSTR1_WDT2_POS   17
#define	MXC_F_GCR_RSTR1_WDT2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT2_POS))
#define	MXC_F_GCR_RSTR1_BTLE_POS   18
#define	MXC_F_GCR_RSTR1_BTLE   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_BTLE_POS))
#define	MXC_F_GCR_RSTR1_AUDIO_POS   19
#define	MXC_F_GCR_RSTR1_AUDIO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_AUDIO_POS))
#define	MXC_F_GCR_RSTR1_I2C2_POS   20
#define	MXC_F_GCR_RSTR1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C2_POS))
#define	MXC_F_GCR_RSTR1_RPU_POS   21
#define	MXC_F_GCR_RSTR1_RPU   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_RPU_POS))
#define	MXC_F_GCR_RSTR1_HTMR0_POS   22
#define	MXC_F_GCR_RSTR1_HTMR0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR0_POS))
#define	MXC_F_GCR_RSTR1_HTMR1_POS   23
#define	MXC_F_GCR_RSTR1_HTMR1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR1_POS))
#define	MXC_F_GCR_RSTR1_DVS_POS   24
#define	MXC_F_GCR_RSTR1_DVS   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_DVS_POS))
#define	MXC_F_GCR_RSTR1_SIMO_POS   25
#define	MXC_F_GCR_RSTR1_SIMO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SIMO_POS))

Detailed Description

Reset 1.

Macro Definition Documentation

MXC_F_GCR_RSTR1_AUDIO

#define MXC_F_GCR_RSTR1_AUDIO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_AUDIO_POS))

RSTR1_AUDIO Mask

MXC_F_GCR_RSTR1_AUDIO_POS

#define MXC_F_GCR_RSTR1_AUDIO_POS   19

RSTR1_AUDIO Position

MXC_F_GCR_RSTR1_BTLE

#define MXC_F_GCR_RSTR1_BTLE   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_BTLE_POS))

RSTR1_BTLE Mask

MXC_F_GCR_RSTR1_BTLE_POS

#define MXC_F_GCR_RSTR1_BTLE_POS   18

RSTR1_BTLE Position

MXC_F_GCR_RSTR1_DVS

#define MXC_F_GCR_RSTR1_DVS   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_DVS_POS))

RSTR1_DVS Mask

MXC_F_GCR_RSTR1_DVS_POS

#define MXC_F_GCR_RSTR1_DVS_POS   24

RSTR1_DVS Position

MXC_F_GCR_RSTR1_HTMR0

#define MXC_F_GCR_RSTR1_HTMR0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR0_POS))

RSTR1_HTMR0 Mask

MXC_F_GCR_RSTR1_HTMR0_POS

#define MXC_F_GCR_RSTR1_HTMR0_POS   22

RSTR1_HTMR0 Position

MXC_F_GCR_RSTR1_HTMR1

#define MXC_F_GCR_RSTR1_HTMR1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR1_POS))

RSTR1_HTMR1 Mask

MXC_F_GCR_RSTR1_HTMR1_POS

#define MXC_F_GCR_RSTR1_HTMR1_POS   23

RSTR1_HTMR1 Position

MXC_F_GCR_RSTR1_I2C1

#define MXC_F_GCR_RSTR1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS))

RSTR1_I2C1 Mask

MXC_F_GCR_RSTR1_I2C1_POS

#define MXC_F_GCR_RSTR1_I2C1_POS   0

RSTR1_I2C1 Position

MXC_F_GCR_RSTR1_I2C2

#define MXC_F_GCR_RSTR1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C2_POS))

RSTR1_I2C2 Mask

MXC_F_GCR_RSTR1_I2C2_POS

#define MXC_F_GCR_RSTR1_I2C2_POS   20

RSTR1_I2C2 Position

MXC_F_GCR_RSTR1_OWIRE

#define MXC_F_GCR_RSTR1_OWIRE   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_OWIRE_POS))

RSTR1_OWIRE Mask

MXC_F_GCR_RSTR1_OWIRE_POS

#define MXC_F_GCR_RSTR1_OWIRE_POS   7

RSTR1_OWIRE Position

MXC_F_GCR_RSTR1_PT

#define MXC_F_GCR_RSTR1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PT_POS))

RSTR1_PT Mask

MXC_F_GCR_RSTR1_PT_POS

#define MXC_F_GCR_RSTR1_PT_POS   1

RSTR1_PT Position

MXC_F_GCR_RSTR1_RPU

#define MXC_F_GCR_RSTR1_RPU   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_RPU_POS))

RSTR1_RPU Mask

MXC_F_GCR_RSTR1_RPU_POS

#define MXC_F_GCR_RSTR1_RPU_POS   21

RSTR1_RPU Position

MXC_F_GCR_RSTR1_SDHC

#define MXC_F_GCR_RSTR1_SDHC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SDHC_POS))

RSTR1_SDHC Mask

MXC_F_GCR_RSTR1_SDHC_POS

#define MXC_F_GCR_RSTR1_SDHC_POS   6

RSTR1_SDHC Position

MXC_F_GCR_RSTR1_SIMO

#define MXC_F_GCR_RSTR1_SIMO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SIMO_POS))

RSTR1_SIMO Mask

MXC_F_GCR_RSTR1_SIMO_POS

#define MXC_F_GCR_RSTR1_SIMO_POS   25

RSTR1_SIMO Position

MXC_F_GCR_RSTR1_SMPHR

#define MXC_F_GCR_RSTR1_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SMPHR_POS))

RSTR1_SMPHR Mask

MXC_F_GCR_RSTR1_SMPHR_POS

#define MXC_F_GCR_RSTR1_SMPHR_POS   16

RSTR1_SMPHR Position

MXC_F_GCR_RSTR1_SPI0

#define MXC_F_GCR_RSTR1_SPI0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPI0_POS))

RSTR1_SPI0 Mask

MXC_F_GCR_RSTR1_SPI0_POS

#define MXC_F_GCR_RSTR1_SPI0_POS   9

RSTR1_SPI0 Position

MXC_F_GCR_RSTR1_SPIXIP

#define MXC_F_GCR_RSTR1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXIP_POS))

RSTR1_SPIXIP Mask

MXC_F_GCR_RSTR1_SPIXIP_POS

#define MXC_F_GCR_RSTR1_SPIXIP_POS   3

RSTR1_SPIXIP Position

MXC_F_GCR_RSTR1_SPIXMEM

#define MXC_F_GCR_RSTR1_SPIXMEM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXMEM_POS))

RSTR1_SPIXMEM Mask

MXC_F_GCR_RSTR1_SPIXMEM_POS

#define MXC_F_GCR_RSTR1_SPIXMEM_POS   15

RSTR1_SPIXMEM Position

MXC_F_GCR_RSTR1_WDT1

#define MXC_F_GCR_RSTR1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS))

RSTR1_WDT1 Mask

MXC_F_GCR_RSTR1_WDT1_POS

#define MXC_F_GCR_RSTR1_WDT1_POS   8

RSTR1_WDT1 Position

MXC_F_GCR_RSTR1_WDT2

#define MXC_F_GCR_RSTR1_WDT2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT2_POS))

RSTR1_WDT2 Mask

MXC_F_GCR_RSTR1_WDT2_POS

#define MXC_F_GCR_RSTR1_WDT2_POS   17

RSTR1_WDT2 Position

MXC_F_GCR_RSTR1_XSPIM

#define MXC_F_GCR_RSTR1_XSPIM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_XSPIM_POS))

RSTR1_XSPIM Mask

MXC_F_GCR_RSTR1_XSPIM_POS

#define MXC_F_GCR_RSTR1_XSPIM_POS   4

RSTR1_XSPIM Position