MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
rpu_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t gcr;
78 __IO uint32_t sir;
79 __IO uint32_t fcr;
80 __R uint32_t rsv_0xc;
81 __IO uint32_t tpu;
82 __R uint32_t rsv_0x14_0x1f[3];
83 __IO uint32_t rpu;
84 __R uint32_t rsv_0x24_0x2f[3];
85 __IO uint32_t wdt0;
86 __IO uint32_t wdt1;
87 __IO uint32_t wdt2;
88 __R uint32_t rsv_0x3c;
89 __IO uint32_t smon;
90 __IO uint32_t simo;
91 __IO uint32_t dvs;
92 __R uint32_t rsv_0x4c;
93 __IO uint32_t aes;
94 __R uint32_t rsv_0x54_0x5f[3];
95 __IO uint32_t rtc;
96 __IO uint32_t wut;
97 __IO uint32_t pwrseq;
98 __IO uint32_t mcr;
99 __R uint32_t rsv_0x70_0x7f[4];
100 __IO uint32_t gpio0;
101 __R uint32_t rsv_0x84_0x8f[3];
102 __IO uint32_t gpio1;
103 __R uint32_t rsv_0x94_0xff[27];
104 __IO uint32_t tmr0;
105 __R uint32_t rsv_0x104_0x10f[3];
106 __IO uint32_t tmr1;
107 __R uint32_t rsv_0x114_0x11f[3];
108 __IO uint32_t tmr2;
109 __R uint32_t rsv_0x124_0x12f[3];
110 __IO uint32_t tmr3;
111 __R uint32_t rsv_0x134_0x13f[3];
112 __IO uint32_t tmr4;
113 __R uint32_t rsv_0x144_0x14f[3];
114 __IO uint32_t tmr5;
115 __R uint32_t rsv_0x154_0x1af[23];
116 __IO uint32_t htimer0;
117 __R uint32_t rsv_0x1b4_0x1bf[3];
118 __IO uint32_t htimer1;
119 __R uint32_t rsv_0x1c4_0x1cf[3];
120 __IO uint32_t i2c0_bus0;
121 __R uint32_t rsv_0x1d4_0x1df[3];
122 __IO uint32_t i2c1_bus0;
123 __R uint32_t rsv_0x1e4_0x1ef[3];
124 __IO uint32_t i2c2_bus0;
125 __R uint32_t rsv_0x1f4_0x25f[27];
126 __IO uint32_t spixfm;
127 __R uint32_t rsv_0x264_0x26f[3];
128 __IO uint32_t spixfc;
129 __R uint32_t rsv_0x274_0x27f[3];
130 __IO uint32_t dma0;
131 __R uint32_t rsv_0x284_0x28f[3];
132 __IO uint32_t flc0;
133 __IO uint32_t flc1;
134 __R uint32_t rsv_0x298_0x29f[2];
135 __IO uint32_t icc0;
136 __IO uint32_t icc1;
137 __R uint32_t rsv_0x2a8_0x2ef[18];
138 __IO uint32_t sfcc;
139 __R uint32_t rsv_0x2f4_0x32f[15];
140 __IO uint32_t srcc;
141 __R uint32_t rsv_0x334_0x33f[3];
142 __IO uint32_t adc;
143 __R uint32_t rsv_0x344_0x34f[3];
144 __IO uint32_t dma1;
145 __R uint32_t rsv_0x354_0x35f[3];
146 __IO uint32_t sdma;
147 __R uint32_t rsv_0x364_0x36f[3];
148 __IO uint32_t sdhcctrl;
149 __R uint32_t rsv_0x374_0x39f[11];
150 __IO uint32_t spixr;
151 __R uint32_t rsv_0x3a4_0x3bf[7];
152 __IO uint32_t ptg_bus0;
153 __R uint32_t rsv_0x3c4_0x3cf[3];
154 __IO uint32_t owm;
155 __R uint32_t rsv_0x3d4_0x3df[3];
156 __IO uint32_t sema;
157 __R uint32_t rsv_0x3e4_0x41f[15];
158 __IO uint32_t uart0;
159 __R uint32_t rsv_0x424_0x42f[3];
160 __IO uint32_t uart1;
161 __R uint32_t rsv_0x434_0x43f[3];
162 __IO uint32_t uart2;
163 __R uint32_t rsv_0x444_0x45f[7];
164 __IO uint32_t spi1;
165 __R uint32_t rsv_0x464_0x46f[3];
166 __IO uint32_t spi2;
167 __R uint32_t rsv_0x474_0x4bf[19];
168 __IO uint32_t audio;
169 __R uint32_t rsv_0x4c4_0x4cf[3];
170 __IO uint32_t trng;
171 __R uint32_t rsv_0x4d4_0x4ff[11];
172 __IO uint32_t btle;
173 __R uint32_t rsv_0x504_0xb0f[387];
174 __IO uint32_t usbhs;
175 __R uint32_t rsv_0xb14_0xb5f[19];
176 __IO uint32_t sdio;
177 __R uint32_t rsv_0xb64_0xbbf[23];
178 __IO uint32_t spixfm_fifo;
179 __R uint32_t rsv_0xbc4_0xbdf[7];
180 __IO uint32_t spi0;
181 __R uint32_t rsv_0xbe4_0xeff[199];
182 __IO uint32_t sysram0;
183 __R uint32_t rsv_0xf04_0xf0f[3];
184 __IO uint32_t sysram1;
185 __R uint32_t rsv_0xf14_0xf1f[3];
186 __IO uint32_t sysram2;
187 __R uint32_t rsv_0xf24_0xf2f[3];
188 __IO uint32_t sysram3;
189 __R uint32_t rsv_0xf34_0xf3f[3];
190 __IO uint32_t sysram4;
191 __R uint32_t rsv_0xf44_0xf4f[3];
192 __IO uint32_t sysram5;
193 __R uint32_t rsv_0xf54_0xf5f[3];
194 __IO uint32_t sysram6_11;
195 __R uint32_t rsv_0xf64_0x11cf[155];
196 __IO uint32_t i2c0_bus1;
197 __R uint32_t rsv_0x11d4_0x11df[3];
198 __IO uint32_t i2c1_bus1;
199 __R uint32_t rsv_0x11e4_0x11ef[3];
200 __IO uint32_t i2c2_bus1;
201 __R uint32_t rsv_0x11f4_0x13bf[115];
202 __IO uint32_t ptg_bus1;
203} mxc_rpu_regs_t;
204
205/* Register offsets for module RPU */
212#define MXC_R_RPU_GCR ((uint32_t)0x00000000UL)
213#define MXC_R_RPU_SIR ((uint32_t)0x00000004UL)
214#define MXC_R_RPU_FCR ((uint32_t)0x00000008UL)
215#define MXC_R_RPU_TPU ((uint32_t)0x00000010UL)
216#define MXC_R_RPU_RPU ((uint32_t)0x00000020UL)
217#define MXC_R_RPU_WDT0 ((uint32_t)0x00000030UL)
218#define MXC_R_RPU_WDT1 ((uint32_t)0x00000034UL)
219#define MXC_R_RPU_WDT2 ((uint32_t)0x00000038UL)
220#define MXC_R_RPU_SMON ((uint32_t)0x00000040UL)
221#define MXC_R_RPU_SIMO ((uint32_t)0x00000044UL)
222#define MXC_R_RPU_DVS ((uint32_t)0x00000048UL)
223#define MXC_R_RPU_AES ((uint32_t)0x00000050UL)
224#define MXC_R_RPU_RTC ((uint32_t)0x00000060UL)
225#define MXC_R_RPU_WUT ((uint32_t)0x00000064UL)
226#define MXC_R_RPU_PWRSEQ ((uint32_t)0x00000068UL)
227#define MXC_R_RPU_MCR ((uint32_t)0x0000006CUL)
228#define MXC_R_RPU_GPIO0 ((uint32_t)0x00000080UL)
229#define MXC_R_RPU_GPIO1 ((uint32_t)0x00000090UL)
230#define MXC_R_RPU_TMR0 ((uint32_t)0x00000100UL)
231#define MXC_R_RPU_TMR1 ((uint32_t)0x00000110UL)
232#define MXC_R_RPU_TMR2 ((uint32_t)0x00000120UL)
233#define MXC_R_RPU_TMR3 ((uint32_t)0x00000130UL)
234#define MXC_R_RPU_TMR4 ((uint32_t)0x00000140UL)
235#define MXC_R_RPU_TMR5 ((uint32_t)0x00000150UL)
236#define MXC_R_RPU_HTIMER0 ((uint32_t)0x000001B0UL)
237#define MXC_R_RPU_HTIMER1 ((uint32_t)0x000001C0UL)
238#define MXC_R_RPU_I2C0_BUS0 ((uint32_t)0x000001D0UL)
239#define MXC_R_RPU_I2C1_BUS0 ((uint32_t)0x000001E0UL)
240#define MXC_R_RPU_I2C2_BUS0 ((uint32_t)0x000001F0UL)
241#define MXC_R_RPU_SPIXFM ((uint32_t)0x00000260UL)
242#define MXC_R_RPU_SPIXFC ((uint32_t)0x00000270UL)
243#define MXC_R_RPU_DMA0 ((uint32_t)0x00000280UL)
244#define MXC_R_RPU_FLC0 ((uint32_t)0x00000290UL)
245#define MXC_R_RPU_FLC1 ((uint32_t)0x00000294UL)
246#define MXC_R_RPU_ICC0 ((uint32_t)0x000002A0UL)
247#define MXC_R_RPU_ICC1 ((uint32_t)0x000002A4UL)
248#define MXC_R_RPU_SFCC ((uint32_t)0x000002F0UL)
249#define MXC_R_RPU_SRCC ((uint32_t)0x00000330UL)
250#define MXC_R_RPU_ADC ((uint32_t)0x00000340UL)
251#define MXC_R_RPU_DMA1 ((uint32_t)0x00000350UL)
252#define MXC_R_RPU_SDMA ((uint32_t)0x00000360UL)
253#define MXC_R_RPU_SDHCCTRL ((uint32_t)0x00000370UL)
254#define MXC_R_RPU_SPIXR ((uint32_t)0x000003A0UL)
255#define MXC_R_RPU_PTG_BUS0 ((uint32_t)0x000003C0UL)
256#define MXC_R_RPU_OWM ((uint32_t)0x000003D0UL)
257#define MXC_R_RPU_SEMA ((uint32_t)0x000003E0UL)
258#define MXC_R_RPU_UART0 ((uint32_t)0x00000420UL)
259#define MXC_R_RPU_UART1 ((uint32_t)0x00000430UL)
260#define MXC_R_RPU_UART2 ((uint32_t)0x00000440UL)
261#define MXC_R_RPU_SPI1 ((uint32_t)0x00000460UL)
262#define MXC_R_RPU_SPI2 ((uint32_t)0x00000470UL)
263#define MXC_R_RPU_AUDIO ((uint32_t)0x000004C0UL)
264#define MXC_R_RPU_TRNG ((uint32_t)0x000004D0UL)
265#define MXC_R_RPU_BTLE ((uint32_t)0x00000500UL)
266#define MXC_R_RPU_USBHS ((uint32_t)0x00000B10UL)
267#define MXC_R_RPU_SDIO ((uint32_t)0x00000B60UL)
268#define MXC_R_RPU_SPIXFM_FIFO ((uint32_t)0x00000BC0UL)
269#define MXC_R_RPU_SPI0 ((uint32_t)0x00000BE0UL)
270#define MXC_R_RPU_SYSRAM0 ((uint32_t)0x00000F00UL)
271#define MXC_R_RPU_SYSRAM1 ((uint32_t)0x00000F10UL)
272#define MXC_R_RPU_SYSRAM2 ((uint32_t)0x00000F20UL)
273#define MXC_R_RPU_SYSRAM3 ((uint32_t)0x00000F30UL)
274#define MXC_R_RPU_SYSRAM4 ((uint32_t)0x00000F40UL)
275#define MXC_R_RPU_SYSRAM5 ((uint32_t)0x00000F50UL)
276#define MXC_R_RPU_SYSRAM6_11 ((uint32_t)0x00000F60UL)
277#define MXC_R_RPU_I2C0_BUS1 ((uint32_t)0x000011D0UL)
278#define MXC_R_RPU_I2C1_BUS1 ((uint32_t)0x000011E0UL)
279#define MXC_R_RPU_I2C2_BUS1 ((uint32_t)0x000011F0UL)
280#define MXC_R_RPU_PTG_BUS1 ((uint32_t)0x000013C0UL)
289#define MXC_F_RPU_GCR_ACCESS_POS 0
290#define MXC_F_RPU_GCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GCR_ACCESS_POS))
300#define MXC_F_RPU_SIR_ACCESS_POS 0
301#define MXC_F_RPU_SIR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SIR_ACCESS_POS))
311#define MXC_F_RPU_FCR_ACCESS_POS 0
312#define MXC_F_RPU_FCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FCR_ACCESS_POS))
322#define MXC_F_RPU_TPU_ACCESS_POS 0
323#define MXC_F_RPU_TPU_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TPU_ACCESS_POS))
333#define MXC_F_RPU_RPU_ACCESS_POS 0
334#define MXC_F_RPU_RPU_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_RPU_ACCESS_POS))
344#define MXC_F_RPU_WDT0_ACCESS_POS 0
345#define MXC_F_RPU_WDT0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT0_ACCESS_POS))
355#define MXC_F_RPU_WDT1_ACCESS_POS 0
356#define MXC_F_RPU_WDT1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT1_ACCESS_POS))
366#define MXC_F_RPU_WDT2_ACCESS_POS 0
367#define MXC_F_RPU_WDT2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT2_ACCESS_POS))
377#define MXC_F_RPU_SMON_ACCESS_POS 0
378#define MXC_F_RPU_SMON_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SMON_ACCESS_POS))
388#define MXC_F_RPU_SIMO_ACCESS_POS 0
389#define MXC_F_RPU_SIMO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SIMO_ACCESS_POS))
399#define MXC_F_RPU_DVS_ACCESS_POS 0
400#define MXC_F_RPU_DVS_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DVS_ACCESS_POS))
410#define MXC_F_RPU_AES_ACCESS_POS 0
411#define MXC_F_RPU_AES_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_AES_ACCESS_POS))
421#define MXC_F_RPU_RTC_ACCESS_POS 0
422#define MXC_F_RPU_RTC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_RTC_ACCESS_POS))
432#define MXC_F_RPU_WUT_ACCESS_POS 0
433#define MXC_F_RPU_WUT_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WUT_ACCESS_POS))
443#define MXC_F_RPU_PWRSEQ_ACCESS_POS 0
444#define MXC_F_RPU_PWRSEQ_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PWRSEQ_ACCESS_POS))
454#define MXC_F_RPU_MCR_ACCESS_POS 0
455#define MXC_F_RPU_MCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_MCR_ACCESS_POS))
465#define MXC_F_RPU_GPIO0_ACCESS_POS 0
466#define MXC_F_RPU_GPIO0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GPIO0_ACCESS_POS))
476#define MXC_F_RPU_GPIO1_ACCESS_POS 0
477#define MXC_F_RPU_GPIO1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GPIO1_ACCESS_POS))
487#define MXC_F_RPU_TMR0_ACCESS_POS 0
488#define MXC_F_RPU_TMR0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR0_ACCESS_POS))
498#define MXC_F_RPU_TMR1_ACCESS_POS 0
499#define MXC_F_RPU_TMR1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR1_ACCESS_POS))
509#define MXC_F_RPU_TMR2_ACCESS_POS 0
510#define MXC_F_RPU_TMR2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR2_ACCESS_POS))
520#define MXC_F_RPU_TMR3_ACCESS_POS 0
521#define MXC_F_RPU_TMR3_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR3_ACCESS_POS))
531#define MXC_F_RPU_TMR4_ACCESS_POS 0
532#define MXC_F_RPU_TMR4_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR4_ACCESS_POS))
542#define MXC_F_RPU_TMR5_ACCESS_POS 0
543#define MXC_F_RPU_TMR5_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR5_ACCESS_POS))
553#define MXC_F_RPU_HTIMER0_ACCESS_POS 0
554#define MXC_F_RPU_HTIMER0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_HTIMER0_ACCESS_POS))
564#define MXC_F_RPU_HTIMER1_ACCESS_POS 0
565#define MXC_F_RPU_HTIMER1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_HTIMER1_ACCESS_POS))
575#define MXC_F_RPU_I2C0_BUS0_ACCESS_POS 0
576#define MXC_F_RPU_I2C0_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C0_BUS0_ACCESS_POS))
586#define MXC_F_RPU_I2C1_BUS0_ACCESS_POS 0
587#define MXC_F_RPU_I2C1_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C1_BUS0_ACCESS_POS))
597#define MXC_F_RPU_I2C2_BUS0_ACCESS_POS 0
598#define MXC_F_RPU_I2C2_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C2_BUS0_ACCESS_POS))
608#define MXC_F_RPU_SPIXFM_ACCESS_POS 0
609#define MXC_F_RPU_SPIXFM_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFM_ACCESS_POS))
619#define MXC_F_RPU_SPIXFC_ACCESS_POS 0
620#define MXC_F_RPU_SPIXFC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFC_ACCESS_POS))
630#define MXC_F_RPU_DMA0_ACCESS_POS 0
631#define MXC_F_RPU_DMA0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DMA0_ACCESS_POS))
641#define MXC_F_RPU_FLC0_ACCESS_POS 0
642#define MXC_F_RPU_FLC0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FLC0_ACCESS_POS))
652#define MXC_F_RPU_FLC1_ACCESS_POS 0
653#define MXC_F_RPU_FLC1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FLC1_ACCESS_POS))
663#define MXC_F_RPU_ICC0_ACCESS_POS 0
664#define MXC_F_RPU_ICC0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ICC0_ACCESS_POS))
674#define MXC_F_RPU_ICC1_ACCESS_POS 0
675#define MXC_F_RPU_ICC1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ICC1_ACCESS_POS))
685#define MXC_F_RPU_SFCC_ACCESS_POS 0
686#define MXC_F_RPU_SFCC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SFCC_ACCESS_POS))
696#define MXC_F_RPU_SRCC_ACCESS_POS 0
697#define MXC_F_RPU_SRCC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SRCC_ACCESS_POS))
707#define MXC_F_RPU_ADC_ACCESS_POS 0
708#define MXC_F_RPU_ADC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ADC_ACCESS_POS))
718#define MXC_F_RPU_DMA1_ACCESS_POS 0
719#define MXC_F_RPU_DMA1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DMA1_ACCESS_POS))
729#define MXC_F_RPU_SDMA_ACCESS_POS 0
730#define MXC_F_RPU_SDMA_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDMA_ACCESS_POS))
740#define MXC_F_RPU_SDHCCTRL_ACCESS_POS 0
741#define MXC_F_RPU_SDHCCTRL_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDHCCTRL_ACCESS_POS))
751#define MXC_F_RPU_SPIXR_ACCESS_POS 0
752#define MXC_F_RPU_SPIXR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXR_ACCESS_POS))
762#define MXC_F_RPU_PTG_BUS0_ACCESS_POS 0
763#define MXC_F_RPU_PTG_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PTG_BUS0_ACCESS_POS))
773#define MXC_F_RPU_OWM_ACCESS_POS 0
774#define MXC_F_RPU_OWM_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_OWM_ACCESS_POS))
784#define MXC_F_RPU_SEMA_ACCESS_POS 0
785#define MXC_F_RPU_SEMA_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SEMA_ACCESS_POS))
795#define MXC_F_RPU_UART0_ACCESS_POS 0
796#define MXC_F_RPU_UART0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART0_ACCESS_POS))
806#define MXC_F_RPU_UART1_ACCESS_POS 0
807#define MXC_F_RPU_UART1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART1_ACCESS_POS))
817#define MXC_F_RPU_UART2_ACCESS_POS 0
818#define MXC_F_RPU_UART2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART2_ACCESS_POS))
828#define MXC_F_RPU_SPI1_ACCESS_POS 0
829#define MXC_F_RPU_SPI1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI1_ACCESS_POS))
839#define MXC_F_RPU_SPI2_ACCESS_POS 0
840#define MXC_F_RPU_SPI2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI2_ACCESS_POS))
850#define MXC_F_RPU_AUDIO_ACCESS_POS 0
851#define MXC_F_RPU_AUDIO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_AUDIO_ACCESS_POS))
861#define MXC_F_RPU_TRNG_ACCESS_POS 0
862#define MXC_F_RPU_TRNG_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TRNG_ACCESS_POS))
872#define MXC_F_RPU_BTLE_ACCESS_POS 0
873#define MXC_F_RPU_BTLE_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_BTLE_ACCESS_POS))
883#define MXC_F_RPU_USBHS_ACCESS_POS 0
884#define MXC_F_RPU_USBHS_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_USBHS_ACCESS_POS))
894#define MXC_F_RPU_SDIO_ACCESS_POS 0
895#define MXC_F_RPU_SDIO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDIO_ACCESS_POS))
905#define MXC_F_RPU_SPIXFM_FIFO_ACCESS_POS 0
906#define MXC_F_RPU_SPIXFM_FIFO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFM_FIFO_ACCESS_POS))
916#define MXC_F_RPU_SPI0_ACCESS_POS 0
917#define MXC_F_RPU_SPI0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI0_ACCESS_POS))
927#define MXC_F_RPU_SYSRAM0_ACCESS_POS 0
928#define MXC_F_RPU_SYSRAM0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM0_ACCESS_POS))
938#define MXC_F_RPU_SYSRAM1_ACCESS_POS 0
939#define MXC_F_RPU_SYSRAM1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM1_ACCESS_POS))
949#define MXC_F_RPU_SYSRAM2_ACCESS_POS 0
950#define MXC_F_RPU_SYSRAM2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM2_ACCESS_POS))
960#define MXC_F_RPU_SYSRAM3_ACCESS_POS 0
961#define MXC_F_RPU_SYSRAM3_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM3_ACCESS_POS))
971#define MXC_F_RPU_SYSRAM4_ACCESS_POS 0
972#define MXC_F_RPU_SYSRAM4_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM4_ACCESS_POS))
982#define MXC_F_RPU_SYSRAM5_ACCESS_POS 0
983#define MXC_F_RPU_SYSRAM5_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM5_ACCESS_POS))
993#define MXC_F_RPU_SYSRAM6_11_ACCESS_POS 0
994#define MXC_F_RPU_SYSRAM6_11_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM6_11_ACCESS_POS))
1004#define MXC_F_RPU_I2C0_BUS1_ACCESS_POS 0
1005#define MXC_F_RPU_I2C0_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C0_BUS1_ACCESS_POS))
1015#define MXC_F_RPU_I2C1_BUS1_ACCESS_POS 0
1016#define MXC_F_RPU_I2C1_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C1_BUS1_ACCESS_POS))
1026#define MXC_F_RPU_I2C2_BUS1_ACCESS_POS 0
1027#define MXC_F_RPU_I2C2_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C2_BUS1_ACCESS_POS))
1037#define MXC_F_RPU_PTG_BUS1_ACCESS_POS 0
1038#define MXC_F_RPU_PTG_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PTG_BUS1_ACCESS_POS))
1042#ifdef __cplusplus
1043}
1044#endif
1045
1046#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_
mxc_rpu_regs_t::gpio0
__IO uint32_t gpio0
Definition: rpu_regs.h:100
mxc_rpu_regs_t::sdhcctrl
__IO uint32_t sdhcctrl
Definition: rpu_regs.h:148
mxc_rpu_regs_t::pwrseq
__IO uint32_t pwrseq
Definition: rpu_regs.h:97
mxc_rpu_regs_t::icc0
__IO uint32_t icc0
Definition: rpu_regs.h:135
mxc_rpu_regs_t::flc1
__IO uint32_t flc1
Definition: rpu_regs.h:133
mxc_rpu_regs_t::sdio
__IO uint32_t sdio
Definition: rpu_regs.h:176
mxc_rpu_regs_t::dma1
__IO uint32_t dma1
Definition: rpu_regs.h:144
mxc_rpu_regs_t::tmr5
__IO uint32_t tmr5
Definition: rpu_regs.h:114
mxc_rpu_regs_t::uart1
__IO uint32_t uart1
Definition: rpu_regs.h:160
mxc_rpu_regs_t::aes
__IO uint32_t aes
Definition: rpu_regs.h:93
mxc_rpu_regs_t::smon
__IO uint32_t smon
Definition: rpu_regs.h:89
mxc_rpu_regs_t::mcr
__IO uint32_t mcr
Definition: rpu_regs.h:98
mxc_rpu_regs_t::tmr2
__IO uint32_t tmr2
Definition: rpu_regs.h:108
mxc_rpu_regs_t::gpio1
__IO uint32_t gpio1
Definition: rpu_regs.h:102
mxc_rpu_regs_t::i2c2_bus1
__IO uint32_t i2c2_bus1
Definition: rpu_regs.h:200
mxc_rpu_regs_t::fcr
__IO uint32_t fcr
Definition: rpu_regs.h:79
mxc_rpu_regs_t::tmr0
__IO uint32_t tmr0
Definition: rpu_regs.h:104
mxc_rpu_regs_t::wdt1
__IO uint32_t wdt1
Definition: rpu_regs.h:86
mxc_rpu_regs_t::sysram3
__IO uint32_t sysram3
Definition: rpu_regs.h:188
mxc_rpu_regs_t::sysram6_11
__IO uint32_t sysram6_11
Definition: rpu_regs.h:194
mxc_rpu_regs_t::owm
__IO uint32_t owm
Definition: rpu_regs.h:154
mxc_rpu_regs_t::i2c1_bus0
__IO uint32_t i2c1_bus0
Definition: rpu_regs.h:122
mxc_rpu_regs_t::adc
__IO uint32_t adc
Definition: rpu_regs.h:142
mxc_rpu_regs_t::i2c2_bus0
__IO uint32_t i2c2_bus0
Definition: rpu_regs.h:124
mxc_rpu_regs_t::sema
__IO uint32_t sema
Definition: rpu_regs.h:156
mxc_rpu_regs_t::tmr4
__IO uint32_t tmr4
Definition: rpu_regs.h:112
mxc_rpu_regs_t::sfcc
__IO uint32_t sfcc
Definition: rpu_regs.h:138
mxc_rpu_regs_t::rpu
__IO uint32_t rpu
Definition: rpu_regs.h:83
mxc_rpu_regs_t::sysram4
__IO uint32_t sysram4
Definition: rpu_regs.h:190
mxc_rpu_regs_t::spi2
__IO uint32_t spi2
Definition: rpu_regs.h:166
mxc_rpu_regs_t::simo
__IO uint32_t simo
Definition: rpu_regs.h:90
mxc_rpu_regs_t::htimer1
__IO uint32_t htimer1
Definition: rpu_regs.h:118
mxc_rpu_regs_t::i2c0_bus1
__IO uint32_t i2c0_bus1
Definition: rpu_regs.h:196
mxc_rpu_regs_t::htimer0
__IO uint32_t htimer0
Definition: rpu_regs.h:116
mxc_rpu_regs_t::rtc
__IO uint32_t rtc
Definition: rpu_regs.h:95
mxc_rpu_regs_t::i2c1_bus1
__IO uint32_t i2c1_bus1
Definition: rpu_regs.h:198
mxc_rpu_regs_t::trng
__IO uint32_t trng
Definition: rpu_regs.h:170
mxc_rpu_regs_t::dma0
__IO uint32_t dma0
Definition: rpu_regs.h:130
mxc_rpu_regs_t::uart2
__IO uint32_t uart2
Definition: rpu_regs.h:162
mxc_rpu_regs_t::gcr
__IO uint32_t gcr
Definition: rpu_regs.h:77
mxc_rpu_regs_t::tmr3
__IO uint32_t tmr3
Definition: rpu_regs.h:110
mxc_rpu_regs_t::wdt2
__IO uint32_t wdt2
Definition: rpu_regs.h:87
mxc_rpu_regs_t::dvs
__IO uint32_t dvs
Definition: rpu_regs.h:91
mxc_rpu_regs_t::btle
__IO uint32_t btle
Definition: rpu_regs.h:172
mxc_rpu_regs_t::spixfm
__IO uint32_t spixfm
Definition: rpu_regs.h:126
mxc_rpu_regs_t::ptg_bus1
__IO uint32_t ptg_bus1
Definition: rpu_regs.h:202
mxc_rpu_regs_t::ptg_bus0
__IO uint32_t ptg_bus0
Definition: rpu_regs.h:152
mxc_rpu_regs_t::spixr
__IO uint32_t spixr
Definition: rpu_regs.h:150
mxc_rpu_regs_t::flc0
__IO uint32_t flc0
Definition: rpu_regs.h:132
mxc_rpu_regs_t::spixfc
__IO uint32_t spixfc
Definition: rpu_regs.h:128
mxc_rpu_regs_t::spi1
__IO uint32_t spi1
Definition: rpu_regs.h:164
mxc_rpu_regs_t::usbhs
__IO uint32_t usbhs
Definition: rpu_regs.h:174
mxc_rpu_regs_t::wdt0
__IO uint32_t wdt0
Definition: rpu_regs.h:85
mxc_rpu_regs_t::sysram2
__IO uint32_t sysram2
Definition: rpu_regs.h:186
mxc_rpu_regs_t::uart0
__IO uint32_t uart0
Definition: rpu_regs.h:158
mxc_rpu_regs_t::sysram1
__IO uint32_t sysram1
Definition: rpu_regs.h:184
mxc_rpu_regs_t::wut
__IO uint32_t wut
Definition: rpu_regs.h:96
mxc_rpu_regs_t::srcc
__IO uint32_t srcc
Definition: rpu_regs.h:140
mxc_rpu_regs_t::spixfm_fifo
__IO uint32_t spixfm_fifo
Definition: rpu_regs.h:178
mxc_rpu_regs_t::sysram0
__IO uint32_t sysram0
Definition: rpu_regs.h:182
mxc_rpu_regs_t::i2c0_bus0
__IO uint32_t i2c0_bus0
Definition: rpu_regs.h:120
mxc_rpu_regs_t::icc1
__IO uint32_t icc1
Definition: rpu_regs.h:136
mxc_rpu_regs_t::tmr1
__IO uint32_t tmr1
Definition: rpu_regs.h:106
mxc_rpu_regs_t::sdma
__IO uint32_t sdma
Definition: rpu_regs.h:146
mxc_rpu_regs_t::audio
__IO uint32_t audio
Definition: rpu_regs.h:168
mxc_rpu_regs_t::spi0
__IO uint32_t spi0
Definition: rpu_regs.h:180
mxc_rpu_regs_t::tpu
__IO uint32_t tpu
Definition: rpu_regs.h:81
mxc_rpu_regs_t::sir
__IO uint32_t sir
Definition: rpu_regs.h:78
mxc_rpu_regs_t::sysram5
__IO uint32_t sysram5
Definition: rpu_regs.h:192
mxc_rpu_regs_t
Definition: rpu_regs.h:76