Modules

Here is a list of all modules:

[detail level 123]

▼AES
►AES_Registers	Registers, Bit Masks and Bit Positions for the AES Peripheral Module
Register Offsets	AES Peripheral Register Offsets from the AES Base Peripheral Address
AES_CTRL	AES Control Register
AES_STATUS	AES Status Register
AES_INTFL	AES Interrupt Flag Register
AES_INTEN	AES Interrupt Enable Register
AES_FIFO	AES Data Register
►AESKEYS_Registers	Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module
Register Offsets	AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address
▼CRC
►CRC_Registers	Registers, Bit Masks and Bit Positions for the CRC Peripheral Module
Register Offsets	CRC Peripheral Register Offsets from the CRC Base Peripheral Address
CRC_CTRL	CRC Control
CRC_DATAIN32	CRC Data Input
CRC_DATAIN16	CRC Data Input
CRC_DATAIN8	CRC Data Input
CRC_POLY	CRC Polynomial
CRC_VAL	Current CRC Value
▼Direct Memory Access (DMA)
►DMA_Registers	Registers, Bit Masks and Bit Positions for the DMA Peripheral Module
Register Offsets	DMA Peripheral Register Offsets from the DMA Base Peripheral Address
DMA_INTEN	DMA Control Register
DMA_INTFL	DMA Interrupt Register
DMA_CTRL	DMA Channel Control Register
DMA_STATUS	DMA Channel Status Register
DMA_SRC	Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD
DMA_DST	Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD
DMA_CNT	DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered
DMA_SRCRLD	Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition
DMA_DSTRLD	Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition
DMA_CNTRLD	DMA Channel Count Reload Register
▼Flash Controller (FLC)
►FLC_Registers	Registers, Bit Masks and Bit Positions for the FLC Peripheral Module
Register Offsets	FLC Peripheral Register Offsets from the FLC Base Peripheral Address
FLC_ADDR	Flash Write Address
FLC_CLKDIV	Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller
FLC_CTRL	Flash Control Register
FLC_INTR	Flash Interrupt Register
FLC_ECCDATA	ECC Data Register
FLC_DATA	Flash Write Data
FLC_ACTRL	Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero
FLC_WELR0	WELR0
FLC_WELR1	WELR1
FLC_RLR0	RLR0
FLC_RLR1	RLR1
▼General-Purpose Input/Output (GPIO)
►Port and Pin Definitions
Port Definitions
Pin Definitions
►GPIO_Registers	Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module
Register Offsets	GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address
GPIO_EN0	GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port
GPIO_EN0_SET	GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register
GPIO_EN0_CLR	GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register
GPIO_OUTEN	GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port
GPIO_OUTEN_SET	GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register
GPIO_OUTEN_CLR	GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register
GPIO_OUT	GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers
GPIO_OUT_SET	GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register
GPIO_OUT_CLR	GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register
GPIO_IN	GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port
GPIO_INTMODE	GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port
GPIO_INTPOL	GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port
GPIO_INTEN	GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port
GPIO_INTEN_SET	GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register
GPIO_INTEN_CLR	GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register
GPIO_INTFL	GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port
GPIO_INTFL_CLR	GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register
GPIO_WKEN	GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port
GPIO_WKEN_SET	GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register
GPIO_WKEN_CLR	GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register
GPIO_DUALEDGE	GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port
GPIO_PADCTRL0	GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port
GPIO_PADCTRL1	GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port
GPIO_EN1	GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port
GPIO_EN1_SET	GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register
GPIO_EN1_CLR	GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register
GPIO_EN2	GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port
GPIO_EN2_SET	GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register
GPIO_EN2_CLR	GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register
GPIO_HYSEN	GPIO Input Hysteresis Enable
GPIO_SRSEL	GPIO Slew Rate Enable Register
GPIO_DS0	GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode
GPIO_DS1	GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode
GPIO_PS	GPIO Pull Select Mode
▼I2C
►I2C_Registers	Registers, Bit Masks and Bit Positions for the I2C Peripheral Module
Register Offsets	I2C Peripheral Register Offsets from the I2C Base Peripheral Address
I2C_CTRL	Control Register0
I2C_STATUS	Status Register
I2C_INTFL0	Interrupt Status Register
I2C_INTEN0	Interrupt Enable Register
I2C_INTFL1	Interrupt Status Register 1
I2C_INTEN1	Interrupt Staus Register 1
I2C_FIFOLEN	FIFO Configuration Register
I2C_RXCTRL0	Receive Control Register 0
I2C_RXCTRL1	Receive Control Register 1
I2C_TXCTRL0	Transmit Control Register 0
I2C_TXCTRL1	Transmit Control Register 1
I2C_FIFO	Data Register
I2C_MSTCTRL	Master Control Register
I2C_CLKLO	Clock Low Register
I2C_CLKHI	Clock high Register
I2C_HSCLK	Clock high Register
I2C_TIMEOUT	Timeout Register
I2C_SLAVE	Slave Address Register
I2C_DMA	DMA Register
▼Inter-Integrated Sound (I2S)
►I2S_Registers	Registers, Bit Masks and Bit Positions for the I2S Peripheral Module
Register Offsets	I2S Peripheral Register Offsets from the I2S Base Peripheral Address
I2S_CTRL0CH0	Global mode channel
I2S_CTRL1CH0	Local channel Setup
I2S_DMACH0	DMA Control
I2S_FIFOCH0	I2S Fifo
I2S_INTFL	ISR Status
I2S_INTEN	Interrupt Enable
I2S_EXTSETUP	Ext Control
▼ICC
►ICC_Registers	Registers, Bit Masks and Bit Positions for the ICC Peripheral Module
Register Offsets	ICC Peripheral Register Offsets from the ICC Base Peripheral Address
ICC_INFO	Cache ID Register
ICC_SZ	Memory Configuration Register
ICC_CTRL	Cache Control and Status Register
ICC_INVALIDATE	Invalidate All Registers
▼Low Power (LP)
►PWRSEQ_Registers	Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module
Register Offsets	PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address
PWRSEQ_LPCN	Low Power Control Register
PWRSEQ_LPWKST0	Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0
PWRSEQ_LPWKEN0	Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0
PWRSEQ_LPPWKST	Low Power Peripheral Wakeup Status Register
PWRSEQ_LPPWKEN	Low Power Peripheral Wakeup Enable Register
PWRSEQ_LPMEMSD	Low Power Memory Shutdown Control
Assertion Checks for Debugging	Assertion checks for debugging
Delay Utility Functions	Asynchronous delay routines based on the SysTick Timer
Error Codes	A list of common error codes used by the API
Exclusive Access Locks	Lock functions to obtain and release a variable for exclusive access. These functions are marked interrupt safe if they are interrupt safe
System Configuration (MXC_SYS)
▼Real Time Clock (RTC)
►RTC_Registers	Registers, Bit Masks and Bit Positions for the RTC Peripheral Module
Register Offsets	RTC Peripheral Register Offsets from the RTC Base Peripheral Address
RTC_SEC	RTC Second Counter. This register contains the 32-bit second counter
RTC_SSEC	RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00
RTC_TODA	Time-of-day Alarm
RTC_SSECA	RTC sub-second alarm. This register contains the reload value for the sub- second alarm
RTC_CTRL	RTC Control Register
RTC_TRIM	RTC Trim Register
RTC_OSCCTRL	RTC Oscillator Control Register
▼SPI
►SPI_Registers	Registers, Bit Masks and Bit Positions for the SPI Peripheral Module
Register Offsets	SPI Peripheral Register Offsets from the SPI Base Peripheral Address
SPI_FIFO32	Register for reading and writing the FIFO
SPI_FIFO16	Register for reading and writing the FIFO
SPI_FIFO8	Register for reading and writing the FIFO
SPI_CTRL0	Register for controlling SPI peripheral
SPI_CTRL1	Register for controlling SPI peripheral
SPI_CTRL2	Register for controlling SPI peripheral
SPI_SSTIME	Register for controlling SPI peripheral/Slave Select Timing
SPI_CLKCTRL	Register for controlling SPI clock rate
SPI_DMA	Register for controlling DMA
SPI_INTFL	Register for reading and clearing interrupt flags. All bits are write 1 to clear
SPI_INTEN	Register for enabling interrupts
SPI_WKFL	Register for wake up flags. All bits in this register are write 1 to clear
SPI_WKEN	Register for wake up enable
SPI_STAT	SPI Status register
▼Timer (TMR)
►TMR_Registers	Registers, Bit Masks and Bit Positions for the TMR Peripheral Module
Register Offsets	TMR Peripheral Register Offsets from the TMR Base Peripheral Address
TMR_CNT	Timer Counter Register
TMR_CMP	Timer Compare Register
TMR_PWM	Timer PWM Register
TMR_INTFL	Timer Interrupt Status Register
TMR_CTRL0	Timer Control Register
TMR_NOLCMP	Timer Non-Overlapping Compare Register
TMR_CTRL1	Timer Configuration Register
TMR_WKFL	Timer Wakeup Status Register
▼TRNG
►TRNG_Registers	Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module
Register Offsets	TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address
TRNG_CTRL	TRNG Control Register
TRNG_STATUS	Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000
TRNG_DATA	Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000
▼UART
►UART_Registers	Registers, Bit Masks and Bit Positions for the UART Peripheral Module
Register Offsets	UART Peripheral Register Offsets from the UART Base Peripheral Address
UART_CTRL	Control register
UART_STATUS	Status register
UART_INT_EN	Interrupt Enable control register
UART_INT_FL	Interrupt status flags Control register
UART_CLKDIV	Clock Divider register
UART_OSR	Over Sampling Rate register
UART_TXPEEK	TX FIFO Output Peek register
UART_PNR	Pin register
UART_FIFO	FIFO Read/Write register
UART_DMA	DMA Configuration register
UART_WKEN	Wake up enable Control register
UART_WKFL	Wake up Flags register
▼WDT
►WDT_Registers	Registers, Bit Masks and Bit Positions for the WDT Peripheral Module
Register Offsets	WDT Peripheral Register Offsets from the WDT Base Peripheral Address
WDT_CTRL	Watchdog Timer Control Register
WDT_RST	Windowed Watchdog Timer Reset Register
WDT_CLKSEL	Windowed Watchdog Timer Clock Select Register
WDT_CNT	Windowed Watchdog Timer Count Register
▼AES_KEY_Registers	Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module
Register Offsets	AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address
▼ECC_Registers	Registers, Bit Masks and Bit Positions for the ECC Peripheral Module
Register Offsets	ECC Peripheral Register Offsets from the ECC Base Peripheral Address
ECC_EN	ECC Enable Register
▼FCR_Registers	Registers, Bit Masks and Bit Positions for the FCR Peripheral Module
Register Offsets	FCR Peripheral Register Offsets from the FCR Base Peripheral Address
FCR_FCTRL0	Register 0
FCR_AUTOCAL0	Register 1
FCR_AUTOCAL1	Register 2
FCR_AUTOCAL2	Register 3
▼GCR_Registers	Registers, Bit Masks and Bit Positions for the GCR Peripheral Module
Register Offsets	GCR Peripheral Register Offsets from the GCR Base Peripheral Address
GCR_SYSCTRL	System Control
GCR_RST0	Reset
GCR_CLKCTRL	Clock Control
GCR_PM	Power Management
GCR_PCLKDIV	Peripheral Clock Divider
GCR_PCLKDIS0	Peripheral Clock Disable
GCR_MEMCTRL	Memory Clock Control Register
GCR_MEMZ	Memory Zeroize Control
GCR_SYSST	System Status Register
GCR_RST1	Reset 1
GCR_PCLKDIS1	Peripheral Clock Disable
GCR_EVENTEN	Event Enable Register
GCR_REVISION	Revision Register
GCR_SYSIE	System Status Interrupt Enable Register
GCR_ECCERR	ECC Error Register
GCR_ECCCED	ECC Not Double Error Detect Register
GCR_ECCIE	ECC IRQ Enable Register
GCR_ECCADDR	ECC Error Address Register
▼MCR_Registers	Registers, Bit Masks and Bit Positions for the MCR Peripheral Module
Register Offsets	MCR Peripheral Register Offsets from the MCR Base Peripheral Address
MCR_RST	Reset control register 0
MCR_LPPIOCTRL	Low-power peripheral IO control
MCR_CLKDIS	Peripheral clock control register
▼SIR_Registers	Registers, Bit Masks and Bit Positions for the SIR Peripheral Module
Register Offsets	SIR Peripheral Register Offsets from the SIR Base Peripheral Address
SIR_SIR_STATUS	System Initialization Status Register
SIR_SIR_ADDR	Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)