fcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t fctrl0;               
    __IO uint32_t autocal0;             
    __IO uint32_t autocal1;             
    __IO uint32_t autocal2;             
    __I  uint32_t ts0;                  
    __I  uint32_t ts1;                  
    __IO uint32_t adcreftrim0;          
    __IO uint32_t adcreftrim1;          
    __IO uint32_t adcreftrim2;          
    __IO uint32_t erfoks;               
} mxc_fcr_regs_t;
 
/* Register offsets for module FCR */
#define MXC_R_FCR_FCTRL0                   ((uint32_t)0x00000000UL) 
#define MXC_R_FCR_AUTOCAL0                 ((uint32_t)0x00000004UL) 
#define MXC_R_FCR_AUTOCAL1                 ((uint32_t)0x00000008UL) 
#define MXC_R_FCR_AUTOCAL2                 ((uint32_t)0x0000000CUL) 
#define MXC_R_FCR_TS0                      ((uint32_t)0x00000010UL) 
#define MXC_R_FCR_TS1                      ((uint32_t)0x00000014UL) 
#define MXC_R_FCR_ADCREFTRIM0              ((uint32_t)0x00000018UL) 
#define MXC_R_FCR_ADCREFTRIM1              ((uint32_t)0x0000001CUL) 
#define MXC_R_FCR_ADCREFTRIM2              ((uint32_t)0x00000020UL) 
#define MXC_R_FCR_ERFOKS                   ((uint32_t)0x00000024UL) 
#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS            0 
#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL                ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) 
#define MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS               8 
#define MXC_F_FCR_FCTRL0_KEYWIPE_SYS                   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS)) 
#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS        20 
#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) 
#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS        21 
#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS        22 
#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS        23 
#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS        24 
#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS        25 
#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) 
#define MXC_F_FCR_AUTOCAL0_SEL_POS                     0 
#define MXC_F_FCR_AUTOCAL0_SEL                         ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) 
#define MXC_F_FCR_AUTOCAL0_EN_POS                      1 
#define MXC_F_FCR_AUTOCAL0_EN                          ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) 
#define MXC_F_FCR_AUTOCAL0_LOAD_POS                    2 
#define MXC_F_FCR_AUTOCAL0_LOAD                        ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) 
#define MXC_F_FCR_AUTOCAL0_INVERT_POS                  3 
#define MXC_F_FCR_AUTOCAL0_INVERT                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) 
#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS                  4 
#define MXC_F_FCR_AUTOCAL0_ATOMIC                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) 
#define MXC_F_FCR_AUTOCAL0_GAIN_POS                    8 
#define MXC_F_FCR_AUTOCAL0_GAIN                        ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) 
#define MXC_F_FCR_AUTOCAL0_TRIM_POS                    23 
#define MXC_F_FCR_AUTOCAL0_TRIM                        ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) 
#define MXC_F_FCR_AUTOCAL1_INITIAL_POS                 0 
#define MXC_F_FCR_AUTOCAL1_INITIAL                     ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) 
#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS                 0 
#define MXC_F_FCR_AUTOCAL2_RUNTIME                     ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) 
#define MXC_F_FCR_AUTOCAL2_DIV_POS                     8 
#define MXC_F_FCR_AUTOCAL2_DIV                         ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) 
#define MXC_F_FCR_TS0_GAIN_POS                         0 
#define MXC_F_FCR_TS0_GAIN                             ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) 
#define MXC_F_FCR_TS1_OFFSET_POS                       0 
#define MXC_F_FCR_TS1_OFFSET                           ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_TS1_OFFSET_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VREFP_POS                0 
#define MXC_F_FCR_ADCREFTRIM0_VREFP                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VREFM_POS                8 
#define MXC_F_FCR_ADCREFTRIM0_VREFM                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM0_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VREFP_POS                0 
#define MXC_F_FCR_ADCREFTRIM1_VREFP                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VREFM_POS                8 
#define MXC_F_FCR_ADCREFTRIM1_VREFM                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM1_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS            0 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25                ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS          4 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25              ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS           8 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048               ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS         12 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048             ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM2_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) 
#define MXC_F_FCR_ERFOKS_CTRL_POS                      0 
#define MXC_F_FCR_ERFOKS_CTRL                          ((uint32_t)(0xFFFFUL << MXC_F_FCR_ERFOKS_CTRL_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_