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#define | MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) |
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#define | MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) |
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#define | MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) |
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#define | MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_FCR_TS0 ((uint32_t)0x00000010UL) |
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#define | MXC_R_FCR_TS1 ((uint32_t)0x00000014UL) |
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#define | MXC_R_FCR_ADCREFTRIM0 ((uint32_t)0x00000018UL) |
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#define | MXC_R_FCR_ADCREFTRIM1 ((uint32_t)0x0000001CUL) |
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#define | MXC_R_FCR_ADCREFTRIM2 ((uint32_t)0x00000020UL) |
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#define | MXC_R_FCR_ERFOKS ((uint32_t)0x00000024UL) |
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#define | MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 |
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#define | MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) |
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#define | MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS 8 |
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#define | MXC_F_FCR_FCTRL0_KEYWIPE_SYS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 |
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#define | MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 |
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#define | MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 |
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#define | MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 |
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#define | MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 |
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#define | MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) |
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#define | MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 |
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#define | MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_SEL_POS 0 |
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#define | MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_EN_POS 1 |
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#define | MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_LOAD_POS 2 |
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#define | MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_INVERT_POS 3 |
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#define | MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 |
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#define | MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_GAIN_POS 8 |
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#define | MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) |
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#define | MXC_F_FCR_AUTOCAL0_TRIM_POS 23 |
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#define | MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) |
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#define | MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 |
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#define | MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) |
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#define | MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 |
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#define | MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) |
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#define | MXC_F_FCR_AUTOCAL2_DIV_POS 8 |
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#define | MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) |
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#define | MXC_F_FCR_TS0_GAIN_POS 0 |
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#define | MXC_F_FCR_TS0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) |
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#define | MXC_F_FCR_TS1_OFFSET_POS 0 |
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#define | MXC_F_FCR_TS1_OFFSET ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_TS1_OFFSET_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM0_VREFP_POS 0 |
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#define | MXC_F_FCR_ADCREFTRIM0_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM0_VREFM_POS 8 |
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#define | MXC_F_FCR_ADCREFTRIM0_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM0_VCM_POS 16 |
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#define | MXC_F_FCR_ADCREFTRIM0_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS 24 |
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#define | MXC_F_FCR_ADCREFTRIM0_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM1_VREFP_POS 0 |
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#define | MXC_F_FCR_ADCREFTRIM1_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM1_VREFM_POS 8 |
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#define | MXC_F_FCR_ADCREFTRIM1_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM1_VCM_POS 16 |
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#define | MXC_F_FCR_ADCREFTRIM1_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS 24 |
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#define | MXC_F_FCR_ADCREFTRIM1_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS 0 |
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#define | MXC_F_FCR_ADCREFTRIM2_IDRV_1P25 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS 4 |
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#define | MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS 8 |
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#define | MXC_F_FCR_ADCREFTRIM2_IDRV_2P048 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS 12 |
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#define | MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_VCM_POS 16 |
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#define | MXC_F_FCR_ADCREFTRIM2_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) |
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#define | MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS 24 |
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#define | MXC_F_FCR_ADCREFTRIM2_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) |
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#define | MXC_F_FCR_ERFOKS_CTRL_POS 0 |
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#define | MXC_F_FCR_ERFOKS_CTRL ((uint32_t)(0xFFFFUL << MXC_F_FCR_ERFOKS_CTRL_POS)) |
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