mcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __R  uint32_t rsv_0x0;
    __IO uint32_t rst;                  
    __IO uint32_t clkctrl;              
    __IO uint32_t aincomp;              
    __IO uint32_t lppioctrl;            
    __R  uint32_t rsv_0x14_0x23[4];
    __IO uint32_t pclkdis;              
    __R  uint32_t rsv_0x28_0x33[3];
    __IO uint32_t aeskey;               
    __IO uint32_t adc_cfg0;             
    __IO uint32_t adc_cfg1;             
    __IO uint32_t adc_cfg2;             
    __IO uint32_t adc_cfg3;             
} mxc_mcr_regs_t;
 
/* Register offsets for module MCR */
#define MXC_R_MCR_RST                      ((uint32_t)0x00000004UL) 
#define MXC_R_MCR_CLKCTRL                  ((uint32_t)0x00000008UL) 
#define MXC_R_MCR_AINCOMP                  ((uint32_t)0x0000000CUL) 
#define MXC_R_MCR_LPPIOCTRL                ((uint32_t)0x00000010UL) 
#define MXC_R_MCR_PCLKDIS                  ((uint32_t)0x00000024UL) 
#define MXC_R_MCR_AESKEY                   ((uint32_t)0x00000034UL) 
#define MXC_R_MCR_ADC_CFG0                 ((uint32_t)0x00000038UL) 
#define MXC_R_MCR_ADC_CFG1                 ((uint32_t)0x0000003CUL) 
#define MXC_R_MCR_ADC_CFG2                 ((uint32_t)0x00000040UL) 
#define MXC_R_MCR_ADC_CFG3                 ((uint32_t)0x00000044UL) 
#define MXC_F_MCR_RST_LPTMR0_POS                       0 
#define MXC_F_MCR_RST_LPTMR0                           ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) 
#define MXC_F_MCR_RST_LPTMR1_POS                       1 
#define MXC_F_MCR_RST_LPTMR1                           ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) 
#define MXC_F_MCR_RST_LPUART0_POS                      2 
#define MXC_F_MCR_RST_LPUART0                          ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) 
#define MXC_F_MCR_RST_RTC_POS                          3 
#define MXC_F_MCR_RST_RTC                              ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) 
#define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS                 16 
#define MXC_F_MCR_CLKCTRL_ERTCO_PD                     ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) 
#define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS                 17 
#define MXC_F_MCR_CLKCTRL_ERTCO_EN                     ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) 
#define MXC_F_MCR_AINCOMP_PD_POS                       0 
#define MXC_F_MCR_AINCOMP_PD                           ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PD_POS)) 
#define MXC_F_MCR_AINCOMP_HYST_POS                     2 
#define MXC_F_MCR_AINCOMP_HYST                         ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_HYST_POS)) 
#define MXC_F_MCR_AINCOMP_NSEL_COMP0_POS               16 
#define MXC_F_MCR_AINCOMP_NSEL_COMP0                   ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP0_POS)) 
#define MXC_F_MCR_AINCOMP_PSEL_COMP0_POS               20 
#define MXC_F_MCR_AINCOMP_PSEL_COMP0                   ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP0_POS)) 
#define MXC_F_MCR_AINCOMP_NSEL_COMP1_POS               24 
#define MXC_F_MCR_AINCOMP_NSEL_COMP1                   ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP1_POS)) 
#define MXC_F_MCR_AINCOMP_PSEL_COMP1_POS               28 
#define MXC_F_MCR_AINCOMP_PSEL_COMP1                   ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP1_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS               0 
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I                   ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS               1 
#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O                   ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS               2 
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I                   ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS               3 
#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O                   ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS             4 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX                 ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS             5 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX                 ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS            6 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS                ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS            7 
#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS                ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) 
#define MXC_F_MCR_PCLKDIS_LPTMR0_POS                   0 
#define MXC_F_MCR_PCLKDIS_LPTMR0                       ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR0_POS)) 
#define MXC_F_MCR_PCLKDIS_LPTMR1_POS                   1 
#define MXC_F_MCR_PCLKDIS_LPTMR1                       ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR1_POS)) 
#define MXC_F_MCR_PCLKDIS_LPUART0_POS                  2 
#define MXC_F_MCR_PCLKDIS_LPUART0                      ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPUART0_POS)) 
#define MXC_F_MCR_AESKEY_PTR_POS                       0 
#define MXC_F_MCR_AESKEY_PTR                           ((uint32_t)(0xFFFFUL << MXC_F_MCR_AESKEY_PTR_POS)) 
#define MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS               0 
#define MXC_F_MCR_ADC_CFG0_LP_5K_DIS                   ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS)) 
#define MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS              1 
#define MXC_F_MCR_ADC_CFG0_LP_50K_DIS                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS)) 
#define MXC_F_MCR_ADC_CFG0_EXT_REF_POS                 2 
#define MXC_F_MCR_ADC_CFG0_EXT_REF                     ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_EXT_REF_POS)) 
#define MXC_F_MCR_ADC_CFG0_REF_SEL_POS                 3 
#define MXC_F_MCR_ADC_CFG0_REF_SEL                     ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_REF_SEL_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS              0 
#define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS              1 
#define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS              2 
#define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS              3 
#define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS              4 
#define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS              5 
#define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS              6 
#define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS              7 
#define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS              8 
#define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS              9 
#define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN                  ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS             10 
#define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN                 ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS             11 
#define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN                 ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS             12 
#define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN                 ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH0_POS                     0 
#define MXC_F_MCR_ADC_CFG2_CH0                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH0_POS)) 
#define MXC_V_MCR_ADC_CFG2_CH0_DIV1                    ((uint32_t)0x0UL) 
#define MXC_S_MCR_ADC_CFG2_CH0_DIV1                    (MXC_V_MCR_ADC_CFG2_CH0_DIV1 << MXC_F_MCR_ADC_CFG2_CH0_POS) 
#define MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K                 ((uint32_t)0x1UL) 
#define MXC_S_MCR_ADC_CFG2_CH0_DIV2_5K                 (MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K << MXC_F_MCR_ADC_CFG2_CH0_POS) 
#define MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K                ((uint32_t)0x2UL) 
#define MXC_S_MCR_ADC_CFG2_CH0_DIV2_50K                (MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K << MXC_F_MCR_ADC_CFG2_CH0_POS) 
#define MXC_F_MCR_ADC_CFG2_CH1_POS                     2 
#define MXC_F_MCR_ADC_CFG2_CH1                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH1_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH2_POS                     4 
#define MXC_F_MCR_ADC_CFG2_CH2                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH2_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH3_POS                     6 
#define MXC_F_MCR_ADC_CFG2_CH3                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH3_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH4_POS                     8 
#define MXC_F_MCR_ADC_CFG2_CH4                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH4_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH5_POS                     10 
#define MXC_F_MCR_ADC_CFG2_CH5                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH5_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH6_POS                     12 
#define MXC_F_MCR_ADC_CFG2_CH6                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH6_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH7_POS                     14 
#define MXC_F_MCR_ADC_CFG2_CH7                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH7_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH8_POS                     16 
#define MXC_F_MCR_ADC_CFG2_CH8                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH8_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH9_POS                     18 
#define MXC_F_MCR_ADC_CFG2_CH9                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH9_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH10_POS                    20 
#define MXC_F_MCR_ADC_CFG2_CH10                        ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH10_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH11_POS                    22 
#define MXC_F_MCR_ADC_CFG2_CH11                        ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH11_POS)) 
#define MXC_F_MCR_ADC_CFG2_CH12_POS                    24 
#define MXC_F_MCR_ADC_CFG2_CH12                        ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH12_POS)) 
#define MXC_F_MCR_ADC_CFG3_VREFM_POS                   0 
#define MXC_F_MCR_ADC_CFG3_VREFM                       ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFM_POS)) 
#define MXC_F_MCR_ADC_CFG3_VREFP_POS                   8 
#define MXC_F_MCR_ADC_CFG3_VREFP                       ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFP_POS)) 
#define MXC_F_MCR_ADC_CFG3_IDRV_POS                    16 
#define MXC_F_MCR_ADC_CFG3_IDRV                        ((uint32_t)(0xFUL << MXC_F_MCR_ADC_CFG3_IDRV_POS)) 
#define MXC_F_MCR_ADC_CFG3_VCM_POS                     20 
#define MXC_F_MCR_ADC_CFG3_VCM                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_VCM_POS)) 
#define MXC_F_MCR_ADC_CFG3_ATB_POS                     22 
#define MXC_F_MCR_ADC_CFG3_ATB                         ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_ATB_POS)) 
#define MXC_F_MCR_ADC_CFG3_D_IBOOST_POS                24 
#define MXC_F_MCR_ADC_CFG3_D_IBOOST                    ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG3_D_IBOOST_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_