fcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t fctrl0;               
    __IO uint32_t autocal0;             
    __IO uint32_t autocal1;             
    __IO uint32_t autocal2;             
    __IO uint32_t urvbootaddr;          
    __IO uint32_t urvctrl;              
    __IO uint32_t xo32mks;              
    __IO uint32_t sarbufcn;             
    __IO uint32_t ts0;                  
    __IO uint32_t ts1;                  
    __IO uint32_t adcreftrim0;          
    __IO uint32_t adcreftrim1;          
    __IO uint32_t adcreftrim2;          
} mxc_fcr_regs_t;
 
/* Register offsets for module FCR */
#define MXC_R_FCR_FCTRL0                   ((uint32_t)0x00000000UL) 
#define MXC_R_FCR_AUTOCAL0                 ((uint32_t)0x00000004UL) 
#define MXC_R_FCR_AUTOCAL1                 ((uint32_t)0x00000008UL) 
#define MXC_R_FCR_AUTOCAL2                 ((uint32_t)0x0000000CUL) 
#define MXC_R_FCR_URVBOOTADDR              ((uint32_t)0x00000010UL) 
#define MXC_R_FCR_URVCTRL                  ((uint32_t)0x00000014UL) 
#define MXC_R_FCR_XO32MKS                  ((uint32_t)0x00000018UL) 
#define MXC_R_FCR_SARBUFCN                 ((uint32_t)0x0000001CUL) 
#define MXC_R_FCR_TS0                      ((uint32_t)0x00000020UL) 
#define MXC_R_FCR_TS1                      ((uint32_t)0x00000024UL) 
#define MXC_R_FCR_ADCREFTRIM0              ((uint32_t)0x00000028UL) 
#define MXC_R_FCR_ADCREFTRIM1              ((uint32_t)0x0000002CUL) 
#define MXC_R_FCR_ADCREFTRIM2              ((uint32_t)0x00000030UL) 
#define MXC_F_FCR_FCTRL0_RDSGCSEL_POS                  0 
#define MXC_F_FCR_FCTRL0_RDSGCSEL                      ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_RDSGCSEL_POS)) 
#define MXC_F_FCR_FCTRL0_RDSGCSET_POS                  6 
#define MXC_F_FCR_FCTRL0_RDSGCSET                      ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_RDSGCSET_POS)) 
#define MXC_F_FCR_FCTRL0_HYPERCGDLY_POS                8 
#define MXC_F_FCR_FCTRL0_HYPERCGDLY                    ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_HYPERCGDLY_POS)) 
#define MXC_F_FCR_FCTRL0_USBCLKSEL_POS                 16 
#define MXC_F_FCR_FCTRL0_USBCLKSEL                     ((uint32_t)(0x3UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) 
#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS                 20 
#define MXC_F_FCR_FCTRL0_I2C0DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS                 21 
#define MXC_F_FCR_FCTRL0_I2C0DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS                 22 
#define MXC_F_FCR_FCTRL0_I2C1DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS                 23 
#define MXC_F_FCR_FCTRL0_I2C1DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS                 24 
#define MXC_F_FCR_FCTRL0_I2C2DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS                 25 
#define MXC_F_FCR_FCTRL0_I2C2DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) 
#define MXC_F_FCR_AUTOCAL0_ACEN_POS                    0 
#define MXC_F_FCR_AUTOCAL0_ACEN                        ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) 
#define MXC_F_FCR_AUTOCAL0_ACRUN_POS                   1 
#define MXC_F_FCR_AUTOCAL0_ACRUN                       ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) 
#define MXC_F_FCR_AUTOCAL0_LDTRM_POS                   2 
#define MXC_F_FCR_AUTOCAL0_LDTRM                       ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) 
#define MXC_F_FCR_AUTOCAL0_GAININV_POS                 3 
#define MXC_F_FCR_AUTOCAL0_GAININV                     ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) 
#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS                  4 
#define MXC_F_FCR_AUTOCAL0_ATOMIC                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) 
#define MXC_F_FCR_AUTOCAL0_MU_POS                      8 
#define MXC_F_FCR_AUTOCAL0_MU                          ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) 
#define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS         23 
#define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT             ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) 
#define MXC_F_FCR_AUTOCAL1_INITTRM_POS                 0 
#define MXC_F_FCR_AUTOCAL1_INITTRM                     ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) 
#define MXC_F_FCR_AUTOCAL2_DONECNT_POS                 0 
#define MXC_F_FCR_AUTOCAL2_DONECNT                     ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) 
#define MXC_F_FCR_AUTOCAL2_ACDIV_POS                   8 
#define MXC_F_FCR_AUTOCAL2_ACDIV                       ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) 
#define MXC_F_FCR_URVCTRL_MEMSEL_POS                   0 
#define MXC_F_FCR_URVCTRL_MEMSEL                       ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) 
#define MXC_F_FCR_URVCTRL_IFLUSHEN_POS                 1 
#define MXC_F_FCR_URVCTRL_IFLUSHEN                     ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) 
#define MXC_F_FCR_XO32MKS_CLK_POS                      0 
#define MXC_F_FCR_XO32MKS_CLK                          ((uint32_t)(0x7FUL << MXC_F_FCR_XO32MKS_CLK_POS)) 
#define MXC_F_FCR_XO32MKS_EN_POS                       7 
#define MXC_F_FCR_XO32MKS_EN                           ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_EN_POS)) 
#define MXC_F_FCR_XO32MKS_DRIVER_POS                   8 
#define MXC_F_FCR_XO32MKS_DRIVER                       ((uint32_t)(0x7UL << MXC_F_FCR_XO32MKS_DRIVER_POS)) 
#define MXC_F_FCR_XO32MKS_PULSE_POS                    11 
#define MXC_F_FCR_XO32MKS_PULSE                        ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_PULSE_POS)) 
#define MXC_F_FCR_XO32MKS_CLKSEL_POS                   12 
#define MXC_F_FCR_XO32MKS_CLKSEL                       ((uint32_t)(0x3UL << MXC_F_FCR_XO32MKS_CLKSEL_POS)) 
#define MXC_V_FCR_XO32MKS_CLKSEL_NONE                  ((uint32_t)0x0UL) 
#define MXC_S_FCR_XO32MKS_CLKSEL_NONE                  (MXC_V_FCR_XO32MKS_CLKSEL_NONE << MXC_F_FCR_XO32MKS_CLKSEL_POS) 
#define MXC_V_FCR_XO32MKS_CLKSEL_TEST                  ((uint32_t)0x1UL) 
#define MXC_S_FCR_XO32MKS_CLKSEL_TEST                  (MXC_V_FCR_XO32MKS_CLKSEL_TEST << MXC_F_FCR_XO32MKS_CLKSEL_POS) 
#define MXC_V_FCR_XO32MKS_CLKSEL_ISO                   ((uint32_t)0x2UL) 
#define MXC_S_FCR_XO32MKS_CLKSEL_ISO                   (MXC_V_FCR_XO32MKS_CLKSEL_ISO << MXC_F_FCR_XO32MKS_CLKSEL_POS) 
#define MXC_V_FCR_XO32MKS_CLKSEL_IPO                   ((uint32_t)0x3UL) 
#define MXC_S_FCR_XO32MKS_CLKSEL_IPO                   (MXC_V_FCR_XO32MKS_CLKSEL_IPO << MXC_F_FCR_XO32MKS_CLKSEL_POS) 
#define MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN_POS          0 
#define MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN              ((uint32_t)(0xFFUL << MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN_POS)) 
#define MXC_F_FCR_SARBUFCN_THRU_EN_POS                 8 
#define MXC_F_FCR_SARBUFCN_THRU_EN                     ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_THRU_EN_POS)) 
#define MXC_F_FCR_SARBUFCN_RAMP_EN_POS                 9 
#define MXC_F_FCR_SARBUFCN_RAMP_EN                     ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_RAMP_EN_POS)) 
#define MXC_F_FCR_SARBUFCN_THRU_RRI_EN_POS             10 
#define MXC_F_FCR_SARBUFCN_THRU_RRI_EN                 ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_THRU_RRI_EN_POS)) 
#define MXC_F_FCR_SARBUFCN_DIVSEL_POS                  11 
#define MXC_F_FCR_SARBUFCN_DIVSEL                      ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_DIVSEL_POS)) 
#define MXC_F_FCR_TS0_GAIN_POS                         0 
#define MXC_F_FCR_TS0_GAIN                             ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) 
#define MXC_F_FCR_TS1_OFFSET_POS                       0 
#define MXC_F_FCR_TS1_OFFSET                           ((uint32_t)(0x3FFFUL << MXC_F_FCR_TS1_OFFSET_POS)) 
#define MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS               14 
#define MXC_F_FCR_TS1_TS_OFFSET_SIGN                   ((uint32_t)(0x3FFFFUL << MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VREFP_POS                0 
#define MXC_F_FCR_ADCREFTRIM0_VREFP                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VREFM_POS                8 
#define MXC_F_FCR_ADCREFTRIM0_VREFM                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM0_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VREFP_POS                0 
#define MXC_F_FCR_ADCREFTRIM1_VREFP                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VREFM_POS                8 
#define MXC_F_FCR_ADCREFTRIM1_VREFM                    ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM1_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS            0 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25                ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS          4 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25              ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS           8 
#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048               ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS         12 
#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048             ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_VCM_POS                  16 
#define MXC_F_FCR_ADCREFTRIM2_VCM                      ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) 
#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS             24 
#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE                 ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_