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#define | MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) |
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#define | MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) |
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#define | MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) |
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#define | MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) |
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#define | MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) |
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#define | MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) |
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#define | MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) |
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#define | MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) |
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#define | MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) |
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#define | MXC_R_SPI_STAT ((uint32_t)0x00000030UL) |
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#define | MXC_F_SPI_FIFO32_DATA_POS 0 |
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#define | MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) |
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#define | MXC_F_SPI_FIFO16_DATA_POS 0 |
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#define | MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) |
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#define | MXC_F_SPI_FIFO8_DATA_POS 0 |
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#define | MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) |
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#define | MXC_F_SPI_CTRL0_EN_POS 0 |
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#define | MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) |
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#define | MXC_F_SPI_CTRL0_MST_MODE_POS 1 |
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#define | MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) |
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#define | MXC_F_SPI_CTRL0_SS_IO_POS 4 |
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#define | MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) |
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#define | MXC_F_SPI_CTRL0_START_POS 5 |
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#define | MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) |
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#define | MXC_F_SPI_CTRL0_SS_CTRL_POS 8 |
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#define | MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) |
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#define | MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 |
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#define | MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) |
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#define | MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) |
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#define | MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) |
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#define | MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) |
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#define | MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) |
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#define | MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) |
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#define | MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) |
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#define | MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) |
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#define | MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) |
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#define | MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 |
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#define | MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) |
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#define | MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 |
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#define | MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) |
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#define | MXC_F_SPI_CTRL2_CLKPHA_POS 0 |
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#define | MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) |
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#define | MXC_F_SPI_CTRL2_CLKPOL_POS 1 |
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#define | MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) |
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#define | MXC_F_SPI_CTRL2_SCLK_FB_INV_POS 4 |
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#define | MXC_F_SPI_CTRL2_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SCLK_FB_INV_POS)) |
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#define | MXC_F_SPI_CTRL2_NUMBITS_POS 8 |
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#define | MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_16 ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_16 (MXC_V_SPI_CTRL2_NUMBITS_16 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_1 ((uint32_t)0x1UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_1 (MXC_V_SPI_CTRL2_NUMBITS_1 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_2 ((uint32_t)0x2UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_2 (MXC_V_SPI_CTRL2_NUMBITS_2 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_3 ((uint32_t)0x3UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_3 (MXC_V_SPI_CTRL2_NUMBITS_3 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_4 ((uint32_t)0x4UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_4 (MXC_V_SPI_CTRL2_NUMBITS_4 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_5 ((uint32_t)0x5UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_5 (MXC_V_SPI_CTRL2_NUMBITS_5 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_6 ((uint32_t)0x6UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_6 (MXC_V_SPI_CTRL2_NUMBITS_6 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_7 ((uint32_t)0x7UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_7 (MXC_V_SPI_CTRL2_NUMBITS_7 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_8 ((uint32_t)0x8UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_8 (MXC_V_SPI_CTRL2_NUMBITS_8 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_9 ((uint32_t)0x9UL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_9 (MXC_V_SPI_CTRL2_NUMBITS_9 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_10 ((uint32_t)0xAUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_10 (MXC_V_SPI_CTRL2_NUMBITS_10 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_11 ((uint32_t)0xBUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_11 (MXC_V_SPI_CTRL2_NUMBITS_11 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_12 ((uint32_t)0xCUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_12 (MXC_V_SPI_CTRL2_NUMBITS_12 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_13 ((uint32_t)0xDUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_13 (MXC_V_SPI_CTRL2_NUMBITS_13 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_14 ((uint32_t)0xEUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_14 (MXC_V_SPI_CTRL2_NUMBITS_14 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_V_SPI_CTRL2_NUMBITS_15 ((uint32_t)0xFUL) |
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#define | MXC_S_SPI_CTRL2_NUMBITS_15 (MXC_V_SPI_CTRL2_NUMBITS_15 << MXC_F_SPI_CTRL2_NUMBITS_POS) |
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#define | MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 |
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#define | MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) |
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#define | MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) |
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#define | MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) |
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#define | MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) |
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#define | MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) |
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#define | MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) |
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#define | MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 |
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#define | MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) |
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#define | MXC_F_SPI_CTRL2_SS_POL_POS 16 |
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#define | MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) |
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#define | MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) |
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#define | MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) |
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#define | MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) |
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#define | MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) |
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#define | MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) |
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#define | MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) |
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#define | MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) |
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#define | MXC_F_SPI_SSTIME_PRE_POS 0 |
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#define | MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) |
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#define | MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) |
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#define | MXC_F_SPI_SSTIME_POST_POS 8 |
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#define | MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) |
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#define | MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) |
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#define | MXC_F_SPI_SSTIME_INACT_POS 16 |
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#define | MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) |
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#define | MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) |
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#define | MXC_F_SPI_CLKCTRL_LO_POS 0 |
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#define | MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) |
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#define | MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) |
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#define | MXC_F_SPI_CLKCTRL_HI_POS 8 |
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#define | MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) |
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#define | MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) |
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#define | MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 |
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#define | MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) |
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#define | MXC_F_SPI_CLKCTRL_AFP_FCD_POS 24 |
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#define | MXC_F_SPI_CLKCTRL_AFP_FCD ((uint32_t)(0x7UL << MXC_F_SPI_CLKCTRL_AFP_FCD_POS)) |
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#define | MXC_F_SPI_DMA_TX_THD_VAL_POS 0 |
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#define | MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) |
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#define | MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 |
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#define | MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) |
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#define | MXC_F_SPI_DMA_TX_FLUSH_POS 7 |
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#define | MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) |
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#define | MXC_F_SPI_DMA_TX_LVL_POS 8 |
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#define | MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) |
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#define | MXC_F_SPI_DMA_DMA_TX_EN_POS 15 |
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#define | MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) |
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#define | MXC_F_SPI_DMA_RX_THD_VAL_POS 16 |
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#define | MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) |
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#define | MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 |
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#define | MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) |
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#define | MXC_F_SPI_DMA_RX_FLUSH_POS 23 |
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#define | MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) |
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#define | MXC_F_SPI_DMA_RX_LVL_POS 24 |
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#define | MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) |
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#define | MXC_F_SPI_DMA_DMA_RX_EN_POS 31 |
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#define | MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) |
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#define | MXC_F_SPI_INTFL_TX_THD_POS 0 |
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#define | MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) |
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#define | MXC_F_SPI_INTFL_TX_EM_POS 1 |
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#define | MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) |
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#define | MXC_F_SPI_INTFL_RX_THD_POS 2 |
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#define | MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) |
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#define | MXC_F_SPI_INTFL_RX_FULL_POS 3 |
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#define | MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) |
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#define | MXC_F_SPI_INTFL_SSA_POS 4 |
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#define | MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) |
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#define | MXC_F_SPI_INTFL_SSD_POS 5 |
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#define | MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) |
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#define | MXC_F_SPI_INTFL_FAULT_POS 8 |
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#define | MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) |
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#define | MXC_F_SPI_INTFL_ABORT_POS 9 |
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#define | MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) |
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#define | MXC_F_SPI_INTFL_MST_DONE_POS 11 |
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#define | MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) |
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#define | MXC_F_SPI_INTFL_TX_OV_POS 12 |
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#define | MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) |
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#define | MXC_F_SPI_INTFL_TX_UN_POS 13 |
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#define | MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) |
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#define | MXC_F_SPI_INTFL_RX_OV_POS 14 |
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#define | MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) |
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#define | MXC_F_SPI_INTFL_RX_UN_POS 15 |
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#define | MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) |
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#define | MXC_F_SPI_INTEN_TX_THD_POS 0 |
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#define | MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) |
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#define | MXC_F_SPI_INTEN_TX_EM_POS 1 |
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#define | MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) |
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#define | MXC_F_SPI_INTEN_RX_THD_POS 2 |
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#define | MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) |
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#define | MXC_F_SPI_INTEN_RX_FULL_POS 3 |
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#define | MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) |
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#define | MXC_F_SPI_INTEN_SSA_POS 4 |
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#define | MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) |
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#define | MXC_F_SPI_INTEN_SSD_POS 5 |
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#define | MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) |
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#define | MXC_F_SPI_INTEN_FAULT_POS 8 |
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#define | MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) |
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#define | MXC_F_SPI_INTEN_ABORT_POS 9 |
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#define | MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) |
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#define | MXC_F_SPI_INTEN_MST_DONE_POS 11 |
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#define | MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) |
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#define | MXC_F_SPI_INTEN_TX_OV_POS 12 |
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#define | MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) |
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#define | MXC_F_SPI_INTEN_TX_UN_POS 13 |
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#define | MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) |
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#define | MXC_F_SPI_INTEN_RX_OV_POS 14 |
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#define | MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) |
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#define | MXC_F_SPI_INTEN_RX_UN_POS 15 |
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#define | MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) |
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#define | MXC_F_SPI_WKFL_TX_THD_POS 0 |
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#define | MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) |
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#define | MXC_F_SPI_WKFL_TX_EM_POS 1 |
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#define | MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) |
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#define | MXC_F_SPI_WKFL_RX_THD_POS 2 |
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#define | MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) |
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#define | MXC_F_SPI_WKFL_RX_FULL_POS 3 |
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#define | MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) |
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#define | MXC_F_SPI_WKEN_TX_THD_POS 0 |
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#define | MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) |
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#define | MXC_F_SPI_WKEN_TX_EM_POS 1 |
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#define | MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) |
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#define | MXC_F_SPI_WKEN_RX_THD_POS 2 |
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#define | MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) |
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#define | MXC_F_SPI_WKEN_RX_FULL_POS 3 |
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#define | MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) |
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#define | MXC_F_SPI_STAT_BUSY_POS 0 |
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#define | MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) |
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