MAX78002 Peripheral Driver API
Peripheral Driver API for the MAX78002
flc_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t addr;
78 __IO uint32_t clkdiv;
79 __IO uint32_t ctrl;
80 __R uint32_t rsv_0xc_0x23[6];
81 __IO uint32_t intr;
82 __R uint32_t rsv_0x28_0x2f[2];
83 __IO uint32_t data[4];
84 __O uint32_t actrl;
85 __R uint32_t rsv_0x44_0x7f[15];
86 __IO uint32_t welr0;
87 __IO uint32_t rlr0;
88 __IO uint32_t welr1;
89 __IO uint32_t rlr1;
90 __IO uint32_t welr2;
91 __IO uint32_t rlr2;
92 __IO uint32_t welr3;
93 __IO uint32_t rlr3;
94 __IO uint32_t welr4;
95 __IO uint32_t rlr4;
96} mxc_flc_regs_t;
97
98/* Register offsets for module FLC */
105#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL)
106#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL)
107#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL)
108#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL)
109#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL)
110#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL)
111#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL)
112#define MXC_R_FLC_RLR0 ((uint32_t)0x00000084UL)
113#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL)
114#define MXC_R_FLC_RLR1 ((uint32_t)0x0000008CUL)
115#define MXC_R_FLC_WELR2 ((uint32_t)0x00000090UL)
116#define MXC_R_FLC_RLR2 ((uint32_t)0x00000094UL)
117#define MXC_R_FLC_WELR3 ((uint32_t)0x00000098UL)
118#define MXC_R_FLC_RLR3 ((uint32_t)0x0000009CUL)
119#define MXC_R_FLC_WELR4 ((uint32_t)0x000000A0UL)
120#define MXC_R_FLC_RLR4 ((uint32_t)0x000000A4UL)
129#define MXC_F_FLC_ADDR_ADDR_POS 0
130#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS))
141#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0
142#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS))
152#define MXC_F_FLC_CTRL_WR_POS 0
153#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS))
155#define MXC_F_FLC_CTRL_ME_POS 1
156#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS))
158#define MXC_F_FLC_CTRL_PGE_POS 2
159#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS))
161#define MXC_F_FLC_CTRL_WDTH_POS 4
162#define MXC_F_FLC_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WDTH_POS))
164#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
165#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
166#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL)
167#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS)
168#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL)
169#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS)
170#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL)
171#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS)
173#define MXC_F_FLC_CTRL_PEND_POS 24
174#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS))
176#define MXC_F_FLC_CTRL_LVE_POS 25
177#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS))
179#define MXC_F_FLC_CTRL_UNLOCK_POS 28
180#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS))
181#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL)
182#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS)
183#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL)
184#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS)
194#define MXC_F_FLC_INTR_DONE_POS 0
195#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS))
197#define MXC_F_FLC_INTR_AF_POS 1
198#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS))
200#define MXC_F_FLC_INTR_DONEIE_POS 8
201#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS))
203#define MXC_F_FLC_INTR_AFIE_POS 9
204#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS))
214#define MXC_F_FLC_DATA_DATA_POS 0
215#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS))
229#define MXC_F_FLC_ACTRL_ACTRL_POS 0
230#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS))
240#define MXC_F_FLC_WELR0_WELR0_POS 0
241#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS))
251#define MXC_F_FLC_RLR0_RLR0_POS 0
252#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS))
262#define MXC_F_FLC_WELR1_WELR1_POS 0
263#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS))
273#define MXC_F_FLC_RLR1_RLR1_POS 0
274#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS))
284#define MXC_F_FLC_WELR2_WELR2_POS 0
285#define MXC_F_FLC_WELR2_WELR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR2_WELR2_POS))
295#define MXC_F_FLC_RLR2_RLR2_POS 0
296#define MXC_F_FLC_RLR2_RLR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR2_RLR2_POS))
306#define MXC_F_FLC_WELR3_WELR3_POS 0
307#define MXC_F_FLC_WELR3_WELR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR3_WELR3_POS))
317#define MXC_F_FLC_RLR3_RLR3_POS 0
318#define MXC_F_FLC_RLR3_RLR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR3_RLR3_POS))
328#define MXC_F_FLC_WELR4_WELR4_POS 0
329#define MXC_F_FLC_WELR4_WELR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR4_WELR4_POS))
339#define MXC_F_FLC_RLR4_RLR4_POS 0
340#define MXC_F_FLC_RLR4_RLR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR4_RLR4_POS))
344#ifdef __cplusplus
345}
346#endif
347
348#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_FLC_REGS_H_
mxc_flc_regs_t::actrl
__O uint32_t actrl
Definition: flc_regs.h:84
mxc_flc_regs_t::clkdiv
__IO uint32_t clkdiv
Definition: flc_regs.h:78
mxc_flc_regs_t::rlr3
__IO uint32_t rlr3
Definition: flc_regs.h:93
mxc_flc_regs_t::ctrl
__IO uint32_t ctrl
Definition: flc_regs.h:79
mxc_flc_regs_t::welr0
__IO uint32_t welr0
Definition: flc_regs.h:86
mxc_flc_regs_t::welr1
__IO uint32_t welr1
Definition: flc_regs.h:88
mxc_flc_regs_t::welr3
__IO uint32_t welr3
Definition: flc_regs.h:92
mxc_flc_regs_t::rlr1
__IO uint32_t rlr1
Definition: flc_regs.h:89
mxc_flc_regs_t::welr2
__IO uint32_t welr2
Definition: flc_regs.h:90
mxc_flc_regs_t::addr
__IO uint32_t addr
Definition: flc_regs.h:77
mxc_flc_regs_t::welr4
__IO uint32_t welr4
Definition: flc_regs.h:94
mxc_flc_regs_t::rlr4
__IO uint32_t rlr4
Definition: flc_regs.h:95
mxc_flc_regs_t::rlr0
__IO uint32_t rlr0
Definition: flc_regs.h:87
mxc_flc_regs_t::intr
__IO uint32_t intr
Definition: flc_regs.h:81
mxc_flc_regs_t::rlr2
__IO uint32_t rlr2
Definition: flc_regs.h:91
mxc_flc_regs_t
Definition: flc_regs.h:76