Quick Start
Installation
Install from the Git repository:
pip install git+https://github.com/analogdevicesinc/pyadi-dt.git
For XSA pipeline support (requires Vivado sdtgen / lopper on PATH):
pip install "git+https://github.com/analogdevicesinc/pyadi-dt.git#egg=adidt[xsa]"
For development with all test dependencies:
pip install -e ".[dev]"
Generate a device tree from an XSA file
The fastest way to produce a device tree from a Vivado design:
adidtc xsa2dt -x design.xsa --profile ad9081_zcu102 -o out/
This runs the full pipeline — sdtgen, topology parsing, node building
via BoardModel, and DTS merging — and writes a .dts file ready for
dtc compilation.
Use --lint to run the structural linter before writing output:
adidtc xsa2dt -x design.xsa --profile adrv9009_zcu102 --lint -o out/
Browse available profiles before running the pipeline:
adidtc xsa-profiles # list all profiles
adidtc xsa-profile-show ad9081_zcu102 # show profile details as JSON
Generate a device tree overlay from Python
The simplest case — an ADI SPI device on a Raspberry Pi or similar platform. No Vivado, no XSA, no FPGA:
from adidt.model import BoardModel, components
from adidt.model.renderer import BoardModelRenderer
model = BoardModel(
name="rpi5_imu",
platform="rpi5",
components=[
components.adis16495(spi_bus="spi0", cs=0, interrupt_gpio=25),
],
)
nodes = BoardModelRenderer().render(model)
with open("adis16495-rpi5.dts", "w") as f:
f.write("/dts-v1/;\n/plugin/;\n\n")
for node_list in nodes.values():
for node in node_list:
f.write(node + "\n")
See Device Tree Generation for the full walkthrough including compilation and deployment.
Generate a device tree for an FPGA board
For FPGA boards with clock chips and JESD204 links, use pyadi-jif
to solve the clock tree and a board class to generate the DTS:
import adijif
from adidt.boards.daq2 import daq2
# Solve clock tree
sys = adijif.system(["ad9680", "ad9144"], "ad9523_1", "xilinx", 125e6)
sys.fpga.setup_by_dev_kit_name("zcu102")
sys.converter[0].sample_clock = 500e6
sys.converter[1].sample_clock = 500e6
conf = sys.solve()
# Generate DTS via BoardModel
board = daq2(platform="zcu102")
board.output_filename = "fmcdaq2_zcu102.dts"
board.gen_dt_from_config(conf, config_source="adijif_500msps")
Generate a device tree from the CLI
The gen-dts command runs the same board class workflow without writing
a Python script:
adidtc gen-dts -b daq2 -p zcu102 -c solver_config.json
# Generate and compile to DTB
adidtc gen-dts -b ad9081_fmc -p vpk180 -c config.json --compile
See Device Tree Generation for the full walkthrough and
Command Line Interface for all gen-dts options.
Edit a BoardModel before rendering
The BoardModel is editable after construction. Modify any component
config, JESD parameter, or metadata before rendering:
from adidt.boards.daq2 import daq2
from adidt.model.renderer import BoardModelRenderer
board = daq2(platform="zcu102")
model = board.to_board_model(solver_config)
# Change clock VCXO frequency
clock = model.get_component("clock")
clock.config["vcxo_hz"] = 100_000_000
# Change JESD lane count
rx_link = model.get_jesd_link("rx")
rx_link.link_params["L"] = 8
# Render to DTS node strings
nodes = BoardModelRenderer().render(model)
See BoardModel: Unified Device Tree Generation for more patterns.
Inspect a device tree on live hardware
Read device tree properties from a running board over SSH:
adidtc -c remote_sysfs -i 192.168.2.1 prop -cp adi,ad9361 clock-output-names
See Live Update Access Models for local sysfs, remote SSH, SD card, and file-based access modes.
Analyze device tree dependencies
Visualize include dependencies and missing headers in a device tree file:
adidtc deps overlay.dts --format tree
adidtc deps overlay.dts --format dot -o deps.dot # Graphviz output
Configure clocks from JSON
Apply pyadi-jif-solved clock and JESD204 parameters from a JSON file:
adidtc jif --config solved_clocks.json
See Part Layers for the part-layer abstractions (HMC7044, AD9523-1, AD9528, ADRV9009).
Next steps
XSA Flow Tutorials — Step-by-step XSA-to-DTS walkthrough
Device Tree Generation — Generate device trees without Vivado (Raspberry Pi, Intel FPGA, custom boards)
XSA + adijif Tutorial — Derive JESD parameters with
pyadi-jifbefore running the XSA pipelineMCP Server — Use pyadi-dt tools from Claude or Cursor via MCP
Board Model Module — BoardModel API reference
XSA Pipeline — Developer Guide — Pipeline architecture and adding new boards