Reference

AD9081 high speed MxFE clocking model.

ad9081 (ad9081_core)

AD9081 combined transmit and receive model.

__init__(self, model=None, solver=None) special

Initialize AD9081 clocking model for TX and RX.

This is a common class used to handle TX and RX constraints together.

Parameters:

Name	Type	Description	Default
model	GEKKO,CpoModel	Solver model	None
solver	str	Solver name (gekko or CPLEX)	None

get_required_clock_names(self)

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names in order

get_required_clocks(self)

Generate list required clocks.

For AD9081 this will contain [converter clock, sysref requirement SOS]

Returns:

Type	Description
List	List of solver variables, equations, and constants

Exceptions:

Type	Description
Exception	If direct clocking is used. Not yet implemented

validate_config(self)

Validate device configurations including JESD and clocks of both ADC and DAC.

This check only is for static configuration that does not include variables which are solved.

ad9081_core (converter)

AD9081 high speed MxFE model.

This model supports both direct clock configurations and on-board generation

Clocking: AD9081 can internally generate or leverage external clocks. The high speed clock within the system is referred to as the DAC clock and the ADC clock will be a divided down version of the clock: adc_clock == dac_clock / L, where L = 1,2,3,4

For internal generation, the DAC clock is generated through an integer PLL through the following relation: dac_clock == ((m_vco * n_vco) / R * ref_clock) / D

For external clocks, the clock must be provided at the DAC clock rate

Once we have the DAC clock the data rates can be directly evaluated into each JESD framer:

rx_baseband_sample_rate = (dac_clock / L) / datapath_decimation tx_baseband_sample_rate = dac_clock / datapath_interpolation

get_config(self, solution=None)

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Type	Description
Dict	Dictionary of clocking rates and dividers for configuration

get_required_clock_names(self)

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names in order

get_required_clocks(self)

Generate list required clocks.

For AD9081 this will contain [converter clock, sysref requirement SOS]

Returns:

Type	Description
List	List of solver variables, equations, and constants

ad9081_rx (adc, ad9081_core)

AD9081 Receive model.

decimation: int property writable

Decimation factor. This is the product of the coarse and fine decimation.

__init__(self, model=None, solver=None) special

Initialize AD9081 clocking model for RX.

This is a common class used to handle RX constraints together.

Parameters:

Name	Type	Description	Default
model	GEKKO,CpoModel	Solver model	None
solver	str	Solver name (gekko or CPLEX)	None

ad9081_tx (dac, ad9081_core)

AD9081 Transmit model.

interpolation: int property writable

Interpolation factor.

This is the product of the coarse and fine interpolation.

Returns:

Type	Description
int	Interpolation factor

__init__(self, model=None, solver=None) special

Initialize AD9081 clocking model for TX.

This is a common class used to handle TX constraints together.

Parameters:

Name	Type	Description	Default
model	GEKKO,CpoModel	Solver model	None
solver	str	Solver name (gekko or CPLEX)	None

ad9082 (ad9081)

AD9081 combined transmit and receive model.

get_required_clock_names(self)

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names in order

ad9082_rx (ad9081_rx)

AD9082 MxFE RX Clocking Model.

ad9082_tx (ad9081_tx)

AD9082 MxFE TX Clocking Model.

AD9680 high speed ADC clocking model.

ad9680 (ad9680_bf)

AD9680 high speed ADC model.

This model supports direct clock configurations

Clocking: AD9680 has directly clocked ADC that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

input_clock_max

Clocking AD9680 has directly clocked ADCs that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

__init__(self, *args: Any, **kwargs: Any) -> None special

Initialize AD9680 class.

Objects will default to mode 0x88 with 1e9 sample_clock.

Parameters:

Name	Type	Description	Default
*args	Any	Pass through arguments	()
**kwargs	Any	Pass through keyword arguments	{}

get_config(self, solution: CpoSolveResult = None) -> Dict

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Type	Description
Dict	Dictionary of clocking rates and dividers for configuration

get_required_clock_names(self) -> List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names in order

get_required_clocks(self) -> List

Generate list required clocks.

For AD9680 this will contain [converter clock, sysref requirement SOS]

Returns:

Type	Description
List	List of solver variables, equations, and constants

AD9144 high speed DAC clocking model.

ad9144 (ad9144_bf)

AD9144 high speed DAC model.

This model supports both direct clock configurations and on-board generation

Clocking: AD9144 has directly clocked DAC that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

get_config(self, solution=None)

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Type	Description
Dict	Dictionary of clocking rates and dividers for configuration

get_required_clock_names(self)

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names in order

get_required_clocks(self)

Generate list required clocks.

For AD9144 this will contain [converter clock, sysref requirement SOS]

Returns:

Type	Description
List	List of dictionaries of solver components

ADRV9009 transceiver clocking model.

adrv9009 (core, adrv9009_core, gekko_translation)

ADRV9009 combined transmit and receive model.

__init__(self, model=None, solver=None) special

Initialize ADRV9009 clocking model for TX and RX.

This is a common class used to handle TX and RX constraints together.

Parameters:

Name	Type	Description	Default
model	GEKKO,CpoModel	Solver model	None
solver	str	Solver name (gekko or CPLEX)	None

get_required_clocks(self)

Generate list of required clocks.

For ADRV9009 this will contain: [device clock requirement SOS, sysref requirement SOS]

Returns:

Type	Description
list[dict]	List of dictionaries of solver variables, equations, and constants

Exceptions:

Type	Description
Exception	Invalid relation of rates between RX and TX
AssertionError	Gekko called

adrv9009_clock_common (adrv9009_core, adrv9009_bf)

ADRV9009 class managing common singleton (Rx,Tx) methods.

get_config(self, solution=None)

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Type	Description
Dict	Dictionary of clocking rates and dividers for configuration

get_required_clock_names(self)

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

Type	Description
List[str]	List of strings of clock names mapped by get_required_clocks

get_required_clocks(self)

Generate list of required clocks.

For ADRV9009 this will contain: [device clock requirement SOS, sysref requirement SOS]

Returns:

Type	Description
list[dict]	List of dictionaries of solver variables, equations, and constants

adrv9009_core

ADRV9009 transceiver clocking model.

This model manage the JESD configuration and input clock constraints. External LO constraints are not modeled.

Clocking: ADRV9009 uses onboard PLLs to generate the JESD clocks

Lane Rate = I/Q Sample Rate * M * Np * (10 / 8) / L
Lane Rate = sample_clock * M * Np * (10 / 8) / L

adrv9009_rx (adc, adrv9009_clock_common, adrv9009_core)

ADRV9009 Receive model.

adrv9009_tx (dac, adrv9009_clock_common, adrv9009_core)

ADRV9009 Transmit model.