FPGA Reference APIs
Xilinx FPGA clocking model.
xilinx (xilinx_bf)
Xilinx FPGA clocking model.
This model captures different limitations of the Xilinx PLLs and interfaces used for JESD.
Currently only Zynq 7000 devices have been fully tested.
N: List[int]
property
readonly
Get available feedback divider settings.
This is applicable for QPLLs only.
Returns:
| Type | Description |
|---|---|
list[int] |
List of divider integers. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
force_cpll
Force all transceiver sources to be from a single PLL quad. This will try to leverage the output dividers of the PLLs
force_qpll
Force use of QPLL1 for transceiver source (GTH3,GTH4,GTY4)
force_qpll1
Force use of CPLL for transceiver source
force_single_quad_tile
Request that clock chip generated device clock device clock == LMFC/40 NOTE: THIS IS NOT FPGA REF CLOCK
minimize_fpga_ref_clock
Force generation of separate device clock from the clock chip. In many cases, the ref clock and device clock can be the same.
out_clk_select: Union[int, float]
property
writable
Get current PLL clock output mux options for link layer clock.
Valid options are: "XCVR_REFCLK", "XCVR_REFCLK_DIV2", "XCVR_PROGDIV_CLK" If a list of these is provided, the solver will determine one to use
Returns:
| Type | Description |
|---|---|
str,list(str) |
Mux selection for link layer clock. |
requires_separate_link_layer_out_clock: bool
Require generation of separate core clock (LR/40 or LR/66)
target_Fmax
Require generation of separate clock specifically for link layer
vco0_max: int
property
readonly
Get maximum QPLL VCO0 rate for config.
This is applicable for QPLLs only.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
vco0_min: int
property
readonly
Get minimum QPLL VCO0 rate for config.
This is applicable for QPLLs only.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
vco1_max: int
property
readonly
Get maximum QPLL VCO1 rate for config.
This is applicable for QPLLs only.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
vco1_min: int
property
readonly
Get minimum QPLL VCO1 rate for config.
This is applicable for QPLLs only.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
vco_max: int
property
readonly
Get maximum CPLL VCO rate for config.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
vco_min: int
property
readonly
Get minimum CPLL VCO rate for config.
Returns:
| Type | Description |
|---|---|
int |
Rate in samples per second. |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported transceiver type configured. |
determine_pll(self, bit_clock, fpga_ref_clock)
Determin if configuration is possible with CPLL or QPLL.
CPLL is checked first and will check QPLL if that case is invalid.
This is only used for brute-force implementations.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
bit_clock |
int |
Equivalent to lane rate in bits/second |
required |
fpga_ref_clock |
int |
System reference clock |
required |
Returns:
| Type | Description |
|---|---|
Dict |
Dictionary of PLL configuration |
get_config(self, converter, fpga_ref, solution=None)
Extract configurations from solver results.
Collect internal FPGA configuration and output clock definitions.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
converter |
conv |
Converter object connected to FPGA who config is collected |
required |
fpga_ref |
int or float |
Reference clock generated for FPGA for specific converter |
required |
solution |
CpoSolveResult |
CPlex solution. Only needed for CPlex solver |
None |
Exceptions:
| Type | Description |
|---|---|
Exception |
Invalid PLL configuration. |
Returns:
| Type | Description |
|---|---|
Dict |
Dictionary of clocking rates and dividers for configuration |
get_required_clock_names(self)
Get list of strings of names of requested clocks.
This list of names is for the clocks defined by get_required_clocks
Returns:
| Type | Description |
|---|---|
List[str] |
List of strings of clock names in order |
Exceptions:
| Type | Description |
|---|---|
Exception |
Clock have not been enumerated aka get_required_clocks not not called yet. |
get_required_clocks(self, converter, fpga_ref, link_out_ref=None)
Get necessary clocks for QPLL/CPLL configuration.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
converter |
conv |
Converter object of converter connected to FPGA |
required |
fpga_ref |
int, GKVariable, GK_Intermediate, GK_Operators, CpoIntVar |
Abstract or concrete reference to FPGA reference clock |
required |
link_out_ref |
int or GKVariable |
Reference clock generated for FPGA link layer output, also called device clock |
None |
Returns:
| Type | Description |
|---|---|
List |
List of solver variables and constraints |
Exceptions:
| Type | Description |
|---|---|
Exception |
If solver is not valid |
Exception |
Link layer out clock required |
setup_by_dev_kit_name(self, name)
Configure object based on board name. Ex: zc706, zcu102.
Parameters:
| Name | Type | Description | Default |
|---|---|---|---|
name |
str |
Name of dev kit. Ex: zc706, zcu102 |
required |
Exceptions:
| Type | Description |
|---|---|
Exception |
Unsupported board requested. |