JESD204 Component-Level Testbenches

Overview

The component-level testbenches verify individual JESD204 IP modules in isolation. They are located in the HDL repository at library/jesd204/tb.

These testbenches complement the system-level testbenches (like JESD loopback) by testing specific functionality at a granular level and supporting multiple simulators.

Supported Simulators

The simulator can be selected through the SIMULATOR environment variable:

$SIMULATOR	Simulator
modelsim	Mentor/Siemens ModelSim/QuestaSim
xsim	AMD Xilinx Vivado Simulator
xcelium	Cadence Xcelium
(default)	Icarus Verilog (iverilog)

Available Testbenches

Link Layer - Register Map

Testbench	Description
axi_jesd204_rx_regmap_tb	Verifies AXI register read/write interface for RX link layer peripheral
axi_jesd204_tx_regmap_tb	Verifies AXI register read/write interface for TX link layer peripheral

Link Layer - Core

Testbench	Description
rx_tb	Tests RX link layer core including PHY ready and lane alignment
rx_cgs_tb	Tests Code Group Synchronization (CGS) state machine
rx_ctrl_tb	Tests RX control logic
rx_lane_tb	Tests individual RX lane handling
tx_tb	Tests TX link layer with multi-link SYNC handling
tx_ctrl_phase_tb	Tests TX control phase alignment
tx_64b_tb	Tests TX 64b66b mode (JESD204C)

Loopback (Full TX to RX Stack)

Testbench	Description
loopback_tb	Full 8b10b JESD204B loopback test with data integrity verification

Scrambler/Descrambler

Testbench	Description
scrambler_tb	Tests 8b10b scrambler/descrambler loopback integrity
scrambler_64b_tb	Tests 64b66b scrambler/descrambler using reference vectors

Frame Handling

Testbench	Description
frame_align_tb	Tests frame alignment with configurable error injection
jesd204_frame_align_replace_tb	Tests character replacement at frame boundaries
jesd204_frame_mark_tb	Tests SOF/EOF frame marking logic

Soft PCS (8b10b Physical Coding Sublayer)

Testbench	Description
soft_pcs_8b10b_sequence_tb	Tests 8b10b encoder output sequences
soft_pcs_8b10b_table_tb	Verifies 8b10b encoding lookup table
soft_pcs_loopback_tb	Tests soft PCS encode/decode loopback
soft_pcs_pattern_align_tb	Tests comma pattern detection and alignment

Utility

Testbench	Description
crc12_tb	Tests CRC-12 calculation per JESD204C specification

Building and Running

Open a Cygwin or bash terminal
Navigate to the testbench folder:
```
cd library/jesd204/tb
```
(Optional) Set the simulator:
```
export SIMULATOR=xsim
```
Run a testbench:
```
./loopback_tb
```

Output files:

VCD waveforms: vcd/<testbench_name>.vcd
Simulation logs: <testbench_name>_<simulator>.log

Resources

HDL Dependencies

Module	Source	Documentation
jesd204_rx	library/jesd204/jesd204_rx	JESD204B/C Link Receive Peripheral
jesd204_tx	library/jesd204/jesd204_tx	JESD204B/C Link Transmit Peripheral
jesd204_scrambler	library/jesd204/jesd204_common	—
jesd204_lmfc	library/jesd204/jesd204_common	—