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Variables
parameters.c File Reference

Definition of xilinx platform data used by ad463x_fmcz project. More...

#include "parameters.h"
#include "clk_axi_clkgen.h"
Include dependency graph for parameters.c:

Variables

struct xil_uart_init_param uart_extra_ip
 
struct spi_engine_init_param spi_eng_init_param
 
struct spi_engine_offload_init_param spi_engine_offload_init_param
 
struct axi_clkgen_init clkgen_init
 
struct axi_pwm_init_param axi_pwm_init_param
 

Detailed Description

Definition of xilinx platform data used by ad463x_fmcz project.

Author
Antoniu Miclaus (anton.nosp@m.iu.m.nosp@m.iclau.nosp@m.s@an.nosp@m.alog..nosp@m.com)
Axel Haslam (ahasl.nosp@m.am@b.nosp@m.aylib.nosp@m.re.c.nosp@m.om)

Copyright 2024(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Variable Documentation

◆ axi_pwm_init_param

Initial value:
= {
.base_addr = AXI_PWMGEN_BASEADDR,
.ref_clock_Hz = 100000000,
.channel = 0
}

◆ clkgen_init

struct axi_clkgen_init clkgen_init
Initial value:
= {
.name = "rx_clkgen",
.parent_rate = 100000000,
}

◆ spi_eng_init_param

struct spi_engine_init_param spi_eng_init_param
Initial value:
= {
.ref_clk_hz = 100000000,
.type = SPI_ENGINE,
.spi_engine_baseaddr = SPI_ENGINE_BASEADDR,
.cs_delay = 0,
.data_width = 32,
}

◆ spi_engine_offload_init_param

Initial value:
= {
.offload_config = OFFLOAD_RX_EN,
.rx_dma_baseaddr = DMA_BASEADDR,
}

◆ uart_extra_ip

struct xil_uart_init_param uart_extra_ip
Initial value:
= {
.type = UART_PS,
.irq_id = UART_IRQ_ID
}
RX_CLKGEN_BASEADDR
#define RX_CLKGEN_BASEADDR
Definition: parameters.h:103
SPI_ENGINE_BASEADDR
#define SPI_ENGINE_BASEADDR
Definition: parameters.h:102
UART_PS
@ UART_PS
Definition: xilinx_uart.h:65
UART_IRQ_ID
#define UART_IRQ_ID
Definition: parameters.h:56
DMA_BASEADDR
#define DMA_BASEADDR
Definition: parameters.h:101
SPI_ENGINE
@ SPI_ENGINE
Definition: xilinx_spi.h:70
OFFLOAD_RX_EN
#define OFFLOAD_RX_EN
Definition: spi_engine.h:59
AXI_PWMGEN_BASEADDR
#define AXI_PWMGEN_BASEADDR
Definition: parameters.h:104