Header file of AD9528 Driver. More...

#include <stdint.h>
#include <stdbool.h>
#include "no_os_delay.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"

Include dependency graph for ad9528.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes
struct	ad9528_channel_spec
	Output channel configuration. More...

struct	ad9528_platform_data
	platform specific information More...

struct	ad9528_state

struct	ad9528_dev

struct	ad9528_init_param

Macros
#define	AD9528_READ (1 << 15)

#define	AD9528_WRITE (0 << 15)

#define	AD9528_CNT(x) (((x) - 1) << 13)

#define	AD9528_ADDR(x) ((x) & 0xFFF)

#define	AD9528_1B(x) ((1 << 16) \| ((x) + 0))

#define	AD9528_2B(x) ((2 << 16) \| ((x) + 1))

#define	AD9528_3B(x) ((3 << 16) \| ((x) + 2))

#define	AD9528_4B(x) ((4 << 16) \| ((x) + 3))

#define	AD9528_TRANSF_LEN(x) ((x) >> 16)

#define	AD9528_SERIAL_PORT_CONFIG AD9528_1B(0x0)

#define	AD9528_SERIAL_PORT_CONFIG_B AD9528_1B(0x1)

#define	AD9528_CHIP_ID AD9528_4B(0x3)

#define	AD9528_IO_UPDATE AD9528_1B(0xF)

#define	AD9528_PLL1_REF_A_DIVIDER AD9528_2B(0x100)

#define	AD9528_PLL1_REF_B_DIVIDER AD9528_2B(0x102)

#define	AD9528_PLL1_FEEDBACK_DIVIDER AD9528_2B(0x104)

#define	AD9528_PLL1_CHARGE_PUMP_CTRL AD9528_2B(0x106)

#define	AD9528_PLL1_CTRL AD9528_3B(0x108)

#define	AD9528_PLL2_CHARGE_PUMP AD9528_1B(0x200)

#define	AD9528_PLL2_FEEDBACK_DIVIDER_AB AD9528_1B(0x201)

#define	AD9528_PLL2_CTRL AD9528_1B(0x202)

#define	AD9528_PLL2_VCO_CTRL AD9528_1B(0x203)

#define	AD9528_PLL2_VCO_DIVIDER AD9528_1B(0x204)

#define	AD9528_PLL2_LOOP_FILTER_CTRL AD9528_2B(0x205)

#define	AD9528_PLL2_R1_DIVIDER AD9528_1B(0x207)

#define	AD9528_PLL2_N2_DIVIDER AD9528_1B(0x208)

#define	AD9528_CHANNEL_OUTPUT(ch) AD9528_3B(0x300 + 3 * ch)

#define	AD9528_CHANNEL_SYNC AD9528_1B(0x32A)

#define	AD9528_CHANNEL_SYNC_IGNORE AD9528_2B(0x32B)

#define	AD9528_SYSREF_RESAMPLE_CTRL AD9528_2B(0x32D)

#define	AD9528_SYSREF_K_DIVIDER AD9528_2B(0x400)

#define	AD9528_SYSREF_CTRL AD9528_2B(0x402)

#define	AD9528_PD_EN AD9528_1B(0x500)

#define	AD9528_CHANNEL_PD_EN AD9528_2B(0x501)

#define	AD9528_STAT_MON0 AD9528_1B(0x505)

#define	AD9528_STAT_MON1 AD9528_1B(0x506)

#define	AD9528_STAT_PIN_EN AD9528_1B(0x507)

#define	AD9528_READBACK AD9528_2B(0x508)

#define	AD9528_SER_CONF_SOFT_RESET ((1 << 0) \| (1 << 7))

#define	AD9528_SER_CONF_LSB_FIRST ((1 << 1) \| (1 << 6))

#define	AD9528_SER_CONF_ADDR_INCREMENT ((1 << 2) \| (1 << 5))

#define	AD9528_SER_CONF_SDO_ACTIVE ((1 << 3) \| (1 << 4))

#define	AD9528_SER_CONF_READ_BUFFERED (1 << 5)

#define	AD9528_SER_CONF_RESET_SANS_REGMAP (1 << 2)

#define	AD9528_IO_UPDATE_EN (1 << 0)

#define	AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS (1 << 12)

#define	AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)

#define	AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)

#define	AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)

#define	AD9528_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)

#define	AD9528_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)

#define	AD9528_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)

#define	AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 19)

#define	AD9528_PLL1_REF_MODE(x) ((x) << 16)

#define	AD9528_PLL1_FEEDBACK_BYPASS_EN (1 << 13)

#define	AD9528_PLL1_REFB_BYPASS_EN (1 << 12)

#define	AD9528_PLL1_REFA_BYPASS_EN (1 << 11)

#define	AD9528_PLL1_SOURCE_VCXO (1 << 10)

#define	AD9528_PLL1_REFB_CMOS_NEG_INP_EN (1 << 9)

#define	AD9528_PLL1_REFA_CMOS_NEG_INP_EN (1 << 8)

#define	AD9528_PLL1_FREQ_DETECTOR_PD_EN (1 << 7)

#define	AD9528_PLL1_REFB_DIFF_RCV_EN (1 << 6)

#define	AD9528_PLL1_REFA_DIFF_RCV_EN (1 << 5)

#define	AD9528_PLL1_REFB_RCV_EN (1 << 4)

#define	AD9528_PLL1_REFA_RCV_EN (1 << 3)

#define	AD9528_PLL1_VCXO_RCV_PD_EN (1 << 2)

#define	AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)

#define	AD9528_PLL1_OSC_IN_DIFF_EN (1 << 0)

#define	AD9528_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)

#define	AD9528_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)

#define	AD9528_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)

#define	AD9528_PLL2_FB_NDIV(a, b) (4 * (b) + (a))

#define	AD9528_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)

#define	AD9528_PLL2_FREQ_DOUBLER_EN (1 << 5)

#define	AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)

#define	AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)

#define	AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)

#define	AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)

#define	AD9528_PLL2_DOUBLER_R1_EN (1 << 4)

#define	AD9528_PLL2_FORCE_REFERENCE_VALID (1 << 2)

#define	AD9528_PLL2_FORCE_VCO_MIDSCALE (1 << 1)

#define	AD9528_PLL2_VCO_CALIBRATE (1 << 0)

#define	AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 3)

#define	AD9528_PLL2_VCO_DIV_M1(x) (((x) & 0x7) << 0)

#define	AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)

#define	AD9528_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x3) << 6)

#define	AD9528_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)

#define	AD9528_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)

#define	AD9528_PLL2_R1_DIV(x) (((x) & 0x1F) << 0)

#define	AD9528_PLL2_N2_DIV(x) ((((x) - 1) & 0xFF) << 0)

#define	AD9528_CLK_DIST_DIV_MIN 1

#define	AD9528_CLK_DIST_DIV_MAX 256

#define	AD9528_CLK_DIST_DIV(x) ((((x) - 1) & 0xFF) << 16)

#define	AD9528_CLK_DIST_DIV_MASK (0xFF << 16)

#define	AD9528_CLK_DIST_DIV_REV(x) ((((x) >> 16) & 0xFF) + 1)

#define	AD9528_CLK_DIST_DRIVER_MODE(x) (((x) & 0x3) << 14)

#define	AD9528_CLK_DIST_DRIVER_MODE_REV(x) (((x) >> 14) & 0x3)

#define	AD9528_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 8)

#define	AD9528_CLK_DIST_DIV_PHASE_REV(x) (((x) >> 8) & 0x3F)

#define	AD9528_CLK_DIST_CTRL(x) (((x) & 0x7) << 5)

#define	AD9528_CLK_DIST_CTRL_MASK (0x7 << 5)

#define	AD9528_CLK_DIST_CTRL_REV(x) (((x) >> 5) & 0x7)

#define	AD9528_CHANNEL_SYNC_SET (1 << 0)

#define	AD9528_CHANNEL_IGNORE_MASK(x) (((x) & 0x3FFF) << 0)

#define	AD9528_CHANNEL_IGNORE_MASK_REV(x) (((x) >> 0) & 0x3FFF)

#define	AD9528_SYSREF_K_DIV(x) (((x) & 0xFFFF) << 0)

#define	AD9528_SYSREF_K_DIV_MIN (1u)

#define	AD9528_SYSREF_K_DIV_MAX (65535u)

#define	AD9528_SYSREF_SOURCE(x) (((x) & 0x3) << 14)

#define	AD9528_SYSREF_PATTERN_MODE(x) (((x) & 0x3) << 12)

#define	AD9528_SYSREF_NSHOT_MODE(x) (((x) & 0x7) << 9)

#define	AD9528_SYSREF_PATTERN_REQ (1 << 8)

#define	AD9528_SYSREF_REQUEST_BY_PIN (1 << 7)

#define	AD9528_SYSREF_PATTERN_TRIGGER_CTRL(x) (((x) & 0x3) << 5)

#define	AD9528_SYSREF_RESAMPLER_CLK_SRC_PLL1 (1 << 4)

#define	AD9528_SYSREF_PATTERN_CLK_SRC_PLL1 (1 << 3)

#define	AD9528_SYSREF_TEST_MODE(x) (((x) & 0x3) << 1)

#define	AD9528_SYSREF_RESET (1 << 0)

#define	AD9528_PD_BIAS NO_OS_BIT(4)

#define	AD9528_PD_PLL2 NO_OS_BIT(3)

#define	AD9528_PD_PLL1 NO_OS_BIT(2)

#define	AD9528_PD_OUT_CLOCKS NO_OS_BIT(1)

#define	AD9528_PD_CHIP NO_OS_BIT(0)

#define	AD9528_CHANNEL_PD_MASK(x) (((x) & 0x3FFF) << 0)

#define	AD9528_CHANNEL_PD_MASK_REV(x) (((x) >> 0) & 0x3FFF)

#define	AD9528_IS_CALIBRATING (1 << 8)

#define	AD9528_PLL2_OK (1 << 7)

#define	AD9528_PLL1_OK (1 << 6)

#define	AD9528_VCXO_OK (1 << 5)

#define	AD9528_REFA_REFB_NOK (1 << 4)

#define	AD9528_REFB_OK (1 << 3)

#define	AD9528_REFA_OK (1 << 2)

#define	AD9528_PLL2_LOCKED (1 << 1)

#define	AD9528_PLL1_LOCKED (1 << 0)

#define	AD9528_STAT0_PIN_EN (1 << 2)

#define	AD9528_STAT1_PIN_EN (1 << 3)

#define	AD9528_STAT0_DIV_EN (1 << 1)

#define	AD9528_STAT1_DIV_EN (1 << 0)

#define	AD9528_NUM_CHAN 14

#define	AD9528_SPI_MAGIC 0x00FF05

#define	DRIVER_MODE_LVDS 0

#define	DRIVER_MODE_LVDS_BOOST 1

#define	DRIVER_MODE_HSTL 2

#define	SOURCE_VCO 0

#define	SOURCE_VCXO 1

#define	SOURCE_SYSREF_VCO 2

#define	SOURCE_SYSREF_VCXO 3

#define	SOURCE_VCXO_INV 5

#define	SOURCE_SYSREF_VCXO_INV 7

#define	REF_MODE_STAY_ON_REFB 0

#define	REF_MODE_REVERT_TO_REFA 1

#define	REF_MODE_SELECT_REFA 2

#define	REF_MODE_SELECT_REFB 3

#define	REF_MODE_EXT_REF 4

#define	SYSREF_SRC_EXTERNAL 0

#define	SYSREF_SRC_EXTERNAL_RESAMPLED 1

#define	SYSREF_SRC_INTERNAL 2

#define	SYSREF_PATTERN_NSHOT 0

#define	SYSREF_PATTERN_CONTINUOUS 1

#define	SYSREF_PATTERN_PRBS 2

#define	SYSREF_PATTERN_STOP 3

#define	SYSREF_NSHOT_1_PULSE 1

#define	SYSREF_NSHOT_2_PULSES 2

#define	SYSREF_NSHOT_4_PULSES 3

#define	SYSREF_NSHOT_6_PULSES 4

#define	SYSREF_NSHOT_8_PULSES 5

#define	SYSREF_LEVEL_HIGH 0

#define	SYSREF_EDGE_RISING 2

#define	SYSREF_EDGE_FALLING 3

#define	RPOLE2_900_OHM 0

#define	RPOLE2_450_OHM 1

#define	RPOLE2_300_OHM 2

#define	RPOLE2_225_OHM 3

#define	RZERO_3250_OHM 0

#define	RZERO_2750_OHM 1

#define	RZERO_2250_OHM 2

#define	RZERO_2100_OHM 3

#define	RZERO_3000_OHM 4

#define	RZERO_2500_OHM 5

#define	RZERO_2000_OHM 6

#define	RZERO_1850_OHM 7

#define	CPOLE1_0_PF 0

#define	CPOLE1_8_PF 1

#define	CPOLE1_16_PF 2

#define	CPOLE1_24_PF 3

#define	CPOLE1_32_PF 5

#define	CPOLE1_40_PF 6

#define	CPOLE1_48_PF 7

#define	AD_IFE(_pde, _a, _b) ((dev->pdata->_pde) ? _a : _b)

#define	AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)

Enumerations
enum	{ AD9528_STAT_PLL1_LD, AD9528_STAT_PLL2_LD, AD9528_STAT_REFA, AD9528_STAT_REFB, AD9528_STAT_REFAB_MISSING, AD9528_STAT_VCXO, AD9528_STAT_PLL1_FB_CLK, AD9528_STAT_PLL2_FB_CLK, AD9528_SYNC }

enum	{ AD9528_VCO, AD9528_VCXO, AD9528_SYSREF, AD9528_NUM_CLK_SRC }

Functions
int32_t	ad9528_init (struct ad9528_init_param *init_param)
	Initializes the AD9528. More...

int32_t	ad9528_setup (struct ad9528_dev **device, struct ad9528_init_param init_param)
	Initializes the AD9528. More...

int32_t	ad9528_spi_read (struct ad9528_dev dev, uint32_t reg_addr, uint32_t reg_data)
	Reads the value of the selected register. More...

int32_t	ad9528_spi_write (struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
	Writes a value to the selected register. More...

int32_t	ad9528_spi_read_n (struct ad9528_dev dev, uint32_t reg_addr, uint32_t reg_data)
	Reads the value of the selected register. More...

int32_t	ad9528_spi_write_n (struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
	Writes a value to the selected register. More...

int32_t	ad9528_poll (struct ad9528_dev *dev, uint32_t reg_addr, uint32_t mask, uint32_t data)
	Poll register. More...

int32_t	ad9528_io_update (struct ad9528_dev *dev)
	Updates the AD9528 configuration. More...

int32_t	ad9528_sync (struct ad9528_dev *dev)
	Updates the AD9528 configuration. More...

uint32_t	ad9528_clk_round_rate (struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
	Calculate closest possible rate. More...

int32_t	ad9528_clk_set_rate (struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
	Set channel rate. More...

int32_t	ad9528_reset (struct ad9528_dev *dev)
	Performs a hard reset on the AD9528. More...

int32_t	ad9528_remove (struct ad9528_dev *dev)
	Free the resources allocated by ad9528_setup(). More...

Detailed Description

Header file of AD9528 Driver.

Author: DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
The use of this software may or may not infringe the patent rights of one or more patent holders. This license does not release you from the requirement that you obtain separate licenses from these patent holders to use this software.
Use of the software either in source or binary form, must be run on or directly connected to an Analog Devices Inc. component.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD9528_1B

#define AD9528_1B ( x ) ((1 << 16) | ((x) + 0))

◆ AD9528_2B

#define AD9528_2B ( x ) ((2 << 16) | ((x) + 1))

◆ AD9528_3B

#define AD9528_3B ( x ) ((3 << 16) | ((x) + 2))

◆ AD9528_4B

#define AD9528_4B ( x ) ((4 << 16) | ((x) + 3))

◆ AD9528_ADDR

#define AD9528_ADDR ( x ) ((x) & 0xFFF)

◆ AD9528_CHANNEL_IGNORE_MASK

#define AD9528_CHANNEL_IGNORE_MASK ( x ) (((x) & 0x3FFF) << 0)

◆ AD9528_CHANNEL_IGNORE_MASK_REV

#define AD9528_CHANNEL_IGNORE_MASK_REV ( x ) (((x) >> 0) & 0x3FFF)

◆ AD9528_CHANNEL_OUTPUT

#define AD9528_CHANNEL_OUTPUT ( ch ) AD9528_3B(0x300 + 3 * ch)

◆ AD9528_CHANNEL_PD_EN

#define AD9528_CHANNEL_PD_EN AD9528_2B(0x501)

◆ AD9528_CHANNEL_PD_MASK

#define AD9528_CHANNEL_PD_MASK ( x ) (((x) & 0x3FFF) << 0)

◆ AD9528_CHANNEL_PD_MASK_REV

#define AD9528_CHANNEL_PD_MASK_REV ( x ) (((x) >> 0) & 0x3FFF)

◆ AD9528_CHANNEL_SYNC

#define AD9528_CHANNEL_SYNC AD9528_1B(0x32A)

◆ AD9528_CHANNEL_SYNC_IGNORE

#define AD9528_CHANNEL_SYNC_IGNORE AD9528_2B(0x32B)

◆ AD9528_CHANNEL_SYNC_SET

#define AD9528_CHANNEL_SYNC_SET (1 << 0)

◆ AD9528_CHIP_ID

#define AD9528_CHIP_ID AD9528_4B(0x3)

◆ AD9528_CLK_DIST_CTRL

#define AD9528_CLK_DIST_CTRL ( x ) (((x) & 0x7) << 5)

◆ AD9528_CLK_DIST_CTRL_MASK

#define AD9528_CLK_DIST_CTRL_MASK (0x7 << 5)

◆ AD9528_CLK_DIST_CTRL_REV

#define AD9528_CLK_DIST_CTRL_REV ( x ) (((x) >> 5) & 0x7)

◆ AD9528_CLK_DIST_DIV

#define AD9528_CLK_DIST_DIV ( x ) ((((x) - 1) & 0xFF) << 16)

◆ AD9528_CLK_DIST_DIV_MASK

#define AD9528_CLK_DIST_DIV_MASK (0xFF << 16)

◆ AD9528_CLK_DIST_DIV_MAX

#define AD9528_CLK_DIST_DIV_MAX 256

◆ AD9528_CLK_DIST_DIV_MIN

#define AD9528_CLK_DIST_DIV_MIN 1

◆ AD9528_CLK_DIST_DIV_PHASE

#define AD9528_CLK_DIST_DIV_PHASE ( x ) (((x) & 0x3F) << 8)

◆ AD9528_CLK_DIST_DIV_PHASE_REV

#define AD9528_CLK_DIST_DIV_PHASE_REV ( x ) (((x) >> 8) & 0x3F)

◆ AD9528_CLK_DIST_DIV_REV

#define AD9528_CLK_DIST_DIV_REV ( x ) ((((x) >> 16) & 0xFF) + 1)

◆ AD9528_CLK_DIST_DRIVER_MODE

#define AD9528_CLK_DIST_DRIVER_MODE ( x ) (((x) & 0x3) << 14)

◆ AD9528_CLK_DIST_DRIVER_MODE_REV

#define AD9528_CLK_DIST_DRIVER_MODE_REV ( x ) (((x) >> 14) & 0x3)

◆ AD9528_CNT

#define AD9528_CNT ( x ) (((x) - 1) << 13)

◆ AD9528_IO_UPDATE

#define AD9528_IO_UPDATE AD9528_1B(0xF)

◆ AD9528_IO_UPDATE_EN

#define AD9528_IO_UPDATE_EN (1 << 0)

◆ AD9528_IS_CALIBRATING

#define AD9528_IS_CALIBRATING (1 << 8)

◆ AD9528_NUM_CHAN

#define AD9528_NUM_CHAN 14

◆ AD9528_PD_BIAS

#define AD9528_PD_BIAS NO_OS_BIT(4)

◆ AD9528_PD_CHIP

#define AD9528_PD_CHIP NO_OS_BIT(0)

◆ AD9528_PD_EN

#define AD9528_PD_EN AD9528_1B(0x500)

◆ AD9528_PD_OUT_CLOCKS

#define AD9528_PD_OUT_CLOCKS NO_OS_BIT(1)

◆ AD9528_PD_PLL1

#define AD9528_PD_PLL1 NO_OS_BIT(2)

◆ AD9528_PD_PLL2

#define AD9528_PD_PLL2 NO_OS_BIT(3)

◆ AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS

#define AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS (1 << 12)

◆ AD9528_PLL1_CHARGE_PUMP_CTRL

#define AD9528_PLL1_CHARGE_PUMP_CTRL AD9528_2B(0x106)

◆ AD9528_PLL1_CHARGE_PUMP_CURRENT_nA

#define AD9528_PLL1_CHARGE_PUMP_CURRENT_nA ( x ) (((x) / 500) & 0x7F)

◆ AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL

#define AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)

◆ AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN

#define AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)

◆ AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_UP

#define AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)

◆ AD9528_PLL1_CHARGE_PUMP_MODE_TRISTATE

#define AD9528_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)

◆ AD9528_PLL1_CHARGE_PUMP_TRISTATE

#define AD9528_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)

◆ AD9528_PLL1_CTRL

#define AD9528_PLL1_CTRL AD9528_3B(0x108)

◆ AD9528_PLL1_FEEDBACK_BYPASS_EN

#define AD9528_PLL1_FEEDBACK_BYPASS_EN (1 << 13)

◆ AD9528_PLL1_FEEDBACK_DIVIDER

#define AD9528_PLL1_FEEDBACK_DIVIDER AD9528_2B(0x104)

◆ AD9528_PLL1_FREQ_DETECTOR_PD_EN

#define AD9528_PLL1_FREQ_DETECTOR_PD_EN (1 << 7)

◆ AD9528_PLL1_LOCKED

#define AD9528_PLL1_LOCKED (1 << 0)

◆ AD9528_PLL1_OK

#define AD9528_PLL1_OK (1 << 6)

◆ AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN

#define AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 19)

◆ AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN

#define AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)

◆ AD9528_PLL1_OSC_IN_DIFF_EN

#define AD9528_PLL1_OSC_IN_DIFF_EN (1 << 0)

◆ AD9528_PLL1_REF_A_DIVIDER

#define AD9528_PLL1_REF_A_DIVIDER AD9528_2B(0x100)

◆ AD9528_PLL1_REF_B_DIVIDER

#define AD9528_PLL1_REF_B_DIVIDER AD9528_2B(0x102)

◆ AD9528_PLL1_REF_MODE

#define AD9528_PLL1_REF_MODE ( x ) ((x) << 16)

◆ AD9528_PLL1_REFA_BYPASS_EN

#define AD9528_PLL1_REFA_BYPASS_EN (1 << 11)

◆ AD9528_PLL1_REFA_CMOS_NEG_INP_EN

#define AD9528_PLL1_REFA_CMOS_NEG_INP_EN (1 << 8)

◆ AD9528_PLL1_REFA_DIFF_RCV_EN

#define AD9528_PLL1_REFA_DIFF_RCV_EN (1 << 5)

◆ AD9528_PLL1_REFA_RCV_EN

#define AD9528_PLL1_REFA_RCV_EN (1 << 3)

◆ AD9528_PLL1_REFB_BYPASS_EN

#define AD9528_PLL1_REFB_BYPASS_EN (1 << 12)

◆ AD9528_PLL1_REFB_CMOS_NEG_INP_EN

#define AD9528_PLL1_REFB_CMOS_NEG_INP_EN (1 << 9)

◆ AD9528_PLL1_REFB_DIFF_RCV_EN

#define AD9528_PLL1_REFB_DIFF_RCV_EN (1 << 6)

◆ AD9528_PLL1_REFB_RCV_EN

#define AD9528_PLL1_REFB_RCV_EN (1 << 4)

◆ AD9528_PLL1_SOURCE_VCXO

#define AD9528_PLL1_SOURCE_VCXO (1 << 10)

◆ AD9528_PLL1_VCXO_RCV_PD_EN

#define AD9528_PLL1_VCXO_RCV_PD_EN (1 << 2)

◆ AD9528_PLL2_CHARGE_PUMP

#define AD9528_PLL2_CHARGE_PUMP AD9528_1B(0x200)

◆ AD9528_PLL2_CHARGE_PUMP_CURRENT_nA

#define AD9528_PLL2_CHARGE_PUMP_CURRENT_nA ( x ) ((x) / 3500)

◆ AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL

#define AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)

◆ AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN

#define AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)

◆ AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_UP

#define AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)

◆ AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE

#define AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)

◆ AD9528_PLL2_CTRL

#define AD9528_PLL2_CTRL AD9528_1B(0x202)

◆ AD9528_PLL2_DOUBLER_R1_EN

#define AD9528_PLL2_DOUBLER_R1_EN (1 << 4)

◆ AD9528_PLL2_FB_NDIV

#define AD9528_PLL2_FB_NDIV	(	a,
		b
	)	(4 * (b) + (a))

◆ AD9528_PLL2_FB_NDIV_A_CNT

#define AD9528_PLL2_FB_NDIV_A_CNT ( x ) (((x) & 0x3) << 6)

◆ AD9528_PLL2_FB_NDIV_B_CNT

#define AD9528_PLL2_FB_NDIV_B_CNT ( x ) (((x) & 0x3F) << 0)

◆ AD9528_PLL2_FEEDBACK_DIVIDER_AB

#define AD9528_PLL2_FEEDBACK_DIVIDER_AB AD9528_1B(0x201)

◆ AD9528_PLL2_FORCE_REFERENCE_VALID

#define AD9528_PLL2_FORCE_REFERENCE_VALID (1 << 2)

◆ AD9528_PLL2_FORCE_VCO_MIDSCALE

#define AD9528_PLL2_FORCE_VCO_MIDSCALE (1 << 1)

◆ AD9528_PLL2_FREQ_DOUBLER_EN

#define AD9528_PLL2_FREQ_DOUBLER_EN (1 << 5)

◆ AD9528_PLL2_LOCK_DETECT_PWR_DOWN_EN

#define AD9528_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)

◆ AD9528_PLL2_LOCKED

#define AD9528_PLL2_LOCKED (1 << 1)

◆ AD9528_PLL2_LOOP_FILTER_CPOLE1

#define AD9528_PLL2_LOOP_FILTER_CPOLE1 ( x ) (((x) & 0x7) << 0)

◆ AD9528_PLL2_LOOP_FILTER_CTRL

#define AD9528_PLL2_LOOP_FILTER_CTRL AD9528_2B(0x205)

◆ AD9528_PLL2_LOOP_FILTER_RPOLE2

#define AD9528_PLL2_LOOP_FILTER_RPOLE2 ( x ) (((x) & 0x3) << 6)

◆ AD9528_PLL2_LOOP_FILTER_RZERO

#define AD9528_PLL2_LOOP_FILTER_RZERO ( x ) (((x) & 0x7) << 3)

◆ AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN

#define AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)

◆ AD9528_PLL2_N2_DIV

#define AD9528_PLL2_N2_DIV ( x ) ((((x) - 1) & 0xFF) << 0)

◆ AD9528_PLL2_N2_DIVIDER

#define AD9528_PLL2_N2_DIVIDER AD9528_1B(0x208)

◆ AD9528_PLL2_OK

#define AD9528_PLL2_OK (1 << 7)

◆ AD9528_PLL2_R1_DIV

#define AD9528_PLL2_R1_DIV ( x ) (((x) & 0x1F) << 0)

◆ AD9528_PLL2_R1_DIVIDER

#define AD9528_PLL2_R1_DIVIDER AD9528_1B(0x207)

◆ AD9528_PLL2_VCO_CALIBRATE

#define AD9528_PLL2_VCO_CALIBRATE (1 << 0)

◆ AD9528_PLL2_VCO_CTRL

#define AD9528_PLL2_VCO_CTRL AD9528_1B(0x203)

◆ AD9528_PLL2_VCO_DIV_M1

#define AD9528_PLL2_VCO_DIV_M1 ( x ) (((x) & 0x7) << 0)

◆ AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN

#define AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 3)

◆ AD9528_PLL2_VCO_DIVIDER

#define AD9528_PLL2_VCO_DIVIDER AD9528_1B(0x204)

◆ AD9528_READ

#define AD9528_READ (1 << 15)

◆ AD9528_READBACK

#define AD9528_READBACK AD9528_2B(0x508)

◆ AD9528_REFA_OK

#define AD9528_REFA_OK (1 << 2)

◆ AD9528_REFA_REFB_NOK

#define AD9528_REFA_REFB_NOK (1 << 4)

◆ AD9528_REFB_OK

#define AD9528_REFB_OK (1 << 3)

◆ AD9528_SER_CONF_ADDR_INCREMENT

#define AD9528_SER_CONF_ADDR_INCREMENT ((1 << 2) | (1 << 5))

◆ AD9528_SER_CONF_LSB_FIRST

#define AD9528_SER_CONF_LSB_FIRST ((1 << 1) | (1 << 6))

◆ AD9528_SER_CONF_READ_BUFFERED

#define AD9528_SER_CONF_READ_BUFFERED (1 << 5)

◆ AD9528_SER_CONF_RESET_SANS_REGMAP

#define AD9528_SER_CONF_RESET_SANS_REGMAP (1 << 2)

◆ AD9528_SER_CONF_SDO_ACTIVE

#define AD9528_SER_CONF_SDO_ACTIVE ((1 << 3) | (1 << 4))

◆ AD9528_SER_CONF_SOFT_RESET

#define AD9528_SER_CONF_SOFT_RESET ((1 << 0) | (1 << 7))

◆ AD9528_SERIAL_PORT_CONFIG

#define AD9528_SERIAL_PORT_CONFIG AD9528_1B(0x0)

◆ AD9528_SERIAL_PORT_CONFIG_B

#define AD9528_SERIAL_PORT_CONFIG_B AD9528_1B(0x1)

◆ AD9528_SPI_MAGIC

#define AD9528_SPI_MAGIC 0x00FF05

◆ AD9528_STAT0_DIV_EN

#define AD9528_STAT0_DIV_EN (1 << 1)

◆ AD9528_STAT0_PIN_EN

#define AD9528_STAT0_PIN_EN (1 << 2)

◆ AD9528_STAT1_DIV_EN

#define AD9528_STAT1_DIV_EN (1 << 0)

◆ AD9528_STAT1_PIN_EN

#define AD9528_STAT1_PIN_EN (1 << 3)

◆ AD9528_STAT_MON0

#define AD9528_STAT_MON0 AD9528_1B(0x505)

◆ AD9528_STAT_MON1

#define AD9528_STAT_MON1 AD9528_1B(0x506)

◆ AD9528_STAT_PIN_EN

#define AD9528_STAT_PIN_EN AD9528_1B(0x507)

◆ AD9528_SYSREF_CTRL

#define AD9528_SYSREF_CTRL AD9528_2B(0x402)

◆ AD9528_SYSREF_K_DIV

#define AD9528_SYSREF_K_DIV ( x ) (((x) & 0xFFFF) << 0)

◆ AD9528_SYSREF_K_DIV_MAX

#define AD9528_SYSREF_K_DIV_MAX (65535u)

◆ AD9528_SYSREF_K_DIV_MIN

#define AD9528_SYSREF_K_DIV_MIN (1u)

◆ AD9528_SYSREF_K_DIVIDER

#define AD9528_SYSREF_K_DIVIDER AD9528_2B(0x400)

◆ AD9528_SYSREF_NSHOT_MODE

#define AD9528_SYSREF_NSHOT_MODE ( x ) (((x) & 0x7) << 9)

◆ AD9528_SYSREF_PATTERN_CLK_SRC_PLL1

#define AD9528_SYSREF_PATTERN_CLK_SRC_PLL1 (1 << 3)

◆ AD9528_SYSREF_PATTERN_MODE

#define AD9528_SYSREF_PATTERN_MODE ( x ) (((x) & 0x3) << 12)

◆ AD9528_SYSREF_PATTERN_REQ

#define AD9528_SYSREF_PATTERN_REQ (1 << 8)

◆ AD9528_SYSREF_PATTERN_TRIGGER_CTRL

#define AD9528_SYSREF_PATTERN_TRIGGER_CTRL ( x ) (((x) & 0x3) << 5)

◆ AD9528_SYSREF_REQUEST_BY_PIN

#define AD9528_SYSREF_REQUEST_BY_PIN (1 << 7)

◆ AD9528_SYSREF_RESAMPLE_CTRL

#define AD9528_SYSREF_RESAMPLE_CTRL AD9528_2B(0x32D)

◆ AD9528_SYSREF_RESAMPLER_CLK_SRC_PLL1

#define AD9528_SYSREF_RESAMPLER_CLK_SRC_PLL1 (1 << 4)

◆ AD9528_SYSREF_RESET

#define AD9528_SYSREF_RESET (1 << 0)

◆ AD9528_SYSREF_SOURCE

#define AD9528_SYSREF_SOURCE ( x ) (((x) & 0x3) << 14)

◆ AD9528_SYSREF_TEST_MODE

#define AD9528_SYSREF_TEST_MODE ( x ) (((x) & 0x3) << 1)

◆ AD9528_TRANSF_LEN

#define AD9528_TRANSF_LEN ( x ) ((x) >> 16)

◆ AD9528_VCXO_OK

#define AD9528_VCXO_OK (1 << 5)

◆ AD9528_WRITE

#define AD9528_WRITE (0 << 15)

◆ AD_IF

#define AD_IF	(	_pde,
		_a
	)	AD_IFE(_pde, _a, 0)

◆ AD_IFE

#define AD_IFE	(	_pde,
		_a,
		_b
	)	((dev->pdata->_pde) ? _a : _b)

◆ CPOLE1_0_PF

#define CPOLE1_0_PF 0

◆ CPOLE1_16_PF

#define CPOLE1_16_PF 2

◆ CPOLE1_24_PF

#define CPOLE1_24_PF 3

◆ CPOLE1_32_PF

#define CPOLE1_32_PF 5

◆ CPOLE1_40_PF

#define CPOLE1_40_PF 6

◆ CPOLE1_48_PF

#define CPOLE1_48_PF 7

◆ CPOLE1_8_PF

#define CPOLE1_8_PF 1

◆ DRIVER_MODE_HSTL

#define DRIVER_MODE_HSTL 2

◆ DRIVER_MODE_LVDS

#define DRIVER_MODE_LVDS 0

◆ DRIVER_MODE_LVDS_BOOST

#define DRIVER_MODE_LVDS_BOOST 1

◆ REF_MODE_EXT_REF

#define REF_MODE_EXT_REF 4

◆ REF_MODE_REVERT_TO_REFA

#define REF_MODE_REVERT_TO_REFA 1

◆ REF_MODE_SELECT_REFA

#define REF_MODE_SELECT_REFA 2

◆ REF_MODE_SELECT_REFB

#define REF_MODE_SELECT_REFB 3

◆ REF_MODE_STAY_ON_REFB

#define REF_MODE_STAY_ON_REFB 0

◆ RPOLE2_225_OHM

#define RPOLE2_225_OHM 3

◆ RPOLE2_300_OHM

#define RPOLE2_300_OHM 2

◆ RPOLE2_450_OHM

#define RPOLE2_450_OHM 1

◆ RPOLE2_900_OHM

#define RPOLE2_900_OHM 0

◆ RZERO_1850_OHM

#define RZERO_1850_OHM 7

◆ RZERO_2000_OHM

#define RZERO_2000_OHM 6

◆ RZERO_2100_OHM

#define RZERO_2100_OHM 3

◆ RZERO_2250_OHM

#define RZERO_2250_OHM 2

◆ RZERO_2500_OHM

#define RZERO_2500_OHM 5

◆ RZERO_2750_OHM

#define RZERO_2750_OHM 1

◆ RZERO_3000_OHM

#define RZERO_3000_OHM 4

◆ RZERO_3250_OHM

#define RZERO_3250_OHM 0

◆ SOURCE_SYSREF_VCO

#define SOURCE_SYSREF_VCO 2

◆ SOURCE_SYSREF_VCXO

#define SOURCE_SYSREF_VCXO 3

◆ SOURCE_SYSREF_VCXO_INV

#define SOURCE_SYSREF_VCXO_INV 7

◆ SOURCE_VCO

#define SOURCE_VCO 0

◆ SOURCE_VCXO

#define SOURCE_VCXO 1

◆ SOURCE_VCXO_INV

#define SOURCE_VCXO_INV 5

◆ SYSREF_EDGE_FALLING

#define SYSREF_EDGE_FALLING 3

◆ SYSREF_EDGE_RISING

#define SYSREF_EDGE_RISING 2

◆ SYSREF_LEVEL_HIGH

#define SYSREF_LEVEL_HIGH 0

◆ SYSREF_NSHOT_1_PULSE

#define SYSREF_NSHOT_1_PULSE 1

◆ SYSREF_NSHOT_2_PULSES

#define SYSREF_NSHOT_2_PULSES 2

◆ SYSREF_NSHOT_4_PULSES

#define SYSREF_NSHOT_4_PULSES 3

◆ SYSREF_NSHOT_6_PULSES

#define SYSREF_NSHOT_6_PULSES 4

◆ SYSREF_NSHOT_8_PULSES

#define SYSREF_NSHOT_8_PULSES 5

◆ SYSREF_PATTERN_CONTINUOUS

#define SYSREF_PATTERN_CONTINUOUS 1

◆ SYSREF_PATTERN_NSHOT

#define SYSREF_PATTERN_NSHOT 0

◆ SYSREF_PATTERN_PRBS

#define SYSREF_PATTERN_PRBS 2

◆ SYSREF_PATTERN_STOP

#define SYSREF_PATTERN_STOP 3

◆ SYSREF_SRC_EXTERNAL

#define SYSREF_SRC_EXTERNAL 0

◆ SYSREF_SRC_EXTERNAL_RESAMPLED

#define SYSREF_SRC_EXTERNAL_RESAMPLED 1

◆ SYSREF_SRC_INTERNAL

#define SYSREF_SRC_INTERNAL 2

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
AD9528_STAT_PLL1_LD
AD9528_STAT_PLL2_LD
AD9528_STAT_REFA
AD9528_STAT_REFB
AD9528_STAT_REFAB_MISSING
AD9528_STAT_VCXO
AD9528_STAT_PLL1_FB_CLK
AD9528_STAT_PLL2_FB_CLK
AD9528_SYNC

◆ anonymous enum

anonymous enum

Enumerator
AD9528_VCO
AD9528_VCXO
AD9528_SYSREF
AD9528_NUM_CLK_SRC

Function Documentation

◆ ad9528_clk_round_rate()

uint32_t ad9528_clk_round_rate	(	struct ad9528_dev *	dev,
		uint32_t	chan,
		uint32_t	rate
	)

Calculate closest possible rate.

Parameters

dev	- is a pointer to the ad9528_dev data structure.
chan	- The output channel.
rate	- The desired rate.

Returns: The closest possible rate of desired rate.

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◆ ad9528_clk_set_rate()

int32_t ad9528_clk_set_rate	(	struct ad9528_dev *	dev,
		uint32_t	chan,
		uint32_t	rate
	)

Set channel rate.

Parameters

dev	- is a pointer to the ad9528_dev data structure.
chan	- Channel number.
rate	- Channel rate in Hz.

Returns: 0 in case of success, negative error code otherwise.

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◆ ad9528_init()

int32_t ad9528_init ( struct ad9528_init_param * init_param )

Initializes the AD9528.

Parameters

init_param - The structure containing the device initial parameters.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_io_update()

int32_t ad9528_io_update ( struct ad9528_dev * dev )

Updates the AD9528 configuration.

Parameters

dev	- The device structure.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_poll()

int32_t ad9528_poll	(	struct ad9528_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	mask,
		uint32_t	data
	)

Poll register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register.
mask	- The mask that is applied.
data	- The expected data.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_remove()

int32_t ad9528_remove ( struct ad9528_dev * dev )

Free the resources allocated by ad9528_setup().

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

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◆ ad9528_reset()

int32_t ad9528_reset ( struct ad9528_dev * dev )

Performs a hard reset on the AD9528.

Parameters

dev	is a pointer to the ad9528_dev data structure.

Returns: Returns 0 for success, negative value for failure.

◆ ad9528_setup()

int32_t ad9528_setup	(	struct ad9528_dev **	device,
		struct ad9528_init_param	init_param
	)

Initializes the AD9528.

Parameters

device	- The device structure.
init_param	- The structure containing the device initial parameters.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_spi_read()

int32_t ad9528_spi_read	(	struct ad9528_dev *	dev,
		uint32_t	reg_addr,
		uint32_t *	reg_data
	)

Reads the value of the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to read
reg_data	- The register's value.

Returns: Returns 0 in case of success or negative error code.

◆ ad9528_spi_read_n()

int32_t ad9528_spi_read_n	(	struct ad9528_dev *	dev,
		uint32_t	reg_addr,
		uint32_t *	reg_data
	)

Reads the value of the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to read - address[31:16] holds the number of bytes to read (a round about method)– it is also limited to 4 bytes max (to fill in a 32 bit integer type).
reg_data	- The register's value.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_spi_write()

int32_t ad9528_spi_write	(	struct ad9528_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	reg_data
	)

Writes a value to the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to write
reg_data	- The value to write to the register.

Returns: Returns 0 in case of success or negative error code.

◆ ad9528_spi_write_n()

int32_t ad9528_spi_write_n	(	struct ad9528_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	reg_data
	)

Writes a value to the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to write - address[31:16] holds the number of bytes to write (a round about method)– it is also limited to 4 bytes max (to fill in a 32 bit integer type).
reg_data	- The value to write to the register.

Returns: Returns 0 in case of success or negative error code.

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◆ ad9528_sync()

int32_t ad9528_sync ( struct ad9528_dev * dev )

Updates the AD9528 configuration.

Parameters

dev	- The device structure.

Returns: Returns 0 in case of success or negative error code.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ AD9528_1B

◆ AD9528_2B

◆ AD9528_3B

◆ AD9528_4B

◆ AD9528_ADDR

◆ AD9528_CHANNEL_IGNORE_MASK

◆ AD9528_CHANNEL_IGNORE_MASK_REV

◆ AD9528_CHANNEL_OUTPUT

◆ AD9528_CHANNEL_PD_EN

◆ AD9528_CHANNEL_PD_MASK

◆ AD9528_CHANNEL_PD_MASK_REV

◆ AD9528_CHANNEL_SYNC

◆ AD9528_CHANNEL_SYNC_IGNORE

◆ AD9528_CHANNEL_SYNC_SET

◆ AD9528_CHIP_ID

◆ AD9528_CLK_DIST_CTRL

◆ AD9528_CLK_DIST_CTRL_MASK

◆ AD9528_CLK_DIST_CTRL_REV

◆ AD9528_CLK_DIST_DIV

◆ AD9528_CLK_DIST_DIV_MASK

◆ AD9528_CLK_DIST_DIV_MAX

◆ AD9528_CLK_DIST_DIV_MIN

◆ AD9528_CLK_DIST_DIV_PHASE

◆ AD9528_CLK_DIST_DIV_PHASE_REV

◆ AD9528_CLK_DIST_DIV_REV

◆ AD9528_CLK_DIST_DRIVER_MODE

◆ AD9528_CLK_DIST_DRIVER_MODE_REV

◆ AD9528_CNT

◆ AD9528_IO_UPDATE

◆ AD9528_IO_UPDATE_EN

◆ AD9528_IS_CALIBRATING

◆ AD9528_NUM_CHAN

◆ AD9528_PD_BIAS

◆ AD9528_PD_CHIP

◆ AD9528_PD_EN

◆ AD9528_PD_OUT_CLOCKS

◆ AD9528_PD_PLL1

◆ AD9528_PD_PLL2

◆ AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS

◆ AD9528_PLL1_CHARGE_PUMP_CTRL

◆ AD9528_PLL1_CHARGE_PUMP_CURRENT_nA

◆ AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL

◆ AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN

◆ AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_UP

◆ AD9528_PLL1_CHARGE_PUMP_MODE_TRISTATE

◆ AD9528_PLL1_CHARGE_PUMP_TRISTATE

◆ AD9528_PLL1_CTRL

◆ AD9528_PLL1_FEEDBACK_BYPASS_EN

◆ AD9528_PLL1_FEEDBACK_DIVIDER

◆ AD9528_PLL1_FREQ_DETECTOR_PD_EN

◆ AD9528_PLL1_LOCKED

◆ AD9528_PLL1_OK

◆ AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN

◆ AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN

◆ AD9528_PLL1_OSC_IN_DIFF_EN

◆ AD9528_PLL1_REF_A_DIVIDER

◆ AD9528_PLL1_REF_B_DIVIDER

◆ AD9528_PLL1_REF_MODE

◆ AD9528_PLL1_REFA_BYPASS_EN

◆ AD9528_PLL1_REFA_CMOS_NEG_INP_EN

◆ AD9528_PLL1_REFA_DIFF_RCV_EN

◆ AD9528_PLL1_REFA_RCV_EN

◆ AD9528_PLL1_REFB_BYPASS_EN

◆ AD9528_PLL1_REFB_CMOS_NEG_INP_EN

◆ AD9528_PLL1_REFB_DIFF_RCV_EN

◆ AD9528_PLL1_REFB_RCV_EN

◆ AD9528_PLL1_SOURCE_VCXO

◆ AD9528_PLL1_VCXO_RCV_PD_EN

◆ AD9528_PLL2_CHARGE_PUMP

◆ AD9528_PLL2_CHARGE_PUMP_CURRENT_nA

◆ AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL

◆ AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN

◆ AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_UP

◆ AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE