Channel CPACK Utility

The channel CPACK utility core is meant to allow one or more channels to be enabled by software without any padding. This allows full usage of the DMA bandwidth without any overhead. This core normally works with an ADC and DMA modules. The ADC interface is channel based (one interface per each ADC channel) and consists of enable, valid and data signals. The DMA interface is a single FIFO interface consisting of valid and data signals. The enable signals are usually controlled by software. The core simply packs the ADC data of the individual channels into a single data bus, as defined by the ADC enables.

Features

• Supports Altera and AMD Xilinx devices

• Supports up to 64 channels

• Supports configurable channel data width

Files

Name	Description
library/util_pack/util_cpack2/util_cpack2.v	Verilog source for the peripheral.

Configuration Parameters

Name	Description	Default Value	Choices/Range
NUM_OF_CHANNELS	Number of Channels.	4
SAMPLES_PER_CHANNEL	Samples per Channel.	1
SAMPLE_DATA_WIDTH	Sample Width.	16
INTERFACE_TYPE	Interface Type.	1	AXI Streaming (0), FIFO Interface (1)
PARALLEL_OR_SERIAL_N	Parallel prefix sum calculation.	0	Serial (0), Parallel (1)
PIPELINE_STAGES	Configure pipeline stages.	0

The INTERFACE_TYPE parameter refers to the upstream interface type: 1 means FIFO interface, 0 means AXI Stream interface.

The PARALLEL_OR_SERIAL_N parameter refers to how the prefix sum is being implemented inside the IP: 1 means a log-depth structure, 0 means a serial structure. The former may pass timing easier at higher frequencies, while the latter may use fewer resources. Choosing one or the other does not affect the IP functionality.

The PIPELINE_STAGES parameter refers to how or if pipeline stages are added to the design: 0 means no pipeline added, 1 means a pipeline after every 2 MUX stages, 2 means a pipeline after every MUX stage.

Note

Pipelining is not supported in AXI Stream interface mode (i.e. if INTERFACE_TYPE=0). In this case, the PIPELINE_STAGES parameter is ignored.

Interface

m_axis

Enabled if INTERFACE_TYPE = 0.

Physical Port	Logical Port	Direction	Dependency
m_axis_ready	TREADY	in	INTERFACE_TYPE = 0
m_axis_valid	TVALID	out	INTERFACE_TYPE = 0
m_axis_data	TDATA	out [63:0]	INTERFACE_TYPE = 0
m_axis_keep	TKEEP	out [7:0]	INTERFACE_TYPE = 0
m_axis_last	TLAST	out	INTERFACE_TYPE = 0

packed_fifo_wr

Enabled if INTERFACE_TYPE = 1.

FIFO interface to the DMA (sink). packed_fifo_wr_sync controls the correct alignment, when the source and sink interface data width is different. When this bit is asserted, the first sample on the DMA interface (16-bit LSB), must be a sample of the first channel.

Physical Port	Logical Port	Direction	Dependency
packed_fifo_wr_en	EN	out	INTERFACE_TYPE = 1
packed_fifo_wr_data	DATA	out [63:0]	INTERFACE_TYPE = 1
packed_fifo_wr_overflow	OVERFLOW	in	INTERFACE_TYPE = 1

Ports

Physical Port	Direction	Dependency	Description
clk	in		Bus m_axis_packed_fifo_wr is synchronous to this clock domain.
reset	in		Bus m_axis_packed_fifo_wr is synchronous to this reset signal.
fifo_wr_en	in		Indicates that at least one payload from fifo_wr_data_* is valid.
fifo_wr_overflow	out
packed_sync	out	INTERFACE_TYPE = 1
enable_*	in		Indicates the status of the channel, if asserted the channel is active.
fifo_wr_data_*	in [15:0]		ADC data bus from the ADC core.

Detailed Description

The core “collects” samples from the ADC interface and passes it to the DMA (or any other sink module), the data flow is controlled by the ADC. This is best explained through some examples. Let’s consider a 4 channel ADC with a channel data width of 32 bits. The ADC core provides two 16-bit samples on its output for all channels when the valid is asserted. The DMA interface, in this case, is an interleaved 8 samples (128 bits) stream. This is because irrespective of the ADC channel data width, the software always sees data as “samples interleaved”. The same data set may received by the DMA core with a channel width of 128 bits or 16 bits.

Four channel enabled (4’b1111)

Three channel enabled (4’b1110)

Two channel enabled (4’b1100)

References

• HDL IP core at library/util_pack/util_cpack2