CN0585 HDL project

The EVAL-CN0585-FMCZ Low Latency Development Kit (LLDK) board is a development board consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector. Current revision of EVAL-CN0585-FMCZ is Rev B. EVAL-CN0585-FMCZ, EVAL-CN0585-FMCZ and - ZedBoard are connected together to build a development system setup.

Supported boards

Supported devices

Supported carriers

Evaluation board	Carrier	FMC slot
CN0585 + CN0584	ZedBoard	FMC-LPC

Block design

The architecture is composed of two AD3552R digital-to-analog converter interface IPs and four LTC2387-16 analog-to-digital converter interface IPs. All these IPs utilize an 120MHz reference clock, which is produced by an axi_clkgen IP.

Block diagram

The data path and clock domains are depicted in the below diagram:

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq/Microblaze
axi_ltc2387_0	0X44A0_0000
axi_ltc2387_1	0X44A1_0000
axi_ltc2387_2	0X44A2_0000
axi_ltc2387_3	0X44A3_0000
axi_ltc2387_dma	0X44A4_0000
axi_clkgen	0X44B0_0000
axi_pwm_gen	0X44B1_0000
max_spi	0X44B2_0000
axi_ad35xxr_0	0X44D0_0000
axi_dac_0_dma	0X44D3_0000
axi_ad35xxr_1	0X44E0_0000
axi_dac_1_dma	0X44E3_0000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	max_spi	MAX7301	0

GPIOs

To know how the Software GPIO numbers are calculated, check out GPIOs - HDL Architecture page.

GPIO signal	Direction	HDL no.	Zynq-7000
reset	INOUT	36	90
dac_0_ldac	INOUT	35	89
dac_1_ldac	INOUT	34	88
dac_1_alert	IN	33	87
dac_0_alert	IN	32	86

Legend

GPIO signal = name of the GPIO in the HDL project
Direction = from the FPGA point of view
HDL no. = EMIO GPIO number in the HDL
Zynq-7000 = Software GPIO to be used in device trees

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ltc2387_dma	13	57	89
max_spi	8	52	84
axi_dac_0_dma	5	34	66
axi_dac_1_dma	4	33	65

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

~$

cd hdl/projects/cn0585/zed

~/hdl/projects/cn0585/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

CN0585 HDL project source code

IP name	Source code link	Documentation link
AXI_AD35XXR	library/axi_ad35xxr	AXI AD35XXR
AXI_LTC2387	library/axi_ltc2387	AXI LTC2387
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
UTIL_I2C_MIXER	library/util_i2c_mixer	—
UTIL_PACK/UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.