Documentation/MAX32650/dma__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    __IO uint32_t cfg;

    __IO uint32_t st;

    __IO uint32_t src;

    __IO uint32_t dst;

    __IO uint32_t cnt;

    __IO uint32_t src_rld;

    __IO uint32_t dst_rld;

    __IO uint32_t cnt_rld;

} mxc_dma_ch_regs_t;


typedef struct {

    __IO uint32_t cn;

    __I  uint32_t intr;

    __R  uint32_t rsv_0x8_0xff[62];

    __IO mxc_dma_ch_regs_t    ch[16];

} mxc_dma_regs_t;


/* Register offsets for module DMA */

#define MXC_R_DMA_CFG                      ((uint32_t)0x00000000UL)

#define MXC_R_DMA_ST                       ((uint32_t)0x00000004UL)

#define MXC_R_DMA_SRC                      ((uint32_t)0x00000008UL)

#define MXC_R_DMA_DST                      ((uint32_t)0x0000000CUL)

#define MXC_R_DMA_CNT                      ((uint32_t)0x00000010UL)

#define MXC_R_DMA_SRC_RLD                  ((uint32_t)0x00000014UL)

#define MXC_R_DMA_DST_RLD                  ((uint32_t)0x00000018UL)

#define MXC_R_DMA_CNT_RLD                  ((uint32_t)0x0000001CUL)

#define MXC_R_DMA_CN                       ((uint32_t)0x00000000UL)

#define MXC_R_DMA_INTR                     ((uint32_t)0x00000004UL)

#define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL)

#define MXC_F_DMA_CN_CH0_IEN_POS                       0

#define MXC_F_DMA_CN_CH0_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS))

#define MXC_V_DMA_CN_CH0_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH0_IEN_DIS                       (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS)

#define MXC_V_DMA_CN_CH0_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH0_IEN_EN                        (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS)

#define MXC_F_DMA_CN_CH1_IEN_POS                       1

#define MXC_F_DMA_CN_CH1_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS))

#define MXC_V_DMA_CN_CH1_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH1_IEN_DIS                       (MXC_V_DMA_CN_CH1_IEN_DIS << MXC_F_DMA_CN_CH1_IEN_POS)

#define MXC_V_DMA_CN_CH1_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH1_IEN_EN                        (MXC_V_DMA_CN_CH1_IEN_EN << MXC_F_DMA_CN_CH1_IEN_POS)

#define MXC_F_DMA_CN_CH2_IEN_POS                       2

#define MXC_F_DMA_CN_CH2_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS))

#define MXC_V_DMA_CN_CH2_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH2_IEN_DIS                       (MXC_V_DMA_CN_CH2_IEN_DIS << MXC_F_DMA_CN_CH2_IEN_POS)

#define MXC_V_DMA_CN_CH2_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH2_IEN_EN                        (MXC_V_DMA_CN_CH2_IEN_EN << MXC_F_DMA_CN_CH2_IEN_POS)

#define MXC_F_DMA_CN_CH3_IEN_POS                       3

#define MXC_F_DMA_CN_CH3_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS))

#define MXC_V_DMA_CN_CH3_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH3_IEN_DIS                       (MXC_V_DMA_CN_CH3_IEN_DIS << MXC_F_DMA_CN_CH3_IEN_POS)

#define MXC_V_DMA_CN_CH3_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH3_IEN_EN                        (MXC_V_DMA_CN_CH3_IEN_EN << MXC_F_DMA_CN_CH3_IEN_POS)

#define MXC_F_DMA_CN_CH4_IEN_POS                       4

#define MXC_F_DMA_CN_CH4_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH4_IEN_POS))

#define MXC_V_DMA_CN_CH4_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH4_IEN_DIS                       (MXC_V_DMA_CN_CH4_IEN_DIS << MXC_F_DMA_CN_CH4_IEN_POS)

#define MXC_V_DMA_CN_CH4_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH4_IEN_EN                        (MXC_V_DMA_CN_CH4_IEN_EN << MXC_F_DMA_CN_CH4_IEN_POS)

#define MXC_F_DMA_CN_CH5_IEN_POS                       5

#define MXC_F_DMA_CN_CH5_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH5_IEN_POS))

#define MXC_V_DMA_CN_CH5_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH5_IEN_DIS                       (MXC_V_DMA_CN_CH5_IEN_DIS << MXC_F_DMA_CN_CH5_IEN_POS)

#define MXC_V_DMA_CN_CH5_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH5_IEN_EN                        (MXC_V_DMA_CN_CH5_IEN_EN << MXC_F_DMA_CN_CH5_IEN_POS)

#define MXC_F_DMA_CN_CH6_IEN_POS                       6

#define MXC_F_DMA_CN_CH6_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH6_IEN_POS))

#define MXC_V_DMA_CN_CH6_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH6_IEN_DIS                       (MXC_V_DMA_CN_CH6_IEN_DIS << MXC_F_DMA_CN_CH6_IEN_POS)

#define MXC_V_DMA_CN_CH6_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH6_IEN_EN                        (MXC_V_DMA_CN_CH6_IEN_EN << MXC_F_DMA_CN_CH6_IEN_POS)

#define MXC_F_DMA_CN_CH7_IEN_POS                       7

#define MXC_F_DMA_CN_CH7_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH7_IEN_POS))

#define MXC_V_DMA_CN_CH7_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH7_IEN_DIS                       (MXC_V_DMA_CN_CH7_IEN_DIS << MXC_F_DMA_CN_CH7_IEN_POS)

#define MXC_V_DMA_CN_CH7_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH7_IEN_EN                        (MXC_V_DMA_CN_CH7_IEN_EN << MXC_F_DMA_CN_CH7_IEN_POS)

#define MXC_F_DMA_CN_CH8_IEN_POS                       8

#define MXC_F_DMA_CN_CH8_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH8_IEN_POS))

#define MXC_V_DMA_CN_CH8_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH8_IEN_DIS                       (MXC_V_DMA_CN_CH8_IEN_DIS << MXC_F_DMA_CN_CH8_IEN_POS)

#define MXC_V_DMA_CN_CH8_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH8_IEN_EN                        (MXC_V_DMA_CN_CH8_IEN_EN << MXC_F_DMA_CN_CH8_IEN_POS)

#define MXC_F_DMA_CN_CH9_IEN_POS                       9

#define MXC_F_DMA_CN_CH9_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH9_IEN_POS))

#define MXC_V_DMA_CN_CH9_IEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH9_IEN_DIS                       (MXC_V_DMA_CN_CH9_IEN_DIS << MXC_F_DMA_CN_CH9_IEN_POS)

#define MXC_V_DMA_CN_CH9_IEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH9_IEN_EN                        (MXC_V_DMA_CN_CH9_IEN_EN << MXC_F_DMA_CN_CH9_IEN_POS)

#define MXC_F_DMA_CN_CH10_IEN_POS                      10

#define MXC_F_DMA_CN_CH10_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH10_IEN_POS))

#define MXC_V_DMA_CN_CH10_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH10_IEN_DIS                      (MXC_V_DMA_CN_CH10_IEN_DIS << MXC_F_DMA_CN_CH10_IEN_POS)

#define MXC_V_DMA_CN_CH10_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH10_IEN_EN                       (MXC_V_DMA_CN_CH10_IEN_EN << MXC_F_DMA_CN_CH10_IEN_POS)

#define MXC_F_DMA_CN_CH11_IEN_POS                      11

#define MXC_F_DMA_CN_CH11_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH11_IEN_POS))

#define MXC_V_DMA_CN_CH11_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH11_IEN_DIS                      (MXC_V_DMA_CN_CH11_IEN_DIS << MXC_F_DMA_CN_CH11_IEN_POS)

#define MXC_V_DMA_CN_CH11_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH11_IEN_EN                       (MXC_V_DMA_CN_CH11_IEN_EN << MXC_F_DMA_CN_CH11_IEN_POS)

#define MXC_F_DMA_CN_CH12_IEN_POS                      12

#define MXC_F_DMA_CN_CH12_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH12_IEN_POS))

#define MXC_V_DMA_CN_CH12_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH12_IEN_DIS                      (MXC_V_DMA_CN_CH12_IEN_DIS << MXC_F_DMA_CN_CH12_IEN_POS)

#define MXC_V_DMA_CN_CH12_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH12_IEN_EN                       (MXC_V_DMA_CN_CH12_IEN_EN << MXC_F_DMA_CN_CH12_IEN_POS)

#define MXC_F_DMA_CN_CH13_IEN_POS                      13

#define MXC_F_DMA_CN_CH13_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH13_IEN_POS))

#define MXC_V_DMA_CN_CH13_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH13_IEN_DIS                      (MXC_V_DMA_CN_CH13_IEN_DIS << MXC_F_DMA_CN_CH13_IEN_POS)

#define MXC_V_DMA_CN_CH13_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH13_IEN_EN                       (MXC_V_DMA_CN_CH13_IEN_EN << MXC_F_DMA_CN_CH13_IEN_POS)

#define MXC_F_DMA_CN_CH14_IEN_POS                      14

#define MXC_F_DMA_CN_CH14_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH14_IEN_POS))

#define MXC_V_DMA_CN_CH14_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH14_IEN_DIS                      (MXC_V_DMA_CN_CH14_IEN_DIS << MXC_F_DMA_CN_CH14_IEN_POS)

#define MXC_V_DMA_CN_CH14_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH14_IEN_EN                       (MXC_V_DMA_CN_CH14_IEN_EN << MXC_F_DMA_CN_CH14_IEN_POS)

#define MXC_F_DMA_CN_CH15_IEN_POS                      15

#define MXC_F_DMA_CN_CH15_IEN                          ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH15_IEN_POS))

#define MXC_V_DMA_CN_CH15_IEN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CN_CH15_IEN_DIS                      (MXC_V_DMA_CN_CH15_IEN_DIS << MXC_F_DMA_CN_CH15_IEN_POS)

#define MXC_V_DMA_CN_CH15_IEN_EN                       ((uint32_t)0x1UL)

#define MXC_S_DMA_CN_CH15_IEN_EN                       (MXC_V_DMA_CN_CH15_IEN_EN << MXC_F_DMA_CN_CH15_IEN_POS)

#define MXC_F_DMA_INTR_CH0_IPEND_POS                   0

#define MXC_F_DMA_INTR_CH0_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS))

#define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS)

#define MXC_V_DMA_INTR_CH0_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH0_IPEND_PENDING               (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS)

#define MXC_F_DMA_INTR_CH1_IPEND_POS                   1

#define MXC_F_DMA_INTR_CH1_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS))

#define MXC_V_DMA_INTR_CH1_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH1_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH1_IPEND_INACTIVE << MXC_F_DMA_INTR_CH1_IPEND_POS)

#define MXC_V_DMA_INTR_CH1_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH1_IPEND_PENDING               (MXC_V_DMA_INTR_CH1_IPEND_PENDING << MXC_F_DMA_INTR_CH1_IPEND_POS)

#define MXC_F_DMA_INTR_CH2_IPEND_POS                   2

#define MXC_F_DMA_INTR_CH2_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS))

#define MXC_V_DMA_INTR_CH2_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH2_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH2_IPEND_INACTIVE << MXC_F_DMA_INTR_CH2_IPEND_POS)

#define MXC_V_DMA_INTR_CH2_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH2_IPEND_PENDING               (MXC_V_DMA_INTR_CH2_IPEND_PENDING << MXC_F_DMA_INTR_CH2_IPEND_POS)

#define MXC_F_DMA_INTR_CH3_IPEND_POS                   3

#define MXC_F_DMA_INTR_CH3_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS))

#define MXC_V_DMA_INTR_CH3_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH3_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH3_IPEND_INACTIVE << MXC_F_DMA_INTR_CH3_IPEND_POS)

#define MXC_V_DMA_INTR_CH3_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH3_IPEND_PENDING               (MXC_V_DMA_INTR_CH3_IPEND_PENDING << MXC_F_DMA_INTR_CH3_IPEND_POS)

#define MXC_F_DMA_INTR_CH4_IPEND_POS                   4

#define MXC_F_DMA_INTR_CH4_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS))

#define MXC_V_DMA_INTR_CH4_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH4_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH4_IPEND_INACTIVE << MXC_F_DMA_INTR_CH4_IPEND_POS)

#define MXC_V_DMA_INTR_CH4_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH4_IPEND_PENDING               (MXC_V_DMA_INTR_CH4_IPEND_PENDING << MXC_F_DMA_INTR_CH4_IPEND_POS)

#define MXC_F_DMA_INTR_CH5_IPEND_POS                   5

#define MXC_F_DMA_INTR_CH5_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS))

#define MXC_V_DMA_INTR_CH5_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH5_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH5_IPEND_INACTIVE << MXC_F_DMA_INTR_CH5_IPEND_POS)

#define MXC_V_DMA_INTR_CH5_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH5_IPEND_PENDING               (MXC_V_DMA_INTR_CH5_IPEND_PENDING << MXC_F_DMA_INTR_CH5_IPEND_POS)

#define MXC_F_DMA_INTR_CH6_IPEND_POS                   6

#define MXC_F_DMA_INTR_CH6_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS))

#define MXC_V_DMA_INTR_CH6_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH6_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH6_IPEND_INACTIVE << MXC_F_DMA_INTR_CH6_IPEND_POS)

#define MXC_V_DMA_INTR_CH6_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH6_IPEND_PENDING               (MXC_V_DMA_INTR_CH6_IPEND_PENDING << MXC_F_DMA_INTR_CH6_IPEND_POS)

#define MXC_F_DMA_INTR_CH7_IPEND_POS                   7

#define MXC_F_DMA_INTR_CH7_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS))

#define MXC_V_DMA_INTR_CH7_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH7_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH7_IPEND_INACTIVE << MXC_F_DMA_INTR_CH7_IPEND_POS)

#define MXC_V_DMA_INTR_CH7_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH7_IPEND_PENDING               (MXC_V_DMA_INTR_CH7_IPEND_PENDING << MXC_F_DMA_INTR_CH7_IPEND_POS)

#define MXC_F_DMA_INTR_CH8_IPEND_POS                   8

#define MXC_F_DMA_INTR_CH8_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH8_IPEND_POS))

#define MXC_V_DMA_INTR_CH8_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH8_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH8_IPEND_INACTIVE << MXC_F_DMA_INTR_CH8_IPEND_POS)

#define MXC_V_DMA_INTR_CH8_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH8_IPEND_PENDING               (MXC_V_DMA_INTR_CH8_IPEND_PENDING << MXC_F_DMA_INTR_CH8_IPEND_POS)

#define MXC_F_DMA_INTR_CH9_IPEND_POS                   9

#define MXC_F_DMA_INTR_CH9_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH9_IPEND_POS))

#define MXC_V_DMA_INTR_CH9_IPEND_INACTIVE              ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH9_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH9_IPEND_INACTIVE << MXC_F_DMA_INTR_CH9_IPEND_POS)

#define MXC_V_DMA_INTR_CH9_IPEND_PENDING               ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH9_IPEND_PENDING               (MXC_V_DMA_INTR_CH9_IPEND_PENDING << MXC_F_DMA_INTR_CH9_IPEND_POS)

#define MXC_F_DMA_INTR_CH10_IPEND_POS                  10

#define MXC_F_DMA_INTR_CH10_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH10_IPEND_POS))

#define MXC_V_DMA_INTR_CH10_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH10_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH10_IPEND_INACTIVE << MXC_F_DMA_INTR_CH10_IPEND_POS)

#define MXC_V_DMA_INTR_CH10_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH10_IPEND_PENDING              (MXC_V_DMA_INTR_CH10_IPEND_PENDING << MXC_F_DMA_INTR_CH10_IPEND_POS)

#define MXC_F_DMA_INTR_CH11_IPEND_POS                  11

#define MXC_F_DMA_INTR_CH11_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH11_IPEND_POS))

#define MXC_V_DMA_INTR_CH11_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH11_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH11_IPEND_INACTIVE << MXC_F_DMA_INTR_CH11_IPEND_POS)

#define MXC_V_DMA_INTR_CH11_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH11_IPEND_PENDING              (MXC_V_DMA_INTR_CH11_IPEND_PENDING << MXC_F_DMA_INTR_CH11_IPEND_POS)

#define MXC_F_DMA_INTR_CH12_IPEND_POS                  12

#define MXC_F_DMA_INTR_CH12_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH12_IPEND_POS))

#define MXC_V_DMA_INTR_CH12_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH12_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH12_IPEND_INACTIVE << MXC_F_DMA_INTR_CH12_IPEND_POS)

#define MXC_V_DMA_INTR_CH12_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH12_IPEND_PENDING              (MXC_V_DMA_INTR_CH12_IPEND_PENDING << MXC_F_DMA_INTR_CH12_IPEND_POS)

#define MXC_F_DMA_INTR_CH13_IPEND_POS                  13

#define MXC_F_DMA_INTR_CH13_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH13_IPEND_POS))

#define MXC_V_DMA_INTR_CH13_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH13_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH13_IPEND_INACTIVE << MXC_F_DMA_INTR_CH13_IPEND_POS)

#define MXC_V_DMA_INTR_CH13_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH13_IPEND_PENDING              (MXC_V_DMA_INTR_CH13_IPEND_PENDING << MXC_F_DMA_INTR_CH13_IPEND_POS)

#define MXC_F_DMA_INTR_CH14_IPEND_POS                  14

#define MXC_F_DMA_INTR_CH14_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH14_IPEND_POS))

#define MXC_V_DMA_INTR_CH14_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH14_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH14_IPEND_INACTIVE << MXC_F_DMA_INTR_CH14_IPEND_POS)

#define MXC_V_DMA_INTR_CH14_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH14_IPEND_PENDING              (MXC_V_DMA_INTR_CH14_IPEND_PENDING << MXC_F_DMA_INTR_CH14_IPEND_POS)

#define MXC_F_DMA_INTR_CH15_IPEND_POS                  15

#define MXC_F_DMA_INTR_CH15_IPEND                      ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH15_IPEND_POS))

#define MXC_V_DMA_INTR_CH15_IPEND_INACTIVE             ((uint32_t)0x0UL)

#define MXC_S_DMA_INTR_CH15_IPEND_INACTIVE             (MXC_V_DMA_INTR_CH15_IPEND_INACTIVE << MXC_F_DMA_INTR_CH15_IPEND_POS)

#define MXC_V_DMA_INTR_CH15_IPEND_PENDING              ((uint32_t)0x1UL)

#define MXC_S_DMA_INTR_CH15_IPEND_PENDING              (MXC_V_DMA_INTR_CH15_IPEND_PENDING << MXC_F_DMA_INTR_CH15_IPEND_POS)

#define MXC_F_DMA_CFG_CHEN_POS                         0

#define MXC_F_DMA_CFG_CHEN                             ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS))

#define MXC_V_DMA_CFG_CHEN_DIS                         ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_CHEN_DIS                         (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS)

#define MXC_V_DMA_CFG_CHEN_EN                          ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_CHEN_EN                          (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS)

#define MXC_F_DMA_CFG_RLDEN_POS                        1

#define MXC_F_DMA_CFG_RLDEN                            ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS))

#define MXC_V_DMA_CFG_RLDEN_DIS                        ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_RLDEN_DIS                        (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS)

#define MXC_V_DMA_CFG_RLDEN_EN                         ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_RLDEN_EN                         (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS)

#define MXC_F_DMA_CFG_PRI_POS                          2

#define MXC_F_DMA_CFG_PRI                              ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS))

#define MXC_V_DMA_CFG_PRI_HIGH                         ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_PRI_HIGH                         (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS)

#define MXC_V_DMA_CFG_PRI_MEDHIGH                      ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_PRI_MEDHIGH                      (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS)

#define MXC_V_DMA_CFG_PRI_MEDLOW                       ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_PRI_MEDLOW                       (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS)

#define MXC_V_DMA_CFG_PRI_LOW                          ((uint32_t)0x3UL)

#define MXC_S_DMA_CFG_PRI_LOW                          (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS)

#define MXC_F_DMA_CFG_REQSEL_POS                       4

#define MXC_F_DMA_CFG_REQSEL                           ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS))

#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM                  ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM                  (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI0RX                    ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_REQSEL_SPI0RX                    (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI1RX                    ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_REQSEL_SPI1RX                    (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI2RX                    ((uint32_t)0x3UL)

#define MXC_S_DMA_CFG_REQSEL_SPI2RX                    (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART0RX                   ((uint32_t)0x4UL)

#define MXC_S_DMA_CFG_REQSEL_UART0RX                   (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART1RX                   ((uint32_t)0x5UL)

#define MXC_S_DMA_CFG_REQSEL_UART1RX                   (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_I2C0RX                    ((uint32_t)0x7UL)

#define MXC_S_DMA_CFG_REQSEL_I2C0RX                    (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_I2C1RX                    ((uint32_t)0x8UL)

#define MXC_S_DMA_CFG_REQSEL_I2C1RX                    (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_ADC                       ((uint32_t)0x9UL)

#define MXC_S_DMA_CFG_REQSEL_ADC                       (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART2RX                   ((uint32_t)0xEUL)

#define MXC_S_DMA_CFG_REQSEL_UART2RX                   (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI3RX                    ((uint32_t)0xFUL)

#define MXC_S_DMA_CFG_REQSEL_SPI3RX                    (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPIMSSRX                  ((uint32_t)0x10UL)

#define MXC_S_DMA_CFG_REQSEL_SPIMSSRX                  (MXC_V_DMA_CFG_REQSEL_SPIMSSRX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP1                  ((uint32_t)0x11UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP1                  (MXC_V_DMA_CFG_REQSEL_USBRXEP1 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP2                  ((uint32_t)0x12UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP2                  (MXC_V_DMA_CFG_REQSEL_USBRXEP2 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP3                  ((uint32_t)0x13UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP3                  (MXC_V_DMA_CFG_REQSEL_USBRXEP3 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP4                  ((uint32_t)0x14UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP4                  (MXC_V_DMA_CFG_REQSEL_USBRXEP4 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP5                  ((uint32_t)0x15UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP5                  (MXC_V_DMA_CFG_REQSEL_USBRXEP5 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP6                  ((uint32_t)0x16UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP6                  (MXC_V_DMA_CFG_REQSEL_USBRXEP6 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP7                  ((uint32_t)0x17UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP7                  (MXC_V_DMA_CFG_REQSEL_USBRXEP7 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP8                  ((uint32_t)0x18UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP8                  (MXC_V_DMA_CFG_REQSEL_USBRXEP8 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP9                  ((uint32_t)0x19UL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP9                  (MXC_V_DMA_CFG_REQSEL_USBRXEP9 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP10                 ((uint32_t)0x1AUL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP10                 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBRXEP11                 ((uint32_t)0x1BUL)

#define MXC_S_DMA_CFG_REQSEL_USBRXEP11                 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI0TX                    ((uint32_t)0x21UL)

#define MXC_S_DMA_CFG_REQSEL_SPI0TX                    (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI1TX                    ((uint32_t)0x22UL)

#define MXC_S_DMA_CFG_REQSEL_SPI1TX                    (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI2TX                    ((uint32_t)0x23UL)

#define MXC_S_DMA_CFG_REQSEL_SPI2TX                    (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART0TX                   ((uint32_t)0x24UL)

#define MXC_S_DMA_CFG_REQSEL_UART0TX                   (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART1TX                   ((uint32_t)0x25UL)

#define MXC_S_DMA_CFG_REQSEL_UART1TX                   (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_I2C0TX                    ((uint32_t)0x27UL)

#define MXC_S_DMA_CFG_REQSEL_I2C0TX                    (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_I2C1TX                    ((uint32_t)0x28UL)

#define MXC_S_DMA_CFG_REQSEL_I2C1TX                    (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_UART2TX                   ((uint32_t)0x2EUL)

#define MXC_S_DMA_CFG_REQSEL_UART2TX                   (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPI3TX                    ((uint32_t)0x2FUL)

#define MXC_S_DMA_CFG_REQSEL_SPI3TX                    (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_SPIMSSTX                  ((uint32_t)0x30UL)

#define MXC_S_DMA_CFG_REQSEL_SPIMSSTX                  (MXC_V_DMA_CFG_REQSEL_SPIMSSTX << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP1                  ((uint32_t)0x31UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP1                  (MXC_V_DMA_CFG_REQSEL_USBTXEP1 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP2                  ((uint32_t)0x32UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP2                  (MXC_V_DMA_CFG_REQSEL_USBTXEP2 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP3                  ((uint32_t)0x33UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP3                  (MXC_V_DMA_CFG_REQSEL_USBTXEP3 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP4                  ((uint32_t)0x34UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP4                  (MXC_V_DMA_CFG_REQSEL_USBTXEP4 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP5                  ((uint32_t)0x35UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP5                  (MXC_V_DMA_CFG_REQSEL_USBTXEP5 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP6                  ((uint32_t)0x36UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP6                  (MXC_V_DMA_CFG_REQSEL_USBTXEP6 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP7                  ((uint32_t)0x37UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP7                  (MXC_V_DMA_CFG_REQSEL_USBTXEP7 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP8                  ((uint32_t)0x38UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP8                  (MXC_V_DMA_CFG_REQSEL_USBTXEP8 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP9                  ((uint32_t)0x39UL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP9                  (MXC_V_DMA_CFG_REQSEL_USBTXEP9 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP10                 ((uint32_t)0x3AUL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP10                 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_V_DMA_CFG_REQSEL_USBTXEP11                 ((uint32_t)0x3BUL)

#define MXC_S_DMA_CFG_REQSEL_USBTXEP11                 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 << MXC_F_DMA_CFG_REQSEL_POS)

#define MXC_F_DMA_CFG_REQWAIT_POS                      10

#define MXC_F_DMA_CFG_REQWAIT                          ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS))

#define MXC_V_DMA_CFG_REQWAIT_NORMAL                   ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_REQWAIT_NORMAL                   (MXC_V_DMA_CFG_REQWAIT_NORMAL << MXC_F_DMA_CFG_REQWAIT_POS)

#define MXC_V_DMA_CFG_REQWAIT_DELAY                    ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_REQWAIT_DELAY                    (MXC_V_DMA_CFG_REQWAIT_DELAY << MXC_F_DMA_CFG_REQWAIT_POS)

#define MXC_F_DMA_CFG_TOSEL_POS                        11

#define MXC_F_DMA_CFG_TOSEL                            ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS))

#define MXC_V_DMA_CFG_TOSEL_TO4                        ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_TOSEL_TO4                        (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO8                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_TOSEL_TO8                        (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO16                       ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_TOSEL_TO16                       (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO32                       ((uint32_t)0x3UL)

#define MXC_S_DMA_CFG_TOSEL_TO32                       (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO64                       ((uint32_t)0x4UL)

#define MXC_S_DMA_CFG_TOSEL_TO64                       (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO128                      ((uint32_t)0x5UL)

#define MXC_S_DMA_CFG_TOSEL_TO128                      (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO256                      ((uint32_t)0x6UL)

#define MXC_S_DMA_CFG_TOSEL_TO256                      (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_V_DMA_CFG_TOSEL_TO512                      ((uint32_t)0x7UL)

#define MXC_S_DMA_CFG_TOSEL_TO512                      (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS)

#define MXC_F_DMA_CFG_PSSEL_POS                        14

#define MXC_F_DMA_CFG_PSSEL                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS))

#define MXC_V_DMA_CFG_PSSEL_DIS                        ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_PSSEL_DIS                        (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS)

#define MXC_V_DMA_CFG_PSSEL_DIV256                     ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_PSSEL_DIV256                     (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS)

#define MXC_V_DMA_CFG_PSSEL_DIV64K                     ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_PSSEL_DIV64K                     (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS)

#define MXC_V_DMA_CFG_PSSEL_DIV16M                     ((uint32_t)0x3UL)

#define MXC_S_DMA_CFG_PSSEL_DIV16M                     (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS)

#define MXC_F_DMA_CFG_SRCWD_POS                        16

#define MXC_F_DMA_CFG_SRCWD                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS))

#define MXC_V_DMA_CFG_SRCWD_BYTE                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_SRCWD_BYTE                       (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS)

#define MXC_V_DMA_CFG_SRCWD_HALFWORD                   ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_SRCWD_HALFWORD                   (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS)

#define MXC_V_DMA_CFG_SRCWD_WORD                       ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_SRCWD_WORD                       (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS)

#define MXC_F_DMA_CFG_SRINC_POS                        18

#define MXC_F_DMA_CFG_SRINC                            ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRINC_POS))

#define MXC_V_DMA_CFG_SRINC_DIS                        ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_SRINC_DIS                        (MXC_V_DMA_CFG_SRINC_DIS << MXC_F_DMA_CFG_SRINC_POS)

#define MXC_V_DMA_CFG_SRINC_EN                         ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_SRINC_EN                         (MXC_V_DMA_CFG_SRINC_EN << MXC_F_DMA_CFG_SRINC_POS)

#define MXC_F_DMA_CFG_DSTWD_POS                        20

#define MXC_F_DMA_CFG_DSTWD                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS))

#define MXC_V_DMA_CFG_DSTWD_BYTE                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_DSTWD_BYTE                       (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS)

#define MXC_V_DMA_CFG_DSTWD_HALFWORD                   ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_DSTWD_HALFWORD                   (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS)

#define MXC_V_DMA_CFG_DSTWD_WORD                       ((uint32_t)0x2UL)

#define MXC_S_DMA_CFG_DSTWD_WORD                       (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS)

#define MXC_F_DMA_CFG_DSTINC_POS                       22

#define MXC_F_DMA_CFG_DSTINC                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS))

#define MXC_V_DMA_CFG_DSTINC_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_DSTINC_DIS                       (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS)

#define MXC_V_DMA_CFG_DSTINC_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_DSTINC_EN                        (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS)

#define MXC_F_DMA_CFG_BRST_POS                         24

#define MXC_F_DMA_CFG_BRST                             ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS))

#define MXC_F_DMA_CFG_CHDIEN_POS                       30

#define MXC_F_DMA_CFG_CHDIEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS))

#define MXC_V_DMA_CFG_CHDIEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_CHDIEN_DIS                       (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS)

#define MXC_V_DMA_CFG_CHDIEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_CHDIEN_EN                        (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS)

#define MXC_F_DMA_CFG_CTZIEN_POS                       31

#define MXC_F_DMA_CFG_CTZIEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS))

#define MXC_V_DMA_CFG_CTZIEN_DIS                       ((uint32_t)0x0UL)

#define MXC_S_DMA_CFG_CTZIEN_DIS                       (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS)

#define MXC_V_DMA_CFG_CTZIEN_EN                        ((uint32_t)0x1UL)

#define MXC_S_DMA_CFG_CTZIEN_EN                        (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS)

#define MXC_F_DMA_ST_CH_ST_POS                         0

#define MXC_F_DMA_ST_CH_ST                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS))

#define MXC_V_DMA_ST_CH_ST_DISABLED                    ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_CH_ST_DISABLED                    (MXC_V_DMA_ST_CH_ST_DISABLED << MXC_F_DMA_ST_CH_ST_POS)

#define MXC_V_DMA_ST_CH_ST_ENABLED                     ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_CH_ST_ENABLED                     (MXC_V_DMA_ST_CH_ST_ENABLED << MXC_F_DMA_ST_CH_ST_POS)

#define MXC_F_DMA_ST_IPEND_POS                         1

#define MXC_F_DMA_ST_IPEND                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS))

#define MXC_V_DMA_ST_IPEND_INACTIVE                    ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_IPEND_INACTIVE                    (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS)

#define MXC_V_DMA_ST_IPEND_PENDING                     ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_IPEND_PENDING                     (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS)

#define MXC_F_DMA_ST_CTZ_ST_POS                        2

#define MXC_F_DMA_ST_CTZ_ST                            ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS))

#define MXC_V_DMA_ST_CTZ_ST_NOEVENT                    ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_CTZ_ST_NOEVENT                    (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS)

#define MXC_V_DMA_ST_CTZ_ST_CTZ_OCCUR                  ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_CTZ_ST_CTZ_OCCUR                  (MXC_V_DMA_ST_CTZ_ST_CTZ_OCCUR << MXC_F_DMA_ST_CTZ_ST_POS)

#define MXC_V_DMA_ST_CTZ_ST_CLEAR                      ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_CTZ_ST_CLEAR                      (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS)

#define MXC_F_DMA_ST_RLD_ST_POS                        3

#define MXC_F_DMA_ST_RLD_ST                            ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS))

#define MXC_V_DMA_ST_RLD_ST_NOEVENT                    ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_RLD_ST_NOEVENT                    (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS)

#define MXC_V_DMA_ST_RLD_ST_RELOADED                   ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_RLD_ST_RELOADED                   (MXC_V_DMA_ST_RLD_ST_RELOADED << MXC_F_DMA_ST_RLD_ST_POS)

#define MXC_V_DMA_ST_RLD_ST_CLEAR                      ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_RLD_ST_CLEAR                      (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS)

#define MXC_F_DMA_ST_BUS_ERR_POS                       4

#define MXC_F_DMA_ST_BUS_ERR                           ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS))

#define MXC_V_DMA_ST_BUS_ERR_NOEVENT                   ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_BUS_ERR_NOEVENT                   (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS)

#define MXC_V_DMA_ST_BUS_ERR_BUS_ERR                   ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_BUS_ERR_BUS_ERR                   (MXC_V_DMA_ST_BUS_ERR_BUS_ERR << MXC_F_DMA_ST_BUS_ERR_POS)

#define MXC_V_DMA_ST_BUS_ERR_CLEAR                     ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_BUS_ERR_CLEAR                     (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS)

#define MXC_F_DMA_ST_TO_ST_POS                         6

#define MXC_F_DMA_ST_TO_ST                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS))

#define MXC_V_DMA_ST_TO_ST_NOEVENT                     ((uint32_t)0x0UL)

#define MXC_S_DMA_ST_TO_ST_NOEVENT                     (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS)

#define MXC_V_DMA_ST_TO_ST_EXPIRED                     ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_TO_ST_EXPIRED                     (MXC_V_DMA_ST_TO_ST_EXPIRED << MXC_F_DMA_ST_TO_ST_POS)

#define MXC_V_DMA_ST_TO_ST_CLEAR                       ((uint32_t)0x1UL)

#define MXC_S_DMA_ST_TO_ST_CLEAR                       (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS)

#define MXC_F_DMA_SRC_ADDR_POS                         0

#define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))

#define MXC_F_DMA_DST_ADDR_POS                         0

#define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS))

#define MXC_F_DMA_CNT_CNT_POS                          0

#define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS))

#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS                  0

#define MXC_F_DMA_SRC_RLD_SRC_RLD                      ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS))

#define MXC_F_DMA_DST_RLD_DST_RLD_POS                  0

#define MXC_F_DMA_DST_RLD_DST_RLD                      ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS))

#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS                  0

#define MXC_F_DMA_CNT_RLD_CNT_RLD                      ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS))

#define MXC_F_DMA_CNT_RLD_RLDEN_POS                    31

#define MXC_F_DMA_CNT_RLD_RLDEN                        ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS))

#define MXC_V_DMA_CNT_RLD_RLDEN_DIS                    ((uint32_t)0x0UL)

#define MXC_S_DMA_CNT_RLD_RLDEN_DIS                    (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS)

#define MXC_V_DMA_CNT_RLD_RLDEN_EN                     ((uint32_t)0x1UL)

#define MXC_S_DMA_CNT_RLD_RLDEN_EN                     (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS)

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_DMA_REGS_H_

mxc_dma_ch_regs_t::dst
__IO uint32_t dst
Definition: dma_regs.h:80

mxc_dma_ch_regs_t::cfg
__IO uint32_t cfg
Definition: dma_regs.h:77

mxc_dma_ch_regs_t::src
__IO uint32_t src
Definition: dma_regs.h:79

mxc_dma_ch_regs_t::cnt
__IO uint32_t cnt
Definition: dma_regs.h:81

mxc_dma_ch_regs_t::src_rld
__IO uint32_t src_rld
Definition: dma_regs.h:82

mxc_dma_ch_regs_t::cnt_rld
__IO uint32_t cnt_rld
Definition: dma_regs.h:84

mxc_dma_ch_regs_t::dst_rld
__IO uint32_t dst_rld
Definition: dma_regs.h:83

mxc_dma_ch_regs_t::st
__IO uint32_t st
Definition: dma_regs.h:78

mxc_dma_ch_regs_t
Definition: dma_regs.h:76