GCR_RST1

Macros
#define	MXC_F_GCR_RST1_I2C1_POS   0
#define	MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
#define	MXC_F_GCR_RST1_PT_POS   1
#define	MXC_F_GCR_RST1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))
#define	MXC_F_GCR_RST1_SPIXIP_POS   3
#define	MXC_F_GCR_RST1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS))
#define	MXC_F_GCR_RST1_XSPIM_POS   4
#define	MXC_F_GCR_RST1_XSPIM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS))
#define	MXC_F_GCR_RST1_GPIO3_POS   5
#define	MXC_F_GCR_RST1_GPIO3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_GPIO3_POS))
#define	MXC_F_GCR_RST1_SDHC_POS   6
#define	MXC_F_GCR_RST1_SDHC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS))
#define	MXC_F_GCR_RST1_OWIRE_POS   7
#define	MXC_F_GCR_RST1_OWIRE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS))
#define	MXC_F_GCR_RST1_WDT1_POS   8
#define	MXC_F_GCR_RST1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))
#define	MXC_F_GCR_RST1_SPI3_POS   9
#define	MXC_F_GCR_RST1_SPI3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS))
#define	MXC_F_GCR_RST1_I2S_POS   10
#define	MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))
#define	MXC_F_GCR_RST1_XIPR_POS   15
#define	MXC_F_GCR_RST1_XIPR   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS))
#define	MXC_F_GCR_RST1_SEMA_POS   16
#define	MXC_F_GCR_RST1_SEMA   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS))

Detailed Description

Reset 1.

Macro Definition Documentation

MXC_F_GCR_RST1_GPIO3

#define MXC_F_GCR_RST1_GPIO3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_GPIO3_POS))

RST1_GPIO3 Mask

MXC_F_GCR_RST1_GPIO3_POS

#define MXC_F_GCR_RST1_GPIO3_POS   5

RST1_GPIO3 Position

MXC_F_GCR_RST1_I2C1

#define MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))

RST1_I2C1 Mask

MXC_F_GCR_RST1_I2C1_POS

#define MXC_F_GCR_RST1_I2C1_POS   0

RST1_I2C1 Position

MXC_F_GCR_RST1_I2S

#define MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))

RST1_I2S Mask

MXC_F_GCR_RST1_I2S_POS

#define MXC_F_GCR_RST1_I2S_POS   10

RST1_I2S Position

MXC_F_GCR_RST1_OWIRE

#define MXC_F_GCR_RST1_OWIRE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS))

RST1_OWIRE Mask

MXC_F_GCR_RST1_OWIRE_POS

#define MXC_F_GCR_RST1_OWIRE_POS   7

RST1_OWIRE Position

MXC_F_GCR_RST1_PT

#define MXC_F_GCR_RST1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))

RST1_PT Mask

MXC_F_GCR_RST1_PT_POS

#define MXC_F_GCR_RST1_PT_POS   1

RST1_PT Position

MXC_F_GCR_RST1_SDHC

#define MXC_F_GCR_RST1_SDHC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS))

RST1_SDHC Mask

MXC_F_GCR_RST1_SDHC_POS

#define MXC_F_GCR_RST1_SDHC_POS   6

RST1_SDHC Position

MXC_F_GCR_RST1_SEMA

#define MXC_F_GCR_RST1_SEMA   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS))

RST1_SEMA Mask

MXC_F_GCR_RST1_SEMA_POS

#define MXC_F_GCR_RST1_SEMA_POS   16

RST1_SEMA Position

MXC_F_GCR_RST1_SPI3

#define MXC_F_GCR_RST1_SPI3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS))

RST1_SPI3 Mask

MXC_F_GCR_RST1_SPI3_POS

#define MXC_F_GCR_RST1_SPI3_POS   9

RST1_SPI3 Position

MXC_F_GCR_RST1_SPIXIP

#define MXC_F_GCR_RST1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS))

RST1_SPIXIP Mask

MXC_F_GCR_RST1_SPIXIP_POS

#define MXC_F_GCR_RST1_SPIXIP_POS   3

RST1_SPIXIP Position

MXC_F_GCR_RST1_WDT1

#define MXC_F_GCR_RST1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))

RST1_WDT1 Mask

MXC_F_GCR_RST1_WDT1_POS

#define MXC_F_GCR_RST1_WDT1_POS   8

RST1_WDT1 Position

MXC_F_GCR_RST1_XIPR

#define MXC_F_GCR_RST1_XIPR   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS))

RST1_XIPR Mask

MXC_F_GCR_RST1_XIPR_POS

#define MXC_F_GCR_RST1_XIPR_POS   15

RST1_XIPR Position

MXC_F_GCR_RST1_XSPIM

#define MXC_F_GCR_RST1_XSPIM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS))

RST1_XSPIM Mask

MXC_F_GCR_RST1_XSPIM_POS

#define MXC_F_GCR_RST1_XSPIM_POS   4

RST1_XSPIM Position