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MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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| ►Analog Digital Converter (ADC) | |
| ►ADC_Registers | Registers, Bit Masks and Bit Positions for the ADC Peripheral Module |
| Register Offsets | ADC Peripheral Register Offsets from the ADC Base Peripheral Address |
| ADC_CTRL | ADC Control |
| ADC_STATUS | ADC Status |
| ADC_DATA | ADC Output Data |
| ADC_INTR | ADC Interrupt Control Register |
| ADC_LIMIT | ADC Limit |
| ►Color LCD (CLCD) | |
| ►CLCD_Registers | Registers, Bit Masks and Bit Positions for the CLCD Peripheral Module |
| Register Offsets | CLCD Peripheral Register Offsets from the CLCD Base Peripheral Address |
| CLCD_CLK_CTRL | LCD Clock Control Register |
| CLCD_VTIM_0 | LCD Vertical Timing 0 Register |
| CLCD_VTIM_1 | LCD Vertical Timing 1 Register |
| CLCD_HTIM | LCD Horizontal Timing Register |
| CLCD_CTRL | LCD Control Register |
| CLCD_FRBUF | Frame buffer |
| CLCD_INT_EN | LCD Interrupt Enable Register |
| CLCD_INT_STAT | LCD Status Register |
| CLCD_PALETTE_RAM | Palette |
| ►Direct Memory Access (DMA) | |
| ►DMA_Registers | Registers, Bit Masks and Bit Positions for the DMA Peripheral Module |
| Register Offsets | DMA Peripheral Register Offsets from the DMA Base Peripheral Address |
| DMA_CN | DMA Control Register |
| DMA_INTR | DMA Interrupt Register |
| DMA_CFG | DMA Channel Configuration Register |
| DMA_ST | DMA Channel Status Register |
| DMA_SRC | Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD |
| DMA_DST | Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD |
| DMA_CNT | DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered |
| DMA_SRC_RLD | Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition |
| DMA_DST_RLD | Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition |
| DMA_CNT_RLD | DMA Channel Count Reload Register |
| ►External Memory Cache Controller (EMCC) | |
| ►EMCC_Registers | Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module |
| Register Offsets | EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address |
| EMCC_CACHE_ID | Cache ID Register |
| EMCC_MEM_SIZE | Memory Configuration Register |
| EMCC_CACHE_CTRL | Cache Control and Status Register |
| EMCC_INVALIDATE | Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0 |
| ►Flash Controller | |
| ►FLC_Registers | Registers, Bit Masks and Bit Positions for the FLC Peripheral Module |
| Register Offsets | FLC Peripheral Register Offsets from the FLC Base Peripheral Address |
| FLC_ADDR | Flash Write Address |
| FLC_CLKDIV | Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller |
| FLC_CTRL | Flash Control Register |
| FLC_INTR | Flash Interrupt Register |
| FLC_DATA | Flash Write Data |
| FLC_ACTNL | Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero |
| ►General-Purpose Input/Output (GPIO) | |
| ►Port and Pin Definitions | |
| Port Definitions | |
| Pin Definitions | |
| ►GPIO_Registers | Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module |
| Register Offsets | GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address |
| GPIO_EN | GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port |
| GPIO_EN_SET | GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register |
| GPIO_EN_CLR | GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register |
| GPIO_OUT_EN | GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port |
| GPIO_OUT_EN_SET | GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register |
| GPIO_OUT_EN_CLR | GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register |
| GPIO_OUT | GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers |
| GPIO_OUT_SET | GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register |
| GPIO_OUT_CLR | GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register |
| GPIO_IN | GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port |
| GPIO_INT_MODE | GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port |
| GPIO_INT_POL | GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port |
| GPIO_IN_EN | GPIO Port Input Enable |
| GPIO_INT_EN | GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port |
| GPIO_INT_EN_SET | GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register |
| GPIO_INT_EN_CLR | GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register |
| GPIO_INT_STAT | GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port |
| GPIO_INT_CLR | GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register |
| GPIO_WAKE_EN | GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port |
| GPIO_WAKE_EN_SET | GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register |
| GPIO_WAKE_EN_CLR | GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register |
| GPIO_INT_DUAL_EDGE | GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port |
| GPIO_PDPU_SEL0 | GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port |
| GPIO_PDPU_SEL1 | GPIO Input Mode Config 2. Each bit in this register enables the pull-down for the associated GPIO pin in this port |
| GPIO_AF_SEL | GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port |
| GPIO_AF_SEL_SET | GPIO Alternate Function Selectset. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register |
| GPIO_AF_SEL_CLR | GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register |
| GPIO_DS_SEL0 | GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers |
| GPIO_DS_SEL1 | GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers |
| GPIO_PSSEL | GPIO Pull Select Mode |
| GPIO_VSSEL | GPIO Voltage Select |
| ►HyperBus (HPB) | |
| ►HPB_Registers | Registers, Bit Masks and Bit Positions for the HPB Peripheral Module |
| Register Offsets | HPB Peripheral Register Offsets from the HPB Base Peripheral Address |
| HPB_STATUS | HPB Status Register |
| HPB_INTEN | HPB Interrupt Enable |
| HPB_INTFL | HPB Interrupt Status Flags |
| HPB_MBR | HPB Memory Base Address |
| HPB_MCR | HPB Memory Configuration Register |
| HPB_MTR | HPB Memory Timing Register |
| ►I2C | |
| ►I2C_Registers | Registers, Bit Masks and Bit Positions for the I2C Peripheral Module |
| Register Offsets | I2C Peripheral Register Offsets from the I2C Base Peripheral Address |
| I2C_CTRL0 | Control Register 0 |
| I2C_STAT | Status Register |
| I2C_INT_FL0 | Interrupt Status Register |
| I2C_INT_EN0 | Interrupt Enable Register |
| I2C_INT_FL1 | Interrupt Status Register 1 |
| I2C_INT_EN1 | Interrupt Staus Register 1 |
| I2C_FIFO_LEN | FIFO Configuration Register |
| I2C_RX_CTRL0 | Receive Control Register 0 |
| I2C_RX_CTRL1 | Receive Control Register 1 |
| I2C_TX_CTRL0 | Transmit Control Register 0 |
| I2C_TX_CTRL1 | Transmit Control Register 1 |
| I2C_FIFO | Data Register |
| I2C_MSTR_MODE | Master Control Register |
| I2C_CLK_LO | Clock Low Register |
| I2C_CLK_HI | Clock high Register |
| I2C_TIMEOUT | Timeout Register |
| I2C_SLV_ADDR | Slave Address Register |
| I2C_DMA | DMA Register |
| ►SPIMSS | |
| ►SPIMSS_Registers | Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module |
| Register Offsets | SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address |
| SPIMSS_DATA | SPI 16-bit Data Access |
| SPIMSS_CTRL | SPI Control Register |
| SPIMSS_INT_FL | SPI Interrupt Flag Register |
| SPIMSS_MOD | SPI Mode Register |
| SPIMSS_BRG | Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4) |
| SPIMSS_DMA | SPI DMA Register |
| SPIMSS_I2S_CTRL | I2S Control Register |
| ►Internal Cache Controller (ICC) | |
| ►ICC_Registers | Registers, Bit Masks and Bit Positions for the ICC Peripheral Module |
| Register Offsets | ICC Peripheral Register Offsets from the ICC Base Peripheral Address |
| ICC_CACHE_ID | Cache ID Register |
| ICC_MEM_SIZE | Memory Configuration Register |
| ICC_CACHE_CTRL | Cache Control and Status Register |
| ICC_INVALIDATE | Invalidate All Registers |
| ►Low Power (LP) | |
| ►PWRSEQ_Registers | Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module |
| Register Offsets | PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address |
| PWRSEQ_CTRL | Low Power Control Register |
| PWRSEQ_GPIO0_WK_FL | Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0 |
| PWRSEQ_GPIO0_WK_EN | Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0 |
| PWRSEQ_GPIO1_WK_FL | Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1 |
| PWRSEQ_GPIO1_WK_EN | Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1 |
| PWRSEQ_GPIO2_WK_FL | Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO2 |
| PWRSEQ_GPIO2_WK_EN | Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0 |
| PWRSEQ_GPIO3_WK_FL | Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO3 |
| PWRSEQ_GPIO3_WK_EN | Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO3 |
| PWRSEQ_USB_WK_FL | Low Power Peripheral Wakeup Status Register |
| PWRSEQ_USB_WK_EN | Low Power Peripheral Wakeup Enable Register |
| PWRSEQ_MEM_PWR | Low Power Memory Shutdown Control |
| Memory Utility Functions | |
| Assertion Checks for Debugging | Assertion checks for debugging |
| Delay Utility Functions | Asynchronous delay routines based on the SysTick Timer |
| Error Codes | A list of common error codes used by the API |
| Exclusive Access Locks | Lock functions to obtain and release a variable for exclusive access. These functions are marked interrupt safe if they are interrupt safe |
| System Configuration (MXC_SYS) | |
| NVIC Table | Functions handling the nvic table |
| ►1-Wire Master (OWM) | |
| ►OWM_Registers | Registers, Bit Masks and Bit Positions for the OWM Peripheral Module |
| Register Offsets | OWM Peripheral Register Offsets from the OWM Base Peripheral Address |
| OWM_CFG | 1-Wire Master Configuration |
| OWM_CLK_DIV_1US | 1-Wire Master Clock Divisor |
| OWM_CTRL_STAT | 1-Wire Master Control/Status |
| OWM_DATA | 1-Wire Master Data Buffer |
| OWM_INTFL | 1-Wire Master Interrupt Flags |
| OWM_INTEN | 1-Wire Master Interrupt Enables |
| ►Pulse Train Engine | This is the high level API for the pulse train engine |
| ►PT_Registers | Registers, Bit Masks and Bit Positions for the PT Peripheral Module |
| Register Offsets | PT Peripheral Register Offsets from the PT Base Peripheral Address |
| PT_RATE_LENGTH | Pulse Train Configuration |
| PT_LOOP | Pulse Train Loop Count |
| PT_RESTART | Pulse Train Auto-Restart Configuration |
| ►RTC | |
| ►RTC_Registers | Registers, Bit Masks and Bit Positions for the RTC Peripheral Module |
| Register Offsets | RTC Peripheral Register Offsets from the RTC Base Peripheral Address |
| RTC_SEC | RTC Second Counter. This register contains the 32-bit second counter |
| RTC_SSEC | RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00 |
| RTC_TODA | Time-of-day Alarm |
| RTC_SSECA | RTC sub-second alarm. This register contains the reload value for the sub- second alarm |
| RTC_CTRL | RTC Control Register |
| RTC_OSCCTRL | RTC Oscillator Control Register |
| ►Secure Digital High Capacity(SDHC) | |
| ►SDHC_Registers | Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module |
| Register Offsets | SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address |
| SDHC_SDMA | SDMA System Address / Argument 2 |
| SDHC_BLK_SIZE | Block Size |
| SDHC_BLK_CNT | Block Count |
| SDHC_ARG_1 | Argument 1 |
| SDHC_TRANS | Transfer Mode |
| SDHC_CMD | Command |
| SDHC_RESP | Response 0 Register 0-15 |
| SDHC_BUFFER | Buffer Data Port |
| SDHC_PRESENT | Present State |
| SDHC_HOST_CN_1 | Host Control 1 |
| SDHC_PWR | Power Control |
| SDHC_BLK_GAP | Block Gap Control |
| SDHC_WAKEUP | Wakeup Control |
| SDHC_CLK_CN | Clock Control |
| SDHC_TO | Timeout Control |
| SDHC_SW_RESET | Software Reset |
| SDHC_INT_STAT | Normal Interrupt Status |
| SDHC_ER_INT_STAT | Error Interrupt Status |
| SDHC_INT_EN | Normal Interrupt Status Enable |
| SDHC_ER_INT_EN | Error Interrupt Status Enable |
| SDHC_INT_SIGNAL | Normal Interrupt Signal Enable |
| SDHC_ER_INT_SIGNAL | Error Interrupt Signal Enable |
| SDHC_AUTO_CMD_ER | Auto CMD Error Status |
| SDHC_HOST_CN_2 | Host Control 2 |
| SDHC_CFG_0 | Capabilities 0-31 |
| SDHC_CFG_1 | Capabilities 32-63 |
| SDHC_MAX_CURR_CFG | Maximum Current Capabilities |
| SDHC_FORCE_CMD | Force Event for Auto CMD Error Status |
| SDHC_FORCE_EVENT_INT_STAT | Force Event for Error Interrupt Status |
| SDHC_ADMA_ER | ADMA Error Status |
| SDHC_ADMA_ADDR_0 | ADMA System Address 0-31 |
| SDHC_ADMA_ADDR_1 | ADMA System Address 32-63 |
| SDHC_PRESET_0 | Preset Value for Initialization |
| SDHC_PRESET_1 | Preset Value for Default Speed |
| SDHC_PRESET_2 | Preset Value for High Speed |
| SDHC_PRESET_3 | Preset Value for SDR12 |
| SDHC_PRESET_4 | Preset Value for SDR25 |
| SDHC_PRESET_5 | Preset Value for SDR50 |
| SDHC_PRESET_6 | Preset Value for SDR104 |
| SDHC_PRESET_7 | Preset Value for DDR50 |
| SDHC_SLOT_INT | Slot Interrupt Status |
| SDHC_HOST_CN_VER | Host Controller Version |
| ►Semaphore (SEMA) | |
| ►SEMA_Registers | Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module |
| Register Offsets | SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address |
| SEMA_SEMAPHORES | Read to test and set, returns prior value. Write 0 to clear semaphore |
| SEMA_STATUS | Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken |
| ►SPI | |
| ►SPI_Registers | Registers, Bit Masks and Bit Positions for the SPI Peripheral Module |
| Register Offsets | SPI Peripheral Register Offsets from the SPI Base Peripheral Address |
| SPI_FIFO32 | Register for reading and writing the FIFO |
| SPI_FIFO16 | Register for reading and writing the FIFO |
| SPI_FIFO8 | Register for reading and writing the FIFO |
| SPI_CTRL0 | Register for controlling SPI peripheral |
| SPI_CTRL1 | Register for controlling SPI peripheral |
| SPI_CTRL2 | Register for controlling SPI peripheral |
| SPI_SS_TIME | Register for controlling SPI peripheral/Slave Select Timing |
| SPI_CLK_CFG | Register for controlling SPI clock rate |
| SPI_DMA | Register for controlling DMA |
| SPI_INT_FL | Register for reading and clearing interrupt flags. All bits are write 1 to clear |
| SPI_INT_EN | Register for enabling interrupts |
| SPI_WAKE_FL | Register for wake up flags. All bits in this register are write 1 to clear |
| SPI_WAKE_EN | Register for wake up enable |
| SPI_STAT | SPI Status register |
| ►SPI External Flash (SPIXF) | |
| ►SPIXF_Registers | Registers, Bit Masks and Bit Positions for the SPIXF Peripheral Module |
| Register Offsets | SPIXF Peripheral Register Offsets from the SPIXF Base Peripheral Address |
| SPIXF_CFG | SPIX Configuration Register |
| SPIXF_FETCH_CTRL | SPIX Fetch Control Register |
| SPIXF_MODE_CTRL | SPIX Mode Control Register |
| SPIXF_MODE_DATA | SPIX Mode Data Register |
| SPIXF_FB_CTRL | SPIX Feedback Control Register |
| SPIXF_IO_CTRL | SPIX IO Control Register |
| SPIXF_SEC_CTRL | SPIX Memory Security Control Register |
| SPIXF_BUS_IDLE | Bus Idle |
| ►SPI External Ram (SPIXR) | |
| ►SPIXR_Registers | Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module |
| Register Offsets | SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address |
| SPIXR_DATA32 | Register for reading and writing the FIFO |
| SPIXR_DATA16 | Register for reading and writing the FIFO |
| SPIXR_DATA8 | Register for reading and writing the FIFO |
| SPIXR_CTRL1 | Register for controlling SPI peripheral |
| SPIXR_CTRL2 | Register for controlling SPI peripheral |
| SPIXR_CTRL3 | Register for controlling SPI peripheral |
| SPIXR_SS_TIME | Register for controlling SPI peripheral |
| SPIXR_BRG_CTRL | Register for controlling SPI clock rate |
| SPIXR_DMA | Register for controlling DMA |
| SPIXR_INT_FL | Register for reading and clearing interrupt flags. All bits are write 1 to clear |
| SPIXR_INT_EN | Register for enabling interrupts |
| SPIXR_WAKE_FL | Register for wake up flags. All bits in this register are write 1 to clear |
| SPIXR_WAKE_EN | Register for wake up enable |
| SPIXR_STAT | SPI Status register |
| SPIXR_XMEM_CTRL | Register to control external memory |
| ►Timer (TMR) | |
| ►TMR_Registers | Registers, Bit Masks and Bit Positions for the TMR Peripheral Module |
| Register Offsets | TMR Peripheral Register Offsets from the TMR Base Peripheral Address |
| TMR_CNT | Count. This register stores the current timer count |
| TMR_CMP | Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001 |
| TMR_PWM | PWM. This register stores the value that is compared to the current timer count |
| TMR_INTR | Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt |
| TMR_CN | Timer Control Register |
| TMR_NOLCMP | Timer Non-Overlapping Compare Register |
| ►TPU | |
| ►TPU_Registers | Registers, Bit Masks and Bit Positions for the TPU Peripheral Module |
| Register Offsets | TPU Peripheral Register Offsets from the TPU Base Peripheral Address |
| TPU_CRYPTO_CTRL | Crypto Control Register |
| TPU_CIPHER_CTRL | Cipher Control Register |
| TPU_HASH_CTRL | HASH Control Register |
| TPU_CRC_CTRL | CRC Control Register |
| TPU_DMA_SRC | Crypto DMA Source Address |
| TPU_DMA_DEST | Crypto DMA Destination Address |
| TPU_DMA_CNT | Crypto DMA Byte Count |
| TPU_MAA_CTRL | MAA Control Register |
| TPU_CRYPTO_DIN | Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register |
| TPU_CRYPTO_DOUT | Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits |
| TPU_CRC_POLY | CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit |
| TPU_CRC_VAL | CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit |
| TPU_CRC_PRNG | Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled |
| TPU_HAM_ECC | Hamming ECC Register |
| TPU_CIPHER_INIT | Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits |
| TPU_CIPHER_KEY | Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits |
| TPU_HASH_DIGEST | This register holds the calculated hash value. This register is affected by the endian swap bits |
| TPU_HASH_MSG_SZ | Message Size. This register holds the lowest 32-bit of message size in bytes |
| TPU_MAA_MAWS | MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA operation |
| ►TRNG | |
| ►TRNG_Registers | Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module |
| Register Offsets | TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address |
| TRNG_CTRL | TRNG Control Register |
| TRNG_DATA | Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000 |
| ►UART | |
| ►UART_Registers | Registers, Bit Masks and Bit Positions for the UART Peripheral Module |
| Register Offsets | UART Peripheral Register Offsets from the UART Base Peripheral Address |
| UART_CTRL0 | Control Register |
| UART_CTRL1 | Threshold Control register |
| UART_STAT | Status Register |
| UART_INT_EN | Interrupt Enable Register |
| UART_INT_FL | Interrupt Status Flags |
| UART_BAUD0 | Baud rate register. Integer portion |
| UART_BAUD1 | Baud rate register. Decimal Setting |
| UART_FIFO | FIFO Data buffer |
| UART_DMA | DMA Configuration |
| UART_TXFIFO | Transmit FIFO Status register |
| ►Watchdog Timer (WDT) | |
| ►WDT_Registers | Registers, Bit Masks and Bit Positions for the WDT Peripheral Module |
| Register Offsets | WDT Peripheral Register Offsets from the WDT Base Peripheral Address |
| WDT_CTRL | Watchdog Timer Control Register |
| WDT_RST | Watchdog Timer Reset Register |
| ►AES_KEY_Registers | Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module |
| Register Offsets | AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address |
| ►AESKEYS_Registers | Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module |
| Register Offsets | AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address |
| ►BBFC_Registers | Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module |
| Register Offsets | BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address |
| BBFC_BBFCR0 | Register 0 |
| ►GCR_Registers | Registers, Bit Masks and Bit Positions for the GCR Peripheral Module |
| Register Offsets | GCR Peripheral Register Offsets from the GCR Base Peripheral Address |
| GCR_SCON | System Control |
| GCR_RST0 | Reset |
| GCR_CLK_CTRL | Clock Control |
| GCR_PMR | Power Management |
| GCR_PCLK_DIV | Peripheral Clock Divider |
| GCR_PCLK_DIS0 | Peripheral Clock Disable |
| GCR_MEM_CLK | Memory Clock Control Register |
| GCR_MEM_ZERO | Memory Zeroize Control |
| GCR_SYS_STAT | System Status Register |
| GCR_RST1 | Reset 1 |
| GCR_PCLK_DIS1 | Peripheral Clock Disable |
| GCR_EVENT_EN | Event Enable Register |
| GCR_REV | Revision Register |
| GCR_SYS_STAT_IE | System Status Interrupt Enable Register |
| ►NBBFC_Registers | Registers, Bit Masks and Bit Positions for the NBBFC Peripheral Module |
| Register Offsets | NBBFC Peripheral Register Offsets from the NBBFC Base Peripheral Address |
| NBBFC_REG0 | Register 0 |
| NBBFC_REG1 | Register 1 |
| NBBFC_REG2 | Register 2 |
| NBBFC_REG3 | Register 3 |
| ►PTG_Registers | Registers, Bit Masks and Bit Positions for the PTG Peripheral Module |
| Register Offsets | PTG Peripheral Register Offsets from the PTG Base Peripheral Address |
| PTG_ENABLE | Global Enable/Disable Controls for All Pulse Trains |
| PTG_RESYNC | Global Resync (All Pulse Trains) Control |
| PTG_INTFL | Pulse Train Interrupt Flags |
| PTG_INTEN | Pulse Train Interrupt Enable/Disable |
| PTG_SAFE_EN | Pulse Train Global Safe Enable |
| PTG_SAFE_DIS | Pulse Train Global Safe Disable |
| ►SDMA_Registers | Registers, Bit Masks and Bit Positions for the SDMA Peripheral Module |
| Register Offsets | SDMA Peripheral Register Offsets from the SDMA Base Peripheral Address |
| SDMA_INT_MUX_CTRL0 | Interrupt Mux Control 0 |
| SDMA_INT_MUX_CTRL1 | Interrupt Mux Control 1 |
| SDMA_INT_MUX_CTRL2 | Interrupt Mux Control 2 |
| SDMA_INT_MUX_CTRL3 | Interrupt Mux Control 3 |
| SDMA_IP_ADDR | Configurable starting IP address for Q30E |
| SDMA_CTRL | Control Register |
| SDMA_INT_IN_CTRL | Interrupt Input From CPU Control Register |
| SDMA_INT_IN_FLAG | Interrupt Input From CPU Flag |
| SDMA_INT_IN_IE | Interrupt Input From CPU Enable |
| SDMA_IRQ_FLAG | Interrupt Output To CPU Flag |
| SDMA_IRQ_IE | Interrupt Output To CPU Control Register |
| ►SIR_Registers | Registers, Bit Masks and Bit Positions for the SIR Peripheral Module |
| Register Offsets | SIR Peripheral Register Offsets from the SIR Base Peripheral Address |
| SIR_SISTAT | System Initialization Status Register |
| SIR_ERRADDR | Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1) |
| SIR_FSTAT | Funcstat register |
| SIR_SFSTAT | Secfuncstat register |
| ►SMON_Registers | Registers, Bit Masks and Bit Positions for the SMON Peripheral Module |
| Register Offsets | SMON Peripheral Register Offsets from the SMON Base Peripheral Address |
| SMON_EXTSCN | External Sensor Control Register |
| SMON_INTSCN | Internal Sensor Control Register |
| SMON_SECALM | Security Alarm Register |
| SMON_SECDIAG | Security Diagnostic Register |
| SMON_DLRTC | DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred |
| SMON_SECST | Security Monitor Status |
| ►SPIXFC_FIFO_Registers | Registers, Bit Masks and Bit Positions for the SPIXFC_FIFO Peripheral Module |
| Register Offsets | SPIXFC_FIFO Peripheral Register Offsets from the SPIXFC_FIFO Base Peripheral Address |
| ►SPIXFC_Registers | Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module |
| Register Offsets | SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address |
| SPIXFC_CFG | Configuration Register |
| SPIXFC_SS_POL | SPIX Controller Slave Select Polarity Register |
| SPIXFC_GEN_CTRL | SPIX Controller General Controller Register |
| SPIXFC_FIFO_CTRL | SPIX Controller FIFO Control and Status Register |
| SPIXFC_SP_CTRL | SPIX Controller Special Control Register |
| SPIXFC_INT_FL | SPIX Controller Interrupt Status Register |
| SPIXFC_INT_EN | SPIX Controller Interrupt Enable Register |
| ►TRIMSIR_Registers | Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module |
| Register Offsets | TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address |
| ►USBHS_Registers | Registers, Bit Masks and Bit Positions for the USBHS Peripheral Module |
| Register Offsets | USBHS Peripheral Register Offsets from the USBHS Base Peripheral Address |
| USBHS_FADDR | Function address register |
| USBHS_POWER | Power management register |
| USBHS_INTRIN | Interrupt register for EP0 and IN EP1-15 |
| USBHS_INTROUT | Interrupt register for OUT EP 1-15 |
| USBHS_INTRINEN | Interrupt enable for EP 0 and IN EP 1-15 |
| USBHS_INTROUTEN | Interrupt enable for OUT EP 1-15 |
| USBHS_INTRUSB | Interrupt register for common USB interrupts |
| USBHS_INTRUSBEN | Interrupt enable for common USB interrupts |
| USBHS_FRAME | Frame number |
| USBHS_INDEX | Index for banked registers |
| USBHS_TESTMODE | USB 2.0 test mode enable register |
| USBHS_INMAXP | Maximum packet size for INx endpoint (x == INDEX) |
| USBHS_CSR0 | Control status register for EP 0 (when INDEX == 0) |
| USBHS_INCSRL | Control status lower register for INx endpoint (x == INDEX) |
| USBHS_INCSRU | Control status upper register for INx endpoint (x == INDEX) |
| USBHS_OUTMAXP | Maximum packet size for OUTx endpoint (x == INDEX) |
| USBHS_OUTCSRL | Control status lower register for OUTx endpoint (x == INDEX) |
| USBHS_OUTCSRU | Control status upper register for OUTx endpoint (x == INDEX) |
| USBHS_COUNT0 | Number of received bytes in EP 0 FIFO (INDEX == 0) |
| USBHS_OUTCOUNT | Number of received bytes in OUT EPx FIFO (x == INDEX) |
| USBHS_FIFO0 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO1 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO2 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO3 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO4 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO5 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO6 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO7 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO8 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO9 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO10 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO11 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO12 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO13 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO14 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_FIFO15 | Read for OUT data FIFO, write for IN data FIFO |
| USBHS_HWVERS | HWVERS |
| USBHS_EPINFO | Endpoint hardware information |
| USBHS_RAMINFO | RAM width information |
| USBHS_SOFTRESET | Software reset register |
| USBHS_CTUCH | Chirp timeout timer setting |
| USBHS_CTHSRTN | Sets delay between HS resume to UTM normal operating mode |
| USBHS_MXM_INT | USB Added Maxim Interrupt Flag Register |
| USBHS_MXM_INT_EN | USB Added Maxim Interrupt Enable Register |
| USBHS_MXM_SUSPEND | USB Added Maxim Suspend Register |
| USBHS_MXM_REG_A4 | USB Added Maxim Power Status Register |
1.9.4 
