hpb_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t status;               
    __IO uint32_t inten;                
    __IO uint32_t intfl;                
    __R  uint32_t rsv_0xc;
    __IO uint32_t mbr[2];               
    __R  uint32_t rsv_0x18_0x1f[2];
    __IO uint32_t mcr[2];               
    __R  uint32_t rsv_0x28_0x2f[2];
    __IO uint32_t mtr[2];               
} mxc_hpb_regs_t;
 
/* Register offsets for module HPB */
#define MXC_R_HPB_STATUS                   ((uint32_t)0x00000000UL) 
#define MXC_R_HPB_INTEN                    ((uint32_t)0x00000004UL) 
#define MXC_R_HPB_INTFL                    ((uint32_t)0x00000008UL) 
#define MXC_R_HPB_MBR                      ((uint32_t)0x00000010UL) 
#define MXC_R_HPB_MCR                      ((uint32_t)0x00000020UL) 
#define MXC_R_HPB_MTR                      ((uint32_t)0x00000030UL) 
#define MXC_F_HPB_STATUS_RACT_POS                      0 
#define MXC_F_HPB_STATUS_RACT                          ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RACT_POS)) 
#define MXC_V_HPB_STATUS_RACT_NOREAD                   ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_RACT_NOREAD                   (MXC_V_HPB_STATUS_RACT_NOREAD << MXC_F_HPB_STATUS_RACT_POS) 
#define MXC_V_HPB_STATUS_RACT_READ                     ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_RACT_READ                     (MXC_V_HPB_STATUS_RACT_READ << MXC_F_HPB_STATUS_RACT_POS) 
#define MXC_F_HPB_STATUS_RDECERR_POS                   8 
#define MXC_F_HPB_STATUS_RDECERR                       ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RDECERR_POS)) 
#define MXC_V_HPB_STATUS_RDECERR_NOERR                 ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_RDECERR_NOERR                 (MXC_V_HPB_STATUS_RDECERR_NOERR << MXC_F_HPB_STATUS_RDECERR_POS) 
#define MXC_V_HPB_STATUS_RDECERR_ERR                   ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_RDECERR_ERR                   (MXC_V_HPB_STATUS_RDECERR_ERR << MXC_F_HPB_STATUS_RDECERR_POS) 
#define MXC_F_HPB_STATUS_RRSTOERR_POS                  10 
#define MXC_F_HPB_STATUS_RRSTOERR                      ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RRSTOERR_POS)) 
#define MXC_V_HPB_STATUS_RRSTOERR_NOERR                ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_RRSTOERR_NOERR                (MXC_V_HPB_STATUS_RRSTOERR_NOERR << MXC_F_HPB_STATUS_RRSTOERR_POS) 
#define MXC_V_HPB_STATUS_RRSTOERR_ERR                  ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_RRSTOERR_ERR                  (MXC_V_HPB_STATUS_RRSTOERR_ERR << MXC_F_HPB_STATUS_RRSTOERR_POS) 
#define MXC_F_HPB_STATUS_RDSSTALL_POS                  11 
#define MXC_F_HPB_STATUS_RDSSTALL                      ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_RDSSTALL_POS)) 
#define MXC_V_HPB_STATUS_RDSSTALL_NORMALOP             ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_RDSSTALL_NORMALOP             (MXC_V_HPB_STATUS_RDSSTALL_NORMALOP << MXC_F_HPB_STATUS_RDSSTALL_POS) 
#define MXC_V_HPB_STATUS_RDSSTALL_STALLED              ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_RDSSTALL_STALLED              (MXC_V_HPB_STATUS_RDSSTALL_STALLED << MXC_F_HPB_STATUS_RDSSTALL_POS) 
#define MXC_F_HPB_STATUS_WACT_POS                      16 
#define MXC_F_HPB_STATUS_WACT                          ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WACT_POS)) 
#define MXC_V_HPB_STATUS_WACT_NOWRITE                  ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_WACT_NOWRITE                  (MXC_V_HPB_STATUS_WACT_NOWRITE << MXC_F_HPB_STATUS_WACT_POS) 
#define MXC_V_HPB_STATUS_WACT_WRITE                    ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_WACT_WRITE                    (MXC_V_HPB_STATUS_WACT_WRITE << MXC_F_HPB_STATUS_WACT_POS) 
#define MXC_F_HPB_STATUS_WDECERR_POS                   24 
#define MXC_F_HPB_STATUS_WDECERR                       ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WDECERR_POS)) 
#define MXC_V_HPB_STATUS_WDECERR_NOERR                 ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_WDECERR_NOERR                 (MXC_V_HPB_STATUS_WDECERR_NOERR << MXC_F_HPB_STATUS_WDECERR_POS) 
#define MXC_V_HPB_STATUS_WDECERR_ERR                   ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_WDECERR_ERR                   (MXC_V_HPB_STATUS_WDECERR_ERR << MXC_F_HPB_STATUS_WDECERR_POS) 
#define MXC_F_HPB_STATUS_WRSTOERR_POS                  26 
#define MXC_F_HPB_STATUS_WRSTOERR                      ((uint32_t)(0x1UL << MXC_F_HPB_STATUS_WRSTOERR_POS)) 
#define MXC_V_HPB_STATUS_WRSTOERR_NOERR                ((uint32_t)0x0UL) 
#define MXC_S_HPB_STATUS_WRSTOERR_NOERR                (MXC_V_HPB_STATUS_WRSTOERR_NOERR << MXC_F_HPB_STATUS_WRSTOERR_POS) 
#define MXC_V_HPB_STATUS_WRSTOERR_ERR                  ((uint32_t)0x1UL) 
#define MXC_S_HPB_STATUS_WRSTOERR_ERR                  (MXC_V_HPB_STATUS_WRSTOERR_ERR << MXC_F_HPB_STATUS_WRSTOERR_POS) 
#define MXC_F_HPB_INTEN_ERRINTE_POS                    1 
#define MXC_F_HPB_INTEN_ERRINTE                        ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_ERRINTE_POS)) 
#define MXC_V_HPB_INTEN_ERRINTE_DIS                    ((uint32_t)0x0UL) 
#define MXC_S_HPB_INTEN_ERRINTE_DIS                    (MXC_V_HPB_INTEN_ERRINTE_DIS << MXC_F_HPB_INTEN_ERRINTE_POS) 
#define MXC_V_HPB_INTEN_ERRINTE_EN                     ((uint32_t)0x1UL) 
#define MXC_S_HPB_INTEN_ERRINTE_EN                     (MXC_V_HPB_INTEN_ERRINTE_EN << MXC_F_HPB_INTEN_ERRINTE_POS) 
#define MXC_F_HPB_INTFL_ERRINT_POS                     1 
#define MXC_F_HPB_INTFL_ERRINT                         ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_ERRINT_POS)) 
#define MXC_V_HPB_INTFL_ERRINT_NOINT                   ((uint32_t)0x0UL) 
#define MXC_S_HPB_INTFL_ERRINT_NOINT                   (MXC_V_HPB_INTFL_ERRINT_NOINT << MXC_F_HPB_INTFL_ERRINT_POS) 
#define MXC_V_HPB_INTFL_ERRINT_PENDING                 ((uint32_t)0x1UL) 
#define MXC_S_HPB_INTFL_ERRINT_PENDING                 (MXC_V_HPB_INTFL_ERRINT_PENDING << MXC_F_HPB_INTFL_ERRINT_POS) 
#define MXC_F_HPB_MBR_ADDR_POS                         24 
#define MXC_F_HPB_MBR_ADDR                             ((uint32_t)(0xFFUL << MXC_F_HPB_MBR_ADDR_POS)) 
#define MXC_F_HPB_MCR_DEV_TYPE_POS                     3 
#define MXC_F_HPB_MCR_DEV_TYPE                         ((uint32_t)(0x3UL << MXC_F_HPB_MCR_DEV_TYPE_POS)) 
#define MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH              ((uint32_t)0x0UL) 
#define MXC_S_HPB_MCR_DEV_TYPE_HYPERFLASH              (MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH << MXC_F_HPB_MCR_DEV_TYPE_POS) 
#define MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM             ((uint32_t)0x1UL) 
#define MXC_S_HPB_MCR_DEV_TYPE_XCCELAPSRAM             (MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) 
#define MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM                ((uint32_t)0x2UL) 
#define MXC_S_HPB_MCR_DEV_TYPE_HYPERRAM                (MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) 
#define MXC_F_HPB_MCR_CRT_POS                          5 
#define MXC_F_HPB_MCR_CRT                              ((uint32_t)(0x1UL << MXC_F_HPB_MCR_CRT_POS)) 
#define MXC_V_HPB_MCR_CRT_MEM_SPACE                    ((uint32_t)0x0UL) 
#define MXC_S_HPB_MCR_CRT_MEM_SPACE                    (MXC_V_HPB_MCR_CRT_MEM_SPACE << MXC_F_HPB_MCR_CRT_POS) 
#define MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE             ((uint32_t)0x1UL) 
#define MXC_S_HPB_MCR_CRT_CONFIG_REG_SPACE             (MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE << MXC_F_HPB_MCR_CRT_POS) 
#define MXC_F_HPB_MCR_READ_LATENCY_POS                 6 
#define MXC_F_HPB_MCR_READ_LATENCY                     ((uint32_t)(0x1UL << MXC_F_HPB_MCR_READ_LATENCY_POS)) 
#define MXC_V_HPB_MCR_READ_LATENCY_VARIABLE            ((uint32_t)0x0UL) 
#define MXC_S_HPB_MCR_READ_LATENCY_VARIABLE            (MXC_V_HPB_MCR_READ_LATENCY_VARIABLE << MXC_F_HPB_MCR_READ_LATENCY_POS) 
#define MXC_V_HPB_MCR_READ_LATENCY_FIXED               ((uint32_t)0x1UL) 
#define MXC_S_HPB_MCR_READ_LATENCY_FIXED               (MXC_V_HPB_MCR_READ_LATENCY_FIXED << MXC_F_HPB_MCR_READ_LATENCY_POS) 
#define MXC_F_HPB_MCR_HSE_POS                          7 
#define MXC_F_HPB_MCR_HSE                              ((uint32_t)(0x1UL << MXC_F_HPB_MCR_HSE_POS)) 
#define MXC_V_HPB_MCR_HSE_DIS                          ((uint32_t)0x0UL) 
#define MXC_S_HPB_MCR_HSE_DIS                          (MXC_V_HPB_MCR_HSE_DIS << MXC_F_HPB_MCR_HSE_POS) 
#define MXC_V_HPB_MCR_HSE_EN                           ((uint32_t)0x1UL) 
#define MXC_S_HPB_MCR_HSE_EN                           (MXC_V_HPB_MCR_HSE_EN << MXC_F_HPB_MCR_HSE_POS) 
#define MXC_F_HPB_MCR_MAXLEN_POS                       18 
#define MXC_F_HPB_MCR_MAXLEN                           ((uint32_t)(0x1FFUL << MXC_F_HPB_MCR_MAXLEN_POS)) 
#define MXC_F_HPB_MCR_MAXLEN_EN_POS                    31 
#define MXC_F_HPB_MCR_MAXLEN_EN                        ((uint32_t)(0x1UL << MXC_F_HPB_MCR_MAXLEN_EN_POS)) 
#define MXC_V_HPB_MCR_MAXLEN_EN_DIS                    ((uint32_t)0x0UL) 
#define MXC_S_HPB_MCR_MAXLEN_EN_DIS                    (MXC_V_HPB_MCR_MAXLEN_EN_DIS << MXC_F_HPB_MCR_MAXLEN_EN_POS) 
#define MXC_V_HPB_MCR_MAXLEN_EN_EN                     ((uint32_t)0x1UL) 
#define MXC_S_HPB_MCR_MAXLEN_EN_EN                     (MXC_V_HPB_MCR_MAXLEN_EN_EN << MXC_F_HPB_MCR_MAXLEN_EN_POS) 
#define MXC_F_HPB_MTR_LATENCY_POS                      0 
#define MXC_F_HPB_MTR_LATENCY                          ((uint32_t)(0xFUL << MXC_F_HPB_MTR_LATENCY_POS)) 
#define MXC_V_HPB_MTR_LATENCY_5CLK                     ((uint32_t)0x0UL) 
#define MXC_S_HPB_MTR_LATENCY_5CLK                     (MXC_V_HPB_MTR_LATENCY_5CLK << MXC_F_HPB_MTR_LATENCY_POS) 
#define MXC_V_HPB_MTR_LATENCY_6CLK                     ((uint32_t)0x1UL) 
#define MXC_S_HPB_MTR_LATENCY_6CLK                     (MXC_V_HPB_MTR_LATENCY_6CLK << MXC_F_HPB_MTR_LATENCY_POS) 
#define MXC_V_HPB_MTR_LATENCY_3CLK                     ((uint32_t)0xEUL) 
#define MXC_S_HPB_MTR_LATENCY_3CLK                     (MXC_V_HPB_MTR_LATENCY_3CLK << MXC_F_HPB_MTR_LATENCY_POS) 
#define MXC_V_HPB_MTR_LATENCY_4CLK                     ((uint32_t)0xFUL) 
#define MXC_S_HPB_MTR_LATENCY_4CLK                     (MXC_V_HPB_MTR_LATENCY_4CLK << MXC_F_HPB_MTR_LATENCY_POS) 
#define MXC_F_HPB_MTR_WCSH_POS                         8 
#define MXC_F_HPB_MTR_WCSH                             ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSH_POS)) 
#define MXC_F_HPB_MTR_RCSH_POS                         12 
#define MXC_F_HPB_MTR_RCSH                             ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSH_POS)) 
#define MXC_F_HPB_MTR_WCSS_POS                         16 
#define MXC_F_HPB_MTR_WCSS                             ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSS_POS)) 
#define MXC_F_HPB_MTR_RCSS_POS                         20 
#define MXC_F_HPB_MTR_RCSS                             ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSS_POS)) 
#define MXC_F_HPB_MTR_WCSHI_POS                        24 
#define MXC_F_HPB_MTR_WCSHI                            ((uint32_t)(0xFUL << MXC_F_HPB_MTR_WCSHI_POS)) 
#define MXC_F_HPB_MTR_RCSHI_POS                        28 
#define MXC_F_HPB_MTR_RCSHI                            ((uint32_t)(0xFUL << MXC_F_HPB_MTR_RCSHI_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_HPB_REGS_H_