Documentation/MAX32650/spi__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    union {

        __IO uint32_t fifo32;

        __IO uint16_t fifo16[2];

        __IO uint8_t  fifo8[4];

    };

    __IO uint32_t ctrl0;

    __IO uint32_t ctrl1;

    __IO uint32_t ctrl2;

    __IO uint32_t ss_time;

    __IO uint32_t clk_cfg;

    __R  uint32_t rsv_0x18;

    __IO uint32_t dma;

    __IO uint32_t int_fl;

    __IO uint32_t int_en;

    __IO uint32_t wake_fl;

    __IO uint32_t wake_en;

    __I  uint32_t stat;

} mxc_spi_regs_t;


/* Register offsets for module SPI */

#define MXC_R_SPI_FIFO32                   ((uint32_t)0x00000000UL)

#define MXC_R_SPI_FIFO16                   ((uint32_t)0x00000000UL)

#define MXC_R_SPI_FIFO8                    ((uint32_t)0x00000000UL)

#define MXC_R_SPI_CTRL0                    ((uint32_t)0x00000004UL)

#define MXC_R_SPI_CTRL1                    ((uint32_t)0x00000008UL)

#define MXC_R_SPI_CTRL2                    ((uint32_t)0x0000000CUL)

#define MXC_R_SPI_SS_TIME                  ((uint32_t)0x00000010UL)

#define MXC_R_SPI_CLK_CFG                  ((uint32_t)0x00000014UL)

#define MXC_R_SPI_DMA                      ((uint32_t)0x0000001CUL)

#define MXC_R_SPI_INT_FL                   ((uint32_t)0x00000020UL)

#define MXC_R_SPI_INT_EN                   ((uint32_t)0x00000024UL)

#define MXC_R_SPI_WAKE_FL                  ((uint32_t)0x00000028UL)

#define MXC_R_SPI_WAKE_EN                  ((uint32_t)0x0000002CUL)

#define MXC_R_SPI_STAT                     ((uint32_t)0x00000030UL)

#define MXC_F_SPI_FIFO32_DATA_POS                      0

#define MXC_F_SPI_FIFO32_DATA                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS))

#define MXC_F_SPI_FIFO16_DATA_POS                      0

#define MXC_F_SPI_FIFO16_DATA                          ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS))

#define MXC_F_SPI_FIFO8_DATA_POS                       0

#define MXC_F_SPI_FIFO8_DATA                           ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS))

#define MXC_F_SPI_CTRL0_SPI_EN_POS                     0

#define MXC_F_SPI_CTRL0_SPI_EN                         ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS))

#define MXC_V_SPI_CTRL0_SPI_EN_DIS                     ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL0_SPI_EN_DIS                     (MXC_V_SPI_CTRL0_SPI_EN_DIS << MXC_F_SPI_CTRL0_SPI_EN_POS)

#define MXC_V_SPI_CTRL0_SPI_EN_EN                      ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_SPI_EN_EN                      (MXC_V_SPI_CTRL0_SPI_EN_EN << MXC_F_SPI_CTRL0_SPI_EN_POS)

#define MXC_F_SPI_CTRL0_MM_EN_POS                      1

#define MXC_F_SPI_CTRL0_MM_EN                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS))

#define MXC_V_SPI_CTRL0_MM_EN_DIS                      ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL0_MM_EN_DIS                      (MXC_V_SPI_CTRL0_MM_EN_DIS << MXC_F_SPI_CTRL0_MM_EN_POS)

#define MXC_V_SPI_CTRL0_MM_EN_EN                       ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_MM_EN_EN                       (MXC_V_SPI_CTRL0_MM_EN_EN << MXC_F_SPI_CTRL0_MM_EN_POS)

#define MXC_F_SPI_CTRL0_SS_IO_POS                      4

#define MXC_F_SPI_CTRL0_SS_IO                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS))

#define MXC_V_SPI_CTRL0_SS_IO_OUTPUT                   ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL0_SS_IO_OUTPUT                   (MXC_V_SPI_CTRL0_SS_IO_OUTPUT << MXC_F_SPI_CTRL0_SS_IO_POS)

#define MXC_V_SPI_CTRL0_SS_IO_INPUT                    ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_SS_IO_INPUT                    (MXC_V_SPI_CTRL0_SS_IO_INPUT << MXC_F_SPI_CTRL0_SS_IO_POS)

#define MXC_F_SPI_CTRL0_START_POS                      5

#define MXC_F_SPI_CTRL0_START                          ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS))

#define MXC_V_SPI_CTRL0_START_START                    ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_START_START                    (MXC_V_SPI_CTRL0_START_START << MXC_F_SPI_CTRL0_START_POS)

#define MXC_F_SPI_CTRL0_SS_CTRL_POS                    8

#define MXC_F_SPI_CTRL0_SS_CTRL                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS))

#define MXC_V_SPI_CTRL0_SS_CTRL_DEASSERT               ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL0_SS_CTRL_DEASSERT               (MXC_V_SPI_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI_CTRL0_SS_CTRL_POS)

#define MXC_V_SPI_CTRL0_SS_CTRL_ASSERT                 ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_SS_CTRL_ASSERT                 (MXC_V_SPI_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI_CTRL0_SS_CTRL_POS)

#define MXC_F_SPI_CTRL0_SS_SEL_POS                     16

#define MXC_F_SPI_CTRL0_SS_SEL                         ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS))

#define MXC_V_SPI_CTRL0_SS_SEL_SS0                     ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL0_SS_SEL_SS0                     (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS)

#define MXC_V_SPI_CTRL0_SS_SEL_SS1                     ((uint32_t)0x2UL)

#define MXC_S_SPI_CTRL0_SS_SEL_SS1                     (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS)

#define MXC_V_SPI_CTRL0_SS_SEL_SS2                     ((uint32_t)0x4UL)

#define MXC_S_SPI_CTRL0_SS_SEL_SS2                     (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS)

#define MXC_V_SPI_CTRL0_SS_SEL_SS3                     ((uint32_t)0x8UL)

#define MXC_S_SPI_CTRL0_SS_SEL_SS3                     (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS)

#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS                0

#define MXC_F_SPI_CTRL1_TX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS))

#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS                16

#define MXC_F_SPI_CTRL1_RX_NUM_CHAR                    ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS))

#define MXC_F_SPI_CTRL2_CLK_PHA_POS                    0

#define MXC_F_SPI_CTRL2_CLK_PHA                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS))

#define MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE             ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL2_CLK_PHA_RISINGEDGE             (MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)

#define MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE            ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_CLK_PHA_FALLINGEDGE            (MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS)

#define MXC_F_SPI_CTRL2_CLK_POL_POS                    1

#define MXC_F_SPI_CTRL2_CLK_POL                        ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS))

#define MXC_V_SPI_CTRL2_CLK_POL_NORMAL                 ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL2_CLK_POL_NORMAL                 (MXC_V_SPI_CTRL2_CLK_POL_NORMAL << MXC_F_SPI_CTRL2_CLK_POL_POS)

#define MXC_V_SPI_CTRL2_CLK_POL_INVERTED               ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_CLK_POL_INVERTED               (MXC_V_SPI_CTRL2_CLK_POL_INVERTED << MXC_F_SPI_CTRL2_CLK_POL_POS)

#define MXC_F_SPI_CTRL2_NUM_BITS_POS                   8

#define MXC_F_SPI_CTRL2_NUM_BITS                       ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS))

#define MXC_V_SPI_CTRL2_NUM_BITS_16BITS                ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_16BITS                (MXC_V_SPI_CTRL2_NUM_BITS_16BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_1BITS                 ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_1BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_1BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_2BITS                 ((uint32_t)0x2UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_2BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_2BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_3BITS                 ((uint32_t)0x3UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_3BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_3BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_4BITS                 ((uint32_t)0x4UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_4BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_4BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_5BITS                 ((uint32_t)0x5UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_5BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_5BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_6BITS                 ((uint32_t)0x6UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_6BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_6BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_7BITS                 ((uint32_t)0x7UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_7BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_7BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_8BITS                 ((uint32_t)0x8UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_8BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_8BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_9BITS                 ((uint32_t)0x9UL)

#define MXC_S_SPI_CTRL2_NUM_BITS_9BITS                 (MXC_V_SPI_CTRL2_NUM_BITS_9BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_10BITS                ((uint32_t)0xAUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_10BITS                (MXC_V_SPI_CTRL2_NUM_BITS_10BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_11BITS                ((uint32_t)0xBUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_11BITS                (MXC_V_SPI_CTRL2_NUM_BITS_11BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_12BITS                ((uint32_t)0xCUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_12BITS                (MXC_V_SPI_CTRL2_NUM_BITS_12BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_13BITS                ((uint32_t)0xDUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_13BITS                (MXC_V_SPI_CTRL2_NUM_BITS_13BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_14BITS                ((uint32_t)0xEUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_14BITS                (MXC_V_SPI_CTRL2_NUM_BITS_14BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_V_SPI_CTRL2_NUM_BITS_15BITS                ((uint32_t)0xFUL)

#define MXC_S_SPI_CTRL2_NUM_BITS_15BITS                (MXC_V_SPI_CTRL2_NUM_BITS_15BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS)

#define MXC_F_SPI_CTRL2_BUS_WIDTH_POS                  12

#define MXC_F_SPI_CTRL2_BUS_WIDTH                      ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS))

#define MXC_V_SPI_CTRL2_BUS_WIDTH_MONO                 ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL2_BUS_WIDTH_MONO                 (MXC_V_SPI_CTRL2_BUS_WIDTH_MONO << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

#define MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL                 ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_BUS_WIDTH_DUAL                 (MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

#define MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD                 ((uint32_t)0x2UL)

#define MXC_S_SPI_CTRL2_BUS_WIDTH_QUAD                 (MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)

#define MXC_F_SPI_CTRL2_THREE_WIRE_POS                 15

#define MXC_F_SPI_CTRL2_THREE_WIRE                     ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS))

#define MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE               ((uint32_t)0x0UL)

#define MXC_S_SPI_CTRL2_THREE_WIRE_4WIRE               (MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)

#define MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE               ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_THREE_WIRE_3WIRE               (MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS)

#define MXC_F_SPI_CTRL2_SS_POL_POS                     16

#define MXC_F_SPI_CTRL2_SS_POL                         ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS))

#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH                ((uint32_t)0x1UL)

#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH                ((uint32_t)0x2UL)

#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH                ((uint32_t)0x4UL)

#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH                ((uint32_t)0x8UL)

#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH                (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS)

#define MXC_F_SPI_SS_TIME_SSACT1_POS                   0

#define MXC_F_SPI_SS_TIME_SSACT1                       ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS))

#define MXC_V_SPI_SS_TIME_SSACT1_256                   ((uint32_t)0x0UL)

#define MXC_S_SPI_SS_TIME_SSACT1_256                   (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS)

#define MXC_F_SPI_SS_TIME_SSACT2_POS                   8

#define MXC_F_SPI_SS_TIME_SSACT2                       ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS))

#define MXC_V_SPI_SS_TIME_SSACT2_256                   ((uint32_t)0x0UL)

#define MXC_S_SPI_SS_TIME_SSACT2_256                   (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS)

#define MXC_F_SPI_SS_TIME_SSINACT_POS                  16

#define MXC_F_SPI_SS_TIME_SSINACT                      ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS))

#define MXC_V_SPI_SS_TIME_SSINACT_256                  ((uint32_t)0x0UL)

#define MXC_S_SPI_SS_TIME_SSINACT_256                  (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS)

#define MXC_F_SPI_CLK_CFG_LO_POS                       0

#define MXC_F_SPI_CLK_CFG_LO                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS))

#define MXC_F_SPI_CLK_CFG_HI_POS                       8

#define MXC_F_SPI_CLK_CFG_HI                           ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS))

#define MXC_F_SPI_CLK_CFG_SCALE_POS                    16

#define MXC_F_SPI_CLK_CFG_SCALE                        ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS))

#define MXC_V_SPI_CLK_CFG_SCALE_DIV1                   ((uint32_t)0x0UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV1                   (MXC_V_SPI_CLK_CFG_SCALE_DIV1 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV2                   ((uint32_t)0x1UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV2                   (MXC_V_SPI_CLK_CFG_SCALE_DIV2 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV4                   ((uint32_t)0x2UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV4                   (MXC_V_SPI_CLK_CFG_SCALE_DIV4 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV8                   ((uint32_t)0x3UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV8                   (MXC_V_SPI_CLK_CFG_SCALE_DIV8 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV16                  ((uint32_t)0x4UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV16                  (MXC_V_SPI_CLK_CFG_SCALE_DIV16 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV32                  ((uint32_t)0x5UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV32                  (MXC_V_SPI_CLK_CFG_SCALE_DIV32 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV64                  ((uint32_t)0x6UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV64                  (MXC_V_SPI_CLK_CFG_SCALE_DIV64 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV128                 ((uint32_t)0x7UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV128                 (MXC_V_SPI_CLK_CFG_SCALE_DIV128 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_V_SPI_CLK_CFG_SCALE_DIV256                 ((uint32_t)0x8UL)

#define MXC_S_SPI_CLK_CFG_SCALE_DIV256                 (MXC_V_SPI_CLK_CFG_SCALE_DIV256 << MXC_F_SPI_CLK_CFG_SCALE_POS)

#define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS                0

#define MXC_F_SPI_DMA_TX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS))

#define MXC_F_SPI_DMA_TX_FIFO_EN_POS                   6

#define MXC_F_SPI_DMA_TX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS))

#define MXC_V_SPI_DMA_TX_FIFO_EN_DIS                   ((uint32_t)0x0UL)

#define MXC_S_SPI_DMA_TX_FIFO_EN_DIS                   (MXC_V_SPI_DMA_TX_FIFO_EN_DIS << MXC_F_SPI_DMA_TX_FIFO_EN_POS)

#define MXC_V_SPI_DMA_TX_FIFO_EN_EN                    ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_TX_FIFO_EN_EN                    (MXC_V_SPI_DMA_TX_FIFO_EN_EN << MXC_F_SPI_DMA_TX_FIFO_EN_POS)

#define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS                7

#define MXC_F_SPI_DMA_TX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS))

#define MXC_V_SPI_DMA_TX_FIFO_CLEAR_CLEAR              ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_TX_FIFO_CLEAR_CLEAR              (MXC_V_SPI_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)

#define MXC_F_SPI_DMA_TX_FIFO_CNT_POS                  8

#define MXC_F_SPI_DMA_TX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS))

#define MXC_F_SPI_DMA_TX_DMA_EN_POS                    15

#define MXC_F_SPI_DMA_TX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS))

#define MXC_V_SPI_DMA_TX_DMA_EN_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_DMA_TX_DMA_EN_DIS                    (MXC_V_SPI_DMA_TX_DMA_EN_DIS << MXC_F_SPI_DMA_TX_DMA_EN_POS)

#define MXC_V_SPI_DMA_TX_DMA_EN_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_TX_DMA_EN_EN                     (MXC_V_SPI_DMA_TX_DMA_EN_EN << MXC_F_SPI_DMA_TX_DMA_EN_POS)

#define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS                16

#define MXC_F_SPI_DMA_RX_FIFO_LEVEL                    ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS))

#define MXC_F_SPI_DMA_RX_FIFO_EN_POS                   22

#define MXC_F_SPI_DMA_RX_FIFO_EN                       ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS))

#define MXC_V_SPI_DMA_RX_FIFO_EN_DIS                   ((uint32_t)0x0UL)

#define MXC_S_SPI_DMA_RX_FIFO_EN_DIS                   (MXC_V_SPI_DMA_RX_FIFO_EN_DIS << MXC_F_SPI_DMA_RX_FIFO_EN_POS)

#define MXC_V_SPI_DMA_RX_FIFO_EN_EN                    ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_RX_FIFO_EN_EN                    (MXC_V_SPI_DMA_RX_FIFO_EN_EN << MXC_F_SPI_DMA_RX_FIFO_EN_POS)

#define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS                23

#define MXC_F_SPI_DMA_RX_FIFO_CLEAR                    ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS))

#define MXC_V_SPI_DMA_RX_FIFO_CLEAR_CLEAR              ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_RX_FIFO_CLEAR_CLEAR              (MXC_V_SPI_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)

#define MXC_F_SPI_DMA_RX_FIFO_CNT_POS                  24

#define MXC_F_SPI_DMA_RX_FIFO_CNT                      ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS))

#define MXC_F_SPI_DMA_RX_DMA_EN_POS                    31

#define MXC_F_SPI_DMA_RX_DMA_EN                        ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS))

#define MXC_V_SPI_DMA_RX_DMA_EN_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_DMA_RX_DMA_EN_DIS                    (MXC_V_SPI_DMA_RX_DMA_EN_DIS << MXC_F_SPI_DMA_RX_DMA_EN_POS)

#define MXC_V_SPI_DMA_RX_DMA_EN_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_DMA_RX_DMA_EN_EN                     (MXC_V_SPI_DMA_RX_DMA_EN_EN << MXC_F_SPI_DMA_RX_DMA_EN_POS)

#define MXC_F_SPI_INT_FL_TX_LEVEL_POS                  0

#define MXC_F_SPI_INT_FL_TX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS))

#define MXC_V_SPI_INT_FL_TX_LEVEL_CLEAR                ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_TX_LEVEL_CLEAR                (MXC_V_SPI_INT_FL_TX_LEVEL_CLEAR << MXC_F_SPI_INT_FL_TX_LEVEL_POS)

#define MXC_F_SPI_INT_FL_TX_EMPTY_POS                  1

#define MXC_F_SPI_INT_FL_TX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS))

#define MXC_V_SPI_INT_FL_TX_EMPTY_CLEAR                ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_TX_EMPTY_CLEAR                (MXC_V_SPI_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI_INT_FL_TX_EMPTY_POS)

#define MXC_F_SPI_INT_FL_RX_LEVEL_POS                  2

#define MXC_F_SPI_INT_FL_RX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS))

#define MXC_V_SPI_INT_FL_RX_LEVEL_CLEAR                ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_RX_LEVEL_CLEAR                (MXC_V_SPI_INT_FL_RX_LEVEL_CLEAR << MXC_F_SPI_INT_FL_RX_LEVEL_POS)

#define MXC_F_SPI_INT_FL_RX_FULL_POS                   3

#define MXC_F_SPI_INT_FL_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS))

#define MXC_V_SPI_INT_FL_RX_FULL_CLEAR                 ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_RX_FULL_CLEAR                 (MXC_V_SPI_INT_FL_RX_FULL_CLEAR << MXC_F_SPI_INT_FL_RX_FULL_POS)

#define MXC_F_SPI_INT_FL_SSA_POS                       4

#define MXC_F_SPI_INT_FL_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS))

#define MXC_V_SPI_INT_FL_SSA_CLEAR                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_SSA_CLEAR                     (MXC_V_SPI_INT_FL_SSA_CLEAR << MXC_F_SPI_INT_FL_SSA_POS)

#define MXC_F_SPI_INT_FL_SSD_POS                       5

#define MXC_F_SPI_INT_FL_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS))

#define MXC_V_SPI_INT_FL_SSD_CLEAR                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_SSD_CLEAR                     (MXC_V_SPI_INT_FL_SSD_CLEAR << MXC_F_SPI_INT_FL_SSD_POS)

#define MXC_F_SPI_INT_FL_FAULT_POS                     8

#define MXC_F_SPI_INT_FL_FAULT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS))

#define MXC_V_SPI_INT_FL_FAULT_CLEAR                   ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_FAULT_CLEAR                   (MXC_V_SPI_INT_FL_FAULT_CLEAR << MXC_F_SPI_INT_FL_FAULT_POS)

#define MXC_F_SPI_INT_FL_ABORT_POS                     9

#define MXC_F_SPI_INT_FL_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS))

#define MXC_V_SPI_INT_FL_ABORT_CLEAR                   ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_ABORT_CLEAR                   (MXC_V_SPI_INT_FL_ABORT_CLEAR << MXC_F_SPI_INT_FL_ABORT_POS)

#define MXC_F_SPI_INT_FL_M_DONE_POS                    11

#define MXC_F_SPI_INT_FL_M_DONE                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS))

#define MXC_V_SPI_INT_FL_M_DONE_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_M_DONE_CLEAR                  (MXC_V_SPI_INT_FL_M_DONE_CLEAR << MXC_F_SPI_INT_FL_M_DONE_POS)

#define MXC_F_SPI_INT_FL_TX_OVR_POS                    12

#define MXC_F_SPI_INT_FL_TX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS))

#define MXC_V_SPI_INT_FL_TX_OVR_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_TX_OVR_CLEAR                  (MXC_V_SPI_INT_FL_TX_OVR_CLEAR << MXC_F_SPI_INT_FL_TX_OVR_POS)

#define MXC_F_SPI_INT_FL_TX_UND_POS                    13

#define MXC_F_SPI_INT_FL_TX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS))

#define MXC_V_SPI_INT_FL_TX_UND_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_TX_UND_CLEAR                  (MXC_V_SPI_INT_FL_TX_UND_CLEAR << MXC_F_SPI_INT_FL_TX_UND_POS)

#define MXC_F_SPI_INT_FL_RX_OVR_POS                    14

#define MXC_F_SPI_INT_FL_RX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS))

#define MXC_V_SPI_INT_FL_RX_OVR_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_RX_OVR_CLEAR                  (MXC_V_SPI_INT_FL_RX_OVR_CLEAR << MXC_F_SPI_INT_FL_RX_OVR_POS)

#define MXC_F_SPI_INT_FL_RX_UND_POS                    15

#define MXC_F_SPI_INT_FL_RX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS))

#define MXC_V_SPI_INT_FL_RX_UND_CLEAR                  ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_FL_RX_UND_CLEAR                  (MXC_V_SPI_INT_FL_RX_UND_CLEAR << MXC_F_SPI_INT_FL_RX_UND_POS)

#define MXC_F_SPI_INT_EN_TX_LEVEL_POS                  0

#define MXC_F_SPI_INT_EN_TX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS))

#define MXC_V_SPI_INT_EN_TX_LEVEL_DIS                  ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_TX_LEVEL_DIS                  (MXC_V_SPI_INT_EN_TX_LEVEL_DIS << MXC_F_SPI_INT_EN_TX_LEVEL_POS)

#define MXC_V_SPI_INT_EN_TX_LEVEL_EN                   ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_TX_LEVEL_EN                   (MXC_V_SPI_INT_EN_TX_LEVEL_EN << MXC_F_SPI_INT_EN_TX_LEVEL_POS)

#define MXC_F_SPI_INT_EN_TX_EMPTY_POS                  1

#define MXC_F_SPI_INT_EN_TX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS))

#define MXC_V_SPI_INT_EN_TX_EMPTY_DIS                  ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_TX_EMPTY_DIS                  (MXC_V_SPI_INT_EN_TX_EMPTY_DIS << MXC_F_SPI_INT_EN_TX_EMPTY_POS)

#define MXC_V_SPI_INT_EN_TX_EMPTY_EN                   ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_TX_EMPTY_EN                   (MXC_V_SPI_INT_EN_TX_EMPTY_EN << MXC_F_SPI_INT_EN_TX_EMPTY_POS)

#define MXC_F_SPI_INT_EN_RX_LEVEL_POS                  2

#define MXC_F_SPI_INT_EN_RX_LEVEL                      ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS))

#define MXC_V_SPI_INT_EN_RX_LEVEL_DIS                  ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_RX_LEVEL_DIS                  (MXC_V_SPI_INT_EN_RX_LEVEL_DIS << MXC_F_SPI_INT_EN_RX_LEVEL_POS)

#define MXC_V_SPI_INT_EN_RX_LEVEL_EN                   ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_RX_LEVEL_EN                   (MXC_V_SPI_INT_EN_RX_LEVEL_EN << MXC_F_SPI_INT_EN_RX_LEVEL_POS)

#define MXC_F_SPI_INT_EN_RX_FULL_POS                   3

#define MXC_F_SPI_INT_EN_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS))

#define MXC_V_SPI_INT_EN_RX_FULL_DIS                   ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_RX_FULL_DIS                   (MXC_V_SPI_INT_EN_RX_FULL_DIS << MXC_F_SPI_INT_EN_RX_FULL_POS)

#define MXC_V_SPI_INT_EN_RX_FULL_EN                    ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_RX_FULL_EN                    (MXC_V_SPI_INT_EN_RX_FULL_EN << MXC_F_SPI_INT_EN_RX_FULL_POS)

#define MXC_F_SPI_INT_EN_SSA_POS                       4

#define MXC_F_SPI_INT_EN_SSA                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS))

#define MXC_V_SPI_INT_EN_SSA_DIS                       ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_SSA_DIS                       (MXC_V_SPI_INT_EN_SSA_DIS << MXC_F_SPI_INT_EN_SSA_POS)

#define MXC_V_SPI_INT_EN_SSA_EN                        ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_SSA_EN                        (MXC_V_SPI_INT_EN_SSA_EN << MXC_F_SPI_INT_EN_SSA_POS)

#define MXC_F_SPI_INT_EN_SSD_POS                       5

#define MXC_F_SPI_INT_EN_SSD                           ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS))

#define MXC_V_SPI_INT_EN_SSD_DIS                       ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_SSD_DIS                       (MXC_V_SPI_INT_EN_SSD_DIS << MXC_F_SPI_INT_EN_SSD_POS)

#define MXC_V_SPI_INT_EN_SSD_EN                        ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_SSD_EN                        (MXC_V_SPI_INT_EN_SSD_EN << MXC_F_SPI_INT_EN_SSD_POS)

#define MXC_F_SPI_INT_EN_FAULT_POS                     8

#define MXC_F_SPI_INT_EN_FAULT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS))

#define MXC_V_SPI_INT_EN_FAULT_DIS                     ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_FAULT_DIS                     (MXC_V_SPI_INT_EN_FAULT_DIS << MXC_F_SPI_INT_EN_FAULT_POS)

#define MXC_V_SPI_INT_EN_FAULT_EN                      ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_FAULT_EN                      (MXC_V_SPI_INT_EN_FAULT_EN << MXC_F_SPI_INT_EN_FAULT_POS)

#define MXC_F_SPI_INT_EN_ABORT_POS                     9

#define MXC_F_SPI_INT_EN_ABORT                         ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS))

#define MXC_V_SPI_INT_EN_ABORT_DIS                     ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_ABORT_DIS                     (MXC_V_SPI_INT_EN_ABORT_DIS << MXC_F_SPI_INT_EN_ABORT_POS)

#define MXC_V_SPI_INT_EN_ABORT_EN                      ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_ABORT_EN                      (MXC_V_SPI_INT_EN_ABORT_EN << MXC_F_SPI_INT_EN_ABORT_POS)

#define MXC_F_SPI_INT_EN_M_DONE_POS                    11

#define MXC_F_SPI_INT_EN_M_DONE                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS))

#define MXC_V_SPI_INT_EN_M_DONE_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_M_DONE_DIS                    (MXC_V_SPI_INT_EN_M_DONE_DIS << MXC_F_SPI_INT_EN_M_DONE_POS)

#define MXC_V_SPI_INT_EN_M_DONE_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_M_DONE_EN                     (MXC_V_SPI_INT_EN_M_DONE_EN << MXC_F_SPI_INT_EN_M_DONE_POS)

#define MXC_F_SPI_INT_EN_TX_OVR_POS                    12

#define MXC_F_SPI_INT_EN_TX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS))

#define MXC_V_SPI_INT_EN_TX_OVR_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_TX_OVR_DIS                    (MXC_V_SPI_INT_EN_TX_OVR_DIS << MXC_F_SPI_INT_EN_TX_OVR_POS)

#define MXC_V_SPI_INT_EN_TX_OVR_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_TX_OVR_EN                     (MXC_V_SPI_INT_EN_TX_OVR_EN << MXC_F_SPI_INT_EN_TX_OVR_POS)

#define MXC_F_SPI_INT_EN_TX_UND_POS                    13

#define MXC_F_SPI_INT_EN_TX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS))

#define MXC_V_SPI_INT_EN_TX_UND_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_TX_UND_DIS                    (MXC_V_SPI_INT_EN_TX_UND_DIS << MXC_F_SPI_INT_EN_TX_UND_POS)

#define MXC_V_SPI_INT_EN_TX_UND_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_TX_UND_EN                     (MXC_V_SPI_INT_EN_TX_UND_EN << MXC_F_SPI_INT_EN_TX_UND_POS)

#define MXC_F_SPI_INT_EN_RX_OVR_POS                    14

#define MXC_F_SPI_INT_EN_RX_OVR                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS))

#define MXC_V_SPI_INT_EN_RX_OVR_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_RX_OVR_DIS                    (MXC_V_SPI_INT_EN_RX_OVR_DIS << MXC_F_SPI_INT_EN_RX_OVR_POS)

#define MXC_V_SPI_INT_EN_RX_OVR_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_RX_OVR_EN                     (MXC_V_SPI_INT_EN_RX_OVR_EN << MXC_F_SPI_INT_EN_RX_OVR_POS)

#define MXC_F_SPI_INT_EN_RX_UND_POS                    15

#define MXC_F_SPI_INT_EN_RX_UND                        ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS))

#define MXC_V_SPI_INT_EN_RX_UND_DIS                    ((uint32_t)0x0UL)

#define MXC_S_SPI_INT_EN_RX_UND_DIS                    (MXC_V_SPI_INT_EN_RX_UND_DIS << MXC_F_SPI_INT_EN_RX_UND_POS)

#define MXC_V_SPI_INT_EN_RX_UND_EN                     ((uint32_t)0x1UL)

#define MXC_S_SPI_INT_EN_RX_UND_EN                     (MXC_V_SPI_INT_EN_RX_UND_EN << MXC_F_SPI_INT_EN_RX_UND_POS)

#define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS                 0

#define MXC_F_SPI_WAKE_FL_TX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS))

#define MXC_V_SPI_WAKE_FL_TX_LEVEL_CLEAR               ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_FL_TX_LEVEL_CLEAR               (MXC_V_SPI_WAKE_FL_TX_LEVEL_CLEAR << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)

#define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS                 1

#define MXC_F_SPI_WAKE_FL_TX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS))

#define MXC_V_SPI_WAKE_FL_TX_EMPTY_CLEAR               ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_FL_TX_EMPTY_CLEAR               (MXC_V_SPI_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)

#define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS                 2

#define MXC_F_SPI_WAKE_FL_RX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS))

#define MXC_V_SPI_WAKE_FL_RX_LEVEL_CLEAR               ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_FL_RX_LEVEL_CLEAR               (MXC_V_SPI_WAKE_FL_RX_LEVEL_CLEAR << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)

#define MXC_F_SPI_WAKE_FL_RX_FULL_POS                  3

#define MXC_F_SPI_WAKE_FL_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS))

#define MXC_V_SPI_WAKE_FL_RX_FULL_CLEAR                ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_FL_RX_FULL_CLEAR                (MXC_V_SPI_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI_WAKE_FL_RX_FULL_POS)

#define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS                 0

#define MXC_F_SPI_WAKE_EN_TX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS))

#define MXC_V_SPI_WAKE_EN_TX_LEVEL_DIS                 ((uint32_t)0x0UL)

#define MXC_S_SPI_WAKE_EN_TX_LEVEL_DIS                 (MXC_V_SPI_WAKE_EN_TX_LEVEL_DIS << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)

#define MXC_V_SPI_WAKE_EN_TX_LEVEL_EN                  ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_EN_TX_LEVEL_EN                  (MXC_V_SPI_WAKE_EN_TX_LEVEL_EN << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)

#define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS                 1

#define MXC_F_SPI_WAKE_EN_TX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS))

#define MXC_V_SPI_WAKE_EN_TX_EMPTY_DIS                 ((uint32_t)0x0UL)

#define MXC_S_SPI_WAKE_EN_TX_EMPTY_DIS                 (MXC_V_SPI_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)

#define MXC_V_SPI_WAKE_EN_TX_EMPTY_EN                  ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_EN_TX_EMPTY_EN                  (MXC_V_SPI_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)

#define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS                 2

#define MXC_F_SPI_WAKE_EN_RX_LEVEL                     ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS))

#define MXC_V_SPI_WAKE_EN_RX_LEVEL_DIS                 ((uint32_t)0x0UL)

#define MXC_S_SPI_WAKE_EN_RX_LEVEL_DIS                 (MXC_V_SPI_WAKE_EN_RX_LEVEL_DIS << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)

#define MXC_V_SPI_WAKE_EN_RX_LEVEL_EN                  ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_EN_RX_LEVEL_EN                  (MXC_V_SPI_WAKE_EN_RX_LEVEL_EN << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)

#define MXC_F_SPI_WAKE_EN_RX_FULL_POS                  3

#define MXC_F_SPI_WAKE_EN_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS))

#define MXC_V_SPI_WAKE_EN_RX_FULL_DIS                  ((uint32_t)0x0UL)

#define MXC_S_SPI_WAKE_EN_RX_FULL_DIS                  (MXC_V_SPI_WAKE_EN_RX_FULL_DIS << MXC_F_SPI_WAKE_EN_RX_FULL_POS)

#define MXC_V_SPI_WAKE_EN_RX_FULL_EN                   ((uint32_t)0x1UL)

#define MXC_S_SPI_WAKE_EN_RX_FULL_EN                   (MXC_V_SPI_WAKE_EN_RX_FULL_EN << MXC_F_SPI_WAKE_EN_RX_FULL_POS)

#define MXC_F_SPI_STAT_BUSY_POS                        0

#define MXC_F_SPI_STAT_BUSY                            ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS))

#define MXC_V_SPI_STAT_BUSY_NOTACTIVE                  ((uint32_t)0x0UL)

#define MXC_S_SPI_STAT_BUSY_NOTACTIVE                  (MXC_V_SPI_STAT_BUSY_NOTACTIVE << MXC_F_SPI_STAT_BUSY_POS)

#define MXC_V_SPI_STAT_BUSY_ACTIVE                     ((uint32_t)0x1UL)

#define MXC_S_SPI_STAT_BUSY_ACTIVE                     (MXC_V_SPI_STAT_BUSY_ACTIVE << MXC_F_SPI_STAT_BUSY_POS)

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_

mxc_spi_regs_t::ctrl0
__IO uint32_t ctrl0
Definition: spi_regs.h:82

mxc_spi_regs_t::int_fl
__IO uint32_t int_fl
Definition: spi_regs.h:89

mxc_spi_regs_t::stat
__I uint32_t stat
Definition: spi_regs.h:93

mxc_spi_regs_t::fifo32
__IO uint32_t fifo32
Definition: spi_regs.h:78

mxc_spi_regs_t::wake_fl
__IO uint32_t wake_fl
Definition: spi_regs.h:91

mxc_spi_regs_t::int_en
__IO uint32_t int_en
Definition: spi_regs.h:90

mxc_spi_regs_t::ss_time
__IO uint32_t ss_time
Definition: spi_regs.h:85

mxc_spi_regs_t::dma
__IO uint32_t dma
Definition: spi_regs.h:88

mxc_spi_regs_t::ctrl1
__IO uint32_t ctrl1
Definition: spi_regs.h:83

mxc_spi_regs_t::clk_cfg
__IO uint32_t clk_cfg
Definition: spi_regs.h:86

mxc_spi_regs_t::ctrl2
__IO uint32_t ctrl2
Definition: spi_regs.h:84

mxc_spi_regs_t::wake_en
__IO uint32_t wake_en
Definition: spi_regs.h:92

mxc_spi_regs_t
Definition: spi_regs.h:76