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#define | MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000004UL) |
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#define | MXC_R_SPIXR_CTRL2 ((uint32_t)0x00000008UL) |
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#define | MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_SPIXR_SS_TIME ((uint32_t)0x00000010UL) |
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#define | MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) |
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#define | MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) |
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#define | MXC_R_SPIXR_INT_FL ((uint32_t)0x00000020UL) |
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#define | MXC_R_SPIXR_INT_EN ((uint32_t)0x00000024UL) |
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#define | MXC_R_SPIXR_WAKE_FL ((uint32_t)0x00000028UL) |
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#define | MXC_R_SPIXR_WAKE_EN ((uint32_t)0x0000002CUL) |
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#define | MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) |
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#define | MXC_R_SPIXR_XMEM_CTRL ((uint32_t)0x00000034UL) |
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#define | MXC_F_SPIXR_DATA32_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) |
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#define | MXC_F_SPIXR_DATA16_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) |
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#define | MXC_F_SPIXR_DATA8_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) |
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#define | MXC_F_SPIXR_CTRL1_ENABLE_POS 0 |
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#define | MXC_F_SPIXR_CTRL1_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_ENABLE_POS)) |
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#define | MXC_V_SPIXR_CTRL1_ENABLE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL1_ENABLE_DIS (MXC_V_SPIXR_CTRL1_ENABLE_DIS << MXC_F_SPIXR_CTRL1_ENABLE_POS) |
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#define | MXC_V_SPIXR_CTRL1_ENABLE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_ENABLE_EN (MXC_V_SPIXR_CTRL1_ENABLE_EN << MXC_F_SPIXR_CTRL1_ENABLE_POS) |
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#define | MXC_F_SPIXR_CTRL1_MASTER_POS 1 |
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#define | MXC_F_SPIXR_CTRL1_MASTER ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_MASTER_POS)) |
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#define | MXC_V_SPIXR_CTRL1_MASTER_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL1_MASTER_DIS (MXC_V_SPIXR_CTRL1_MASTER_DIS << MXC_F_SPIXR_CTRL1_MASTER_POS) |
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#define | MXC_V_SPIXR_CTRL1_MASTER_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_MASTER_EN (MXC_V_SPIXR_CTRL1_MASTER_EN << MXC_F_SPIXR_CTRL1_MASTER_POS) |
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#define | MXC_F_SPIXR_CTRL1_SS_IO_POS 4 |
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#define | MXC_F_SPIXR_CTRL1_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_IO_POS)) |
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#define | MXC_V_SPIXR_CTRL1_SS_IO_OUTPUT ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_IO_OUTPUT (MXC_V_SPIXR_CTRL1_SS_IO_OUTPUT << MXC_F_SPIXR_CTRL1_SS_IO_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_IO_INPUT ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_IO_INPUT (MXC_V_SPIXR_CTRL1_SS_IO_INPUT << MXC_F_SPIXR_CTRL1_SS_IO_POS) |
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#define | MXC_F_SPIXR_CTRL1_START_POS 5 |
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#define | MXC_F_SPIXR_CTRL1_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_START_POS)) |
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#define | MXC_V_SPIXR_CTRL1_START_START ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_START_START (MXC_V_SPIXR_CTRL1_START_START << MXC_F_SPIXR_CTRL1_START_POS) |
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#define | MXC_F_SPIXR_CTRL1_SS_CTRL_POS 8 |
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#define | MXC_F_SPIXR_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) |
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#define | MXC_V_SPIXR_CTRL1_SS_CTRL_DEASSERT ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_CTRL_DEASSERT (MXC_V_SPIXR_CTRL1_SS_CTRL_DEASSERT << MXC_F_SPIXR_CTRL1_SS_CTRL_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_CTRL_ASSERT ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_CTRL_ASSERT (MXC_V_SPIXR_CTRL1_SS_CTRL_ASSERT << MXC_F_SPIXR_CTRL1_SS_CTRL_POS) |
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#define | MXC_F_SPIXR_CTRL1_SS_POS 16 |
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#define | MXC_F_SPIXR_CTRL1_SS ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_POS)) |
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#define | MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS 0 |
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#define | MXC_F_SPIXR_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) |
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#define | MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS 16 |
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#define | MXC_F_SPIXR_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) |
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#define | MXC_F_SPIXR_CTRL3_CPHA_POS 0 |
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#define | MXC_F_SPIXR_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPHA_POS)) |
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#define | MXC_V_SPIXR_CTRL3_CPHA_RISINGEDGE ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_CPHA_RISINGEDGE (MXC_V_SPIXR_CTRL3_CPHA_RISINGEDGE << MXC_F_SPIXR_CTRL3_CPHA_POS) |
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#define | MXC_V_SPIXR_CTRL3_CPHA_FALLINGEDGE ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_CPHA_FALLINGEDGE (MXC_V_SPIXR_CTRL3_CPHA_FALLINGEDGE << MXC_F_SPIXR_CTRL3_CPHA_POS) |
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#define | MXC_F_SPIXR_CTRL3_CPOL_POS 1 |
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#define | MXC_F_SPIXR_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPOL_POS)) |
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#define | MXC_V_SPIXR_CTRL3_CPOL_NORMAL ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_CPOL_NORMAL (MXC_V_SPIXR_CTRL3_CPOL_NORMAL << MXC_F_SPIXR_CTRL3_CPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_CPOL_INVERTED ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_CPOL_INVERTED (MXC_V_SPIXR_CTRL3_CPOL_INVERTED << MXC_F_SPIXR_CTRL3_CPOL_POS) |
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#define | MXC_F_SPIXR_CTRL3_SCLK_INV_POS 4 |
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#define | MXC_F_SPIXR_CTRL3_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SCLK_INV_POS)) |
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#define | MXC_V_SPIXR_CTRL3_SCLK_INV_NORMAL ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_SCLK_INV_NORMAL (MXC_V_SPIXR_CTRL3_SCLK_INV_NORMAL << MXC_F_SPIXR_CTRL3_SCLK_INV_POS) |
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#define | MXC_F_SPIXR_CTRL3_NUMBITS_POS 8 |
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#define | MXC_F_SPIXR_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL3_NUMBITS_POS)) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_16BITS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_16BITS (MXC_V_SPIXR_CTRL3_NUMBITS_16BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_1BITS ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_1BITS (MXC_V_SPIXR_CTRL3_NUMBITS_1BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_2BITS ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_2BITS (MXC_V_SPIXR_CTRL3_NUMBITS_2BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_3BITS ((uint32_t)0x3UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_3BITS (MXC_V_SPIXR_CTRL3_NUMBITS_3BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_4BITS ((uint32_t)0x4UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_4BITS (MXC_V_SPIXR_CTRL3_NUMBITS_4BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_5BITS ((uint32_t)0x5UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_5BITS (MXC_V_SPIXR_CTRL3_NUMBITS_5BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_6BITS ((uint32_t)0x6UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_6BITS (MXC_V_SPIXR_CTRL3_NUMBITS_6BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_7BITS ((uint32_t)0x7UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_7BITS (MXC_V_SPIXR_CTRL3_NUMBITS_7BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_8BITS ((uint32_t)0x8UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_8BITS (MXC_V_SPIXR_CTRL3_NUMBITS_8BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_9BITS ((uint32_t)0x9UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_9BITS (MXC_V_SPIXR_CTRL3_NUMBITS_9BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_10BITS ((uint32_t)0xAUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_10BITS (MXC_V_SPIXR_CTRL3_NUMBITS_10BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_11BITS ((uint32_t)0xBUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_11BITS (MXC_V_SPIXR_CTRL3_NUMBITS_11BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_12BITS ((uint32_t)0xCUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_12BITS (MXC_V_SPIXR_CTRL3_NUMBITS_12BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_13BITS ((uint32_t)0xDUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_13BITS (MXC_V_SPIXR_CTRL3_NUMBITS_13BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_14BITS ((uint32_t)0xEUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_14BITS (MXC_V_SPIXR_CTRL3_NUMBITS_14BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_15BITS ((uint32_t)0xFUL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_15BITS (MXC_V_SPIXR_CTRL3_NUMBITS_15BITS << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS 12 |
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#define | MXC_F_SPIXR_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_F_SPIXR_CTRL3_THREE_WIRE_POS 15 |
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#define | MXC_F_SPIXR_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) |
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#define | MXC_V_SPIXR_CTRL3_THREE_WIRE_4WIRE ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_THREE_WIRE_4WIRE (MXC_V_SPIXR_CTRL3_THREE_WIRE_4WIRE << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS) |
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#define | MXC_V_SPIXR_CTRL3_THREE_WIRE_3WIRE ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_THREE_WIRE_3WIRE (MXC_V_SPIXR_CTRL3_THREE_WIRE_3WIRE << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS) |
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#define | MXC_F_SPIXR_CTRL3_SSPOL_POS 16 |
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#define | MXC_F_SPIXR_CTRL3_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SSPOL_POS)) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_ACTIVELOW ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_ACTIVELOW (MXC_V_SPIXR_CTRL3_SSPOL_ACTIVELOW << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_ACTIVEHIGH ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_ACTIVEHIGH (MXC_V_SPIXR_CTRL3_SSPOL_ACTIVEHIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_F_SPIXR_SS_TIME_SSACT1_POS 0 |
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#define | MXC_F_SPIXR_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT1_POS)) |
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#define | MXC_F_SPIXR_SS_TIME_SSACT2_POS 8 |
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#define | MXC_F_SPIXR_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSACT2_POS)) |
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#define | MXC_F_SPIXR_SS_TIME_SSINACT_POS 16 |
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#define | MXC_F_SPIXR_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_SS_TIME_SSINACT_POS)) |
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#define | MXC_F_SPIXR_BRG_CTRL_LO_POS 0 |
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#define | MXC_F_SPIXR_BRG_CTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_LO_POS)) |
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#define | MXC_F_SPIXR_BRG_CTRL_HI_POS 8 |
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#define | MXC_F_SPIXR_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_HI_POS)) |
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#define | MXC_F_SPIXR_BRG_CTRL_SCALE_POS 16 |
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#define | MXC_F_SPIXR_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV1 ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV1 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV1 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV2 ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV2 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV2 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV4 ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV4 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV4 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV8 ((uint32_t)0x3UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV8 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV8 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV16 ((uint32_t)0x4UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV16 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV16 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV32 ((uint32_t)0x5UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV32 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV32 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV64 ((uint32_t)0x6UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV64 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV64 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV128 ((uint32_t)0x7UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV128 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV128 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_V_SPIXR_BRG_CTRL_SCALE_DIV256 ((uint32_t)0x8UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_SCALE_DIV256 (MXC_V_SPIXR_BRG_CTRL_SCALE_DIV256 << MXC_F_SPIXR_BRG_CTRL_SCALE_POS) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) |
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#define | MXC_V_SPIXR_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_DMA_TX_FIFO_EN_DIS (MXC_V_SPIXR_DMA_TX_FIFO_EN_DIS << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS) |
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#define | MXC_V_SPIXR_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_TX_FIFO_EN_EN (MXC_V_SPIXR_DMA_TX_FIFO_EN_EN << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) |
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#define | MXC_V_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPIXR_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_DMA_EN_POS 15 |
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#define | MXC_F_SPIXR_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) |
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#define | MXC_V_SPIXR_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_DMA_TX_DMA_EN_DIS (MXC_V_SPIXR_DMA_TX_DMA_EN_DIS << MXC_F_SPIXR_DMA_TX_DMA_EN_POS) |
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#define | MXC_V_SPIXR_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_TX_DMA_EN_EN (MXC_V_SPIXR_DMA_TX_DMA_EN_EN << MXC_F_SPIXR_DMA_TX_DMA_EN_POS) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS 16 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) |
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#define | MXC_V_SPIXR_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_DMA_RX_FIFO_EN_DIS (MXC_V_SPIXR_DMA_RX_FIFO_EN_DIS << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS) |
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#define | MXC_V_SPIXR_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_RX_FIFO_EN_EN (MXC_V_SPIXR_DMA_RX_FIFO_EN_EN << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS 23 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) |
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#define | MXC_V_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPIXR_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_DMA_EN_POS 31 |
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#define | MXC_F_SPIXR_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) |
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#define | MXC_V_SPIXR_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_DMA_RX_DMA_EN_DIS (MXC_V_SPIXR_DMA_RX_DMA_EN_DIS << MXC_F_SPIXR_DMA_RX_DMA_EN_POS) |
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#define | MXC_V_SPIXR_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_DMA_RX_DMA_EN_EN (MXC_V_SPIXR_DMA_RX_DMA_EN_EN << MXC_F_SPIXR_DMA_RX_DMA_EN_POS) |
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#define | MXC_F_SPIXR_INT_FL_TX_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_INT_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_TX_LEVEL_CLEAR (MXC_V_SPIXR_INT_FL_TX_LEVEL_CLEAR << MXC_F_SPIXR_INT_FL_TX_LEVEL_POS) |
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#define | MXC_F_SPIXR_INT_FL_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_EMPTY_POS)) |
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#define | MXC_V_SPIXR_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPIXR_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPIXR_INT_FL_TX_EMPTY_POS) |
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#define | MXC_F_SPIXR_INT_FL_RX_LEVEL_POS 2 |
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#define | MXC_F_SPIXR_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_INT_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_RX_LEVEL_CLEAR (MXC_V_SPIXR_INT_FL_RX_LEVEL_CLEAR << MXC_F_SPIXR_INT_FL_RX_LEVEL_POS) |
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#define | MXC_F_SPIXR_INT_FL_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_FULL_POS)) |
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#define | MXC_V_SPIXR_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_RX_FULL_CLEAR (MXC_V_SPIXR_INT_FL_RX_FULL_CLEAR << MXC_F_SPIXR_INT_FL_RX_FULL_POS) |
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#define | MXC_F_SPIXR_INT_FL_SSA_POS 4 |
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#define | MXC_F_SPIXR_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSA_POS)) |
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#define | MXC_V_SPIXR_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_SSA_CLEAR (MXC_V_SPIXR_INT_FL_SSA_CLEAR << MXC_F_SPIXR_INT_FL_SSA_POS) |
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#define | MXC_F_SPIXR_INT_FL_SSD_POS 5 |
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#define | MXC_F_SPIXR_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_SSD_POS)) |
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#define | MXC_V_SPIXR_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_SSD_CLEAR (MXC_V_SPIXR_INT_FL_SSD_CLEAR << MXC_F_SPIXR_INT_FL_SSD_POS) |
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#define | MXC_F_SPIXR_INT_FL_FAULT_POS 8 |
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#define | MXC_F_SPIXR_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_FAULT_POS)) |
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#define | MXC_V_SPIXR_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_FAULT_CLEAR (MXC_V_SPIXR_INT_FL_FAULT_CLEAR << MXC_F_SPIXR_INT_FL_FAULT_POS) |
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#define | MXC_F_SPIXR_INT_FL_ABORT_POS 9 |
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#define | MXC_F_SPIXR_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_ABORT_POS)) |
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#define | MXC_V_SPIXR_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_ABORT_CLEAR (MXC_V_SPIXR_INT_FL_ABORT_CLEAR << MXC_F_SPIXR_INT_FL_ABORT_POS) |
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#define | MXC_F_SPIXR_INT_FL_M_DONE_POS 11 |
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#define | MXC_F_SPIXR_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_M_DONE_POS)) |
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#define | MXC_V_SPIXR_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_M_DONE_CLEAR (MXC_V_SPIXR_INT_FL_M_DONE_CLEAR << MXC_F_SPIXR_INT_FL_M_DONE_POS) |
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#define | MXC_F_SPIXR_INT_FL_TX_OVR_POS 12 |
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#define | MXC_F_SPIXR_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_OVR_POS)) |
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#define | MXC_V_SPIXR_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_TX_OVR_CLEAR (MXC_V_SPIXR_INT_FL_TX_OVR_CLEAR << MXC_F_SPIXR_INT_FL_TX_OVR_POS) |
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#define | MXC_F_SPIXR_INT_FL_TX_UND_POS 13 |
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#define | MXC_F_SPIXR_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_TX_UND_POS)) |
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#define | MXC_V_SPIXR_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_TX_UND_CLEAR (MXC_V_SPIXR_INT_FL_TX_UND_CLEAR << MXC_F_SPIXR_INT_FL_TX_UND_POS) |
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#define | MXC_F_SPIXR_INT_FL_RX_OVR_POS 14 |
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#define | MXC_F_SPIXR_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_OVR_POS)) |
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#define | MXC_V_SPIXR_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_RX_OVR_CLEAR (MXC_V_SPIXR_INT_FL_RX_OVR_CLEAR << MXC_F_SPIXR_INT_FL_RX_OVR_POS) |
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#define | MXC_F_SPIXR_INT_FL_RX_UND_POS 15 |
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#define | MXC_F_SPIXR_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_FL_RX_UND_POS)) |
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#define | MXC_V_SPIXR_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_FL_RX_UND_CLEAR (MXC_V_SPIXR_INT_FL_RX_UND_CLEAR << MXC_F_SPIXR_INT_FL_RX_UND_POS) |
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#define | MXC_F_SPIXR_INT_EN_TX_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_INT_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_LEVEL_DIS (MXC_V_SPIXR_INT_EN_TX_LEVEL_DIS << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS) |
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#define | MXC_V_SPIXR_INT_EN_TX_LEVEL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_LEVEL_EN (MXC_V_SPIXR_INT_EN_TX_LEVEL_EN << MXC_F_SPIXR_INT_EN_TX_LEVEL_POS) |
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#define | MXC_F_SPIXR_INT_EN_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS)) |
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#define | MXC_V_SPIXR_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_EMPTY_DIS (MXC_V_SPIXR_INT_EN_TX_EMPTY_DIS << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS) |
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#define | MXC_V_SPIXR_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_EMPTY_EN (MXC_V_SPIXR_INT_EN_TX_EMPTY_EN << MXC_F_SPIXR_INT_EN_TX_EMPTY_POS) |
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#define | MXC_F_SPIXR_INT_EN_RX_LEVEL_POS 2 |
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#define | MXC_F_SPIXR_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_INT_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_LEVEL_DIS (MXC_V_SPIXR_INT_EN_RX_LEVEL_DIS << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS) |
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#define | MXC_V_SPIXR_INT_EN_RX_LEVEL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_LEVEL_EN (MXC_V_SPIXR_INT_EN_RX_LEVEL_EN << MXC_F_SPIXR_INT_EN_RX_LEVEL_POS) |
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#define | MXC_F_SPIXR_INT_EN_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_FULL_POS)) |
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#define | MXC_V_SPIXR_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_FULL_DIS (MXC_V_SPIXR_INT_EN_RX_FULL_DIS << MXC_F_SPIXR_INT_EN_RX_FULL_POS) |
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#define | MXC_V_SPIXR_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_FULL_EN (MXC_V_SPIXR_INT_EN_RX_FULL_EN << MXC_F_SPIXR_INT_EN_RX_FULL_POS) |
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#define | MXC_F_SPIXR_INT_EN_SSA_POS 4 |
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#define | MXC_F_SPIXR_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSA_POS)) |
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#define | MXC_V_SPIXR_INT_EN_SSA_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_SSA_DIS (MXC_V_SPIXR_INT_EN_SSA_DIS << MXC_F_SPIXR_INT_EN_SSA_POS) |
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#define | MXC_V_SPIXR_INT_EN_SSA_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_SSA_EN (MXC_V_SPIXR_INT_EN_SSA_EN << MXC_F_SPIXR_INT_EN_SSA_POS) |
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#define | MXC_F_SPIXR_INT_EN_SSD_POS 5 |
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#define | MXC_F_SPIXR_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_SSD_POS)) |
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#define | MXC_V_SPIXR_INT_EN_SSD_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_SSD_DIS (MXC_V_SPIXR_INT_EN_SSD_DIS << MXC_F_SPIXR_INT_EN_SSD_POS) |
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#define | MXC_V_SPIXR_INT_EN_SSD_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_SSD_EN (MXC_V_SPIXR_INT_EN_SSD_EN << MXC_F_SPIXR_INT_EN_SSD_POS) |
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#define | MXC_F_SPIXR_INT_EN_FAULT_POS 8 |
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#define | MXC_F_SPIXR_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_FAULT_POS)) |
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#define | MXC_V_SPIXR_INT_EN_FAULT_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_FAULT_DIS (MXC_V_SPIXR_INT_EN_FAULT_DIS << MXC_F_SPIXR_INT_EN_FAULT_POS) |
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#define | MXC_V_SPIXR_INT_EN_FAULT_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_FAULT_EN (MXC_V_SPIXR_INT_EN_FAULT_EN << MXC_F_SPIXR_INT_EN_FAULT_POS) |
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#define | MXC_F_SPIXR_INT_EN_ABORT_POS 9 |
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#define | MXC_F_SPIXR_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_ABORT_POS)) |
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#define | MXC_V_SPIXR_INT_EN_ABORT_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_ABORT_DIS (MXC_V_SPIXR_INT_EN_ABORT_DIS << MXC_F_SPIXR_INT_EN_ABORT_POS) |
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#define | MXC_V_SPIXR_INT_EN_ABORT_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_ABORT_EN (MXC_V_SPIXR_INT_EN_ABORT_EN << MXC_F_SPIXR_INT_EN_ABORT_POS) |
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#define | MXC_F_SPIXR_INT_EN_M_DONE_POS 11 |
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#define | MXC_F_SPIXR_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_M_DONE_POS)) |
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#define | MXC_V_SPIXR_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_M_DONE_DIS (MXC_V_SPIXR_INT_EN_M_DONE_DIS << MXC_F_SPIXR_INT_EN_M_DONE_POS) |
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#define | MXC_V_SPIXR_INT_EN_M_DONE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_M_DONE_EN (MXC_V_SPIXR_INT_EN_M_DONE_EN << MXC_F_SPIXR_INT_EN_M_DONE_POS) |
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#define | MXC_F_SPIXR_INT_EN_TX_OVR_POS 12 |
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#define | MXC_F_SPIXR_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_OVR_POS)) |
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#define | MXC_V_SPIXR_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_OVR_DIS (MXC_V_SPIXR_INT_EN_TX_OVR_DIS << MXC_F_SPIXR_INT_EN_TX_OVR_POS) |
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#define | MXC_V_SPIXR_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_OVR_EN (MXC_V_SPIXR_INT_EN_TX_OVR_EN << MXC_F_SPIXR_INT_EN_TX_OVR_POS) |
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#define | MXC_F_SPIXR_INT_EN_TX_UND_POS 13 |
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#define | MXC_F_SPIXR_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_TX_UND_POS)) |
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#define | MXC_V_SPIXR_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_UND_DIS (MXC_V_SPIXR_INT_EN_TX_UND_DIS << MXC_F_SPIXR_INT_EN_TX_UND_POS) |
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#define | MXC_V_SPIXR_INT_EN_TX_UND_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_TX_UND_EN (MXC_V_SPIXR_INT_EN_TX_UND_EN << MXC_F_SPIXR_INT_EN_TX_UND_POS) |
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#define | MXC_F_SPIXR_INT_EN_RX_OVR_POS 14 |
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#define | MXC_F_SPIXR_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_OVR_POS)) |
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#define | MXC_V_SPIXR_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_OVR_DIS (MXC_V_SPIXR_INT_EN_RX_OVR_DIS << MXC_F_SPIXR_INT_EN_RX_OVR_POS) |
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#define | MXC_V_SPIXR_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_OVR_EN (MXC_V_SPIXR_INT_EN_RX_OVR_EN << MXC_F_SPIXR_INT_EN_RX_OVR_POS) |
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#define | MXC_F_SPIXR_INT_EN_RX_UND_POS 15 |
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#define | MXC_F_SPIXR_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INT_EN_RX_UND_POS)) |
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#define | MXC_V_SPIXR_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_UND_DIS (MXC_V_SPIXR_INT_EN_RX_UND_DIS << MXC_F_SPIXR_INT_EN_RX_UND_POS) |
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#define | MXC_V_SPIXR_INT_EN_RX_UND_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_INT_EN_RX_UND_EN (MXC_V_SPIXR_INT_EN_RX_UND_EN << MXC_F_SPIXR_INT_EN_RX_UND_POS) |
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#define | MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_WAKE_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_FL_TX_LEVEL_CLEAR (MXC_V_SPIXR_WAKE_FL_TX_LEVEL_CLEAR << MXC_F_SPIXR_WAKE_FL_TX_LEVEL_POS) |
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#define | MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS)) |
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#define | MXC_V_SPIXR_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPIXR_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPIXR_WAKE_FL_TX_EMPTY_POS) |
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#define | MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS 2 |
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#define | MXC_F_SPIXR_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_WAKE_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_FL_RX_LEVEL_CLEAR (MXC_V_SPIXR_WAKE_FL_RX_LEVEL_CLEAR << MXC_F_SPIXR_WAKE_FL_RX_LEVEL_POS) |
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#define | MXC_F_SPIXR_WAKE_FL_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_FL_RX_FULL_POS)) |
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#define | MXC_V_SPIXR_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPIXR_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPIXR_WAKE_FL_RX_FULL_POS) |
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#define | MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_WAKE_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_WAKE_EN_TX_LEVEL_DIS (MXC_V_SPIXR_WAKE_EN_TX_LEVEL_DIS << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS) |
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#define | MXC_V_SPIXR_WAKE_EN_TX_LEVEL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_EN_TX_LEVEL_EN (MXC_V_SPIXR_WAKE_EN_TX_LEVEL_EN << MXC_F_SPIXR_WAKE_EN_TX_LEVEL_POS) |
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#define | MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS)) |
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#define | MXC_V_SPIXR_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPIXR_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS) |
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#define | MXC_V_SPIXR_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_EN_TX_EMPTY_EN (MXC_V_SPIXR_WAKE_EN_TX_EMPTY_EN << MXC_F_SPIXR_WAKE_EN_TX_EMPTY_POS) |
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#define | MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS 2 |
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#define | MXC_F_SPIXR_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS)) |
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#define | MXC_V_SPIXR_WAKE_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_WAKE_EN_RX_LEVEL_DIS (MXC_V_SPIXR_WAKE_EN_RX_LEVEL_DIS << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS) |
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#define | MXC_V_SPIXR_WAKE_EN_RX_LEVEL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_EN_RX_LEVEL_EN (MXC_V_SPIXR_WAKE_EN_RX_LEVEL_EN << MXC_F_SPIXR_WAKE_EN_RX_LEVEL_POS) |
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#define | MXC_F_SPIXR_WAKE_EN_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS)) |
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#define | MXC_V_SPIXR_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_WAKE_EN_RX_FULL_DIS (MXC_V_SPIXR_WAKE_EN_RX_FULL_DIS << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS) |
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#define | MXC_V_SPIXR_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_WAKE_EN_RX_FULL_EN (MXC_V_SPIXR_WAKE_EN_RX_FULL_EN << MXC_F_SPIXR_WAKE_EN_RX_FULL_POS) |
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#define | MXC_F_SPIXR_STAT_BUSY_POS 0 |
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#define | MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) |
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#define | MXC_V_SPIXR_STAT_BUSY_NOTACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_STAT_BUSY_NOTACTIVE (MXC_V_SPIXR_STAT_BUSY_NOTACTIVE << MXC_F_SPIXR_STAT_BUSY_POS) |
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#define | MXC_V_SPIXR_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_STAT_BUSY_ACTIVE (MXC_V_SPIXR_STAT_BUSY_ACTIVE << MXC_F_SPIXR_STAT_BUSY_POS) |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD_POS 0 |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_RD_CMD_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD_POS 8 |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_WR_CMD_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS_POS 16 |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_XMEM_DCLKS_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS 31 |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) |
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#define | MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_XMEM_CTRL_XMEM_EN_DIS (MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_DIS << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS) |
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#define | MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_XMEM_CTRL_XMEM_EN_EN (MXC_V_SPIXR_XMEM_CTRL_XMEM_EN_EN << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS) |
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