gcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t scon;                 
    __IO uint32_t rst0;                 
    __IO uint32_t clk_ctrl;             
    __IO uint32_t pm;                   
    __R  uint32_t rsv_0x10_0x23[5];
    __IO uint32_t pclk_dis0;            
    __IO uint32_t mem_ctrl;             
    __IO uint32_t mem_zctrl;            
    __R  uint32_t rsv_0x30_0x3f[4];
    __IO uint32_t sys_stat;             
    __IO uint32_t rst1;                 
    __IO uint32_t pclk_dis1;            
    __IO uint32_t evten;                
    __I  uint32_t rev;                  
    __IO uint32_t sys_ie;               
} mxc_gcr_regs_t;
 
/* Register offsets for module GCR */
#define MXC_R_GCR_SCON                     ((uint32_t)0x00000000UL) 
#define MXC_R_GCR_RST0                     ((uint32_t)0x00000004UL) 
#define MXC_R_GCR_CLK_CTRL                 ((uint32_t)0x00000008UL) 
#define MXC_R_GCR_PM                       ((uint32_t)0x0000000CUL) 
#define MXC_R_GCR_PCLK_DIS0                ((uint32_t)0x00000024UL) 
#define MXC_R_GCR_MEM_CTRL                 ((uint32_t)0x00000028UL) 
#define MXC_R_GCR_MEM_ZCTRL                ((uint32_t)0x0000002CUL) 
#define MXC_R_GCR_SYS_STAT                 ((uint32_t)0x00000040UL) 
#define MXC_R_GCR_RST1                     ((uint32_t)0x00000044UL) 
#define MXC_R_GCR_PCLK_DIS1                ((uint32_t)0x00000048UL) 
#define MXC_R_GCR_EVTEN                    ((uint32_t)0x0000004CUL) 
#define MXC_R_GCR_REV                      ((uint32_t)0x00000050UL) 
#define MXC_R_GCR_SYS_IE                   ((uint32_t)0x00000054UL) 
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS             4 
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                 ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) 
#define MXC_F_GCR_SCON_FPU_DIS_POS                     5 
#define MXC_F_GCR_SCON_FPU_DIS                         ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) 
#define MXC_F_GCR_SCON_ICC0_FLUSH_POS                  6 
#define MXC_F_GCR_SCON_ICC0_FLUSH                      ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) 
#define MXC_F_GCR_SCON_SWD_DIS_POS                     14 
#define MXC_F_GCR_SCON_SWD_DIS                         ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) 
#define MXC_F_GCR_RST0_DMA_POS                         0 
#define MXC_F_GCR_RST0_DMA                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) 
#define MXC_F_GCR_RST0_WDT0_POS                        1 
#define MXC_F_GCR_RST0_WDT0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) 
#define MXC_F_GCR_RST0_GPIO0_POS                       2 
#define MXC_F_GCR_RST0_GPIO0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) 
#define MXC_F_GCR_RST0_TIMER0_POS                      5 
#define MXC_F_GCR_RST0_TIMER0                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) 
#define MXC_F_GCR_RST0_TIMER1_POS                      6 
#define MXC_F_GCR_RST0_TIMER1                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) 
#define MXC_F_GCR_RST0_TIMER2_POS                      7 
#define MXC_F_GCR_RST0_TIMER2                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) 
#define MXC_F_GCR_RST0_UART0_POS                       11 
#define MXC_F_GCR_RST0_UART0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) 
#define MXC_F_GCR_RST0_UART1_POS                       12 
#define MXC_F_GCR_RST0_UART1                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) 
#define MXC_F_GCR_RST0_SPI0_POS                        13 
#define MXC_F_GCR_RST0_SPI0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) 
#define MXC_F_GCR_RST0_SPI1_POS                        14 
#define MXC_F_GCR_RST0_SPI1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) 
#define MXC_F_GCR_RST0_I2C0_POS                        16 
#define MXC_F_GCR_RST0_I2C0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) 
#define MXC_F_GCR_RST0_RTC_POS                         17 
#define MXC_F_GCR_RST0_RTC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) 
#define MXC_F_GCR_RST0_SOFT_POS                        29 
#define MXC_F_GCR_RST0_SOFT                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) 
#define MXC_F_GCR_RST0_PERIPH_POS                      30 
#define MXC_F_GCR_RST0_PERIPH                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) 
#define MXC_F_GCR_RST0_SYSTEM_POS                      31 
#define MXC_F_GCR_RST0_SYSTEM                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) 
#define MXC_F_GCR_CLK_CTRL_PSC_POS                     6 
#define MXC_F_GCR_CLK_CTRL_PSC                         ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV1                    ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV1                    (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV2                    ((uint32_t)0x1UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV2                    (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV4                    ((uint32_t)0x2UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV4                    (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV8                    ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV8                    (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV16                   ((uint32_t)0x4UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV16                   (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV32                   ((uint32_t)0x5UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV32                   (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV64                   ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV64                   (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_V_GCR_CLK_CTRL_PSC_DIV128                  ((uint32_t)0x7UL) 
#define MXC_S_GCR_CLK_CTRL_PSC_DIV128                  (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) 
#define MXC_F_GCR_CLK_CTRL_CLKSEL_POS                  9 
#define MXC_F_GCR_CLK_CTRL_CLKSEL                      ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) 
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC                 ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC                 (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) 
#define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING             ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING             (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) 
#define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN                ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN                (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) 
#define MXC_F_GCR_CLK_CTRL_CLKRDY_POS                  13 
#define MXC_F_GCR_CLK_CTRL_CLKRDY                      ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) 
#define MXC_F_GCR_CLK_CTRL_X32K_EN_POS                 17 
#define MXC_F_GCR_CLK_CTRL_X32K_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) 
#define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS                 18 
#define MXC_F_GCR_CLK_CTRL_HIRC_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) 
#define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS                25 
#define MXC_F_GCR_CLK_CTRL_X32K_RDY                    ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) 
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS                26 
#define MXC_F_GCR_CLK_CTRL_HIRC_RDY                    ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) 
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS              29 
#define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY                  ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) 
#define MXC_F_GCR_PM_MODE_POS                          0 
#define MXC_F_GCR_PM_MODE                              ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) 
#define MXC_V_GCR_PM_MODE_ACTIVE                       ((uint32_t)0x0UL) 
#define MXC_S_GCR_PM_MODE_ACTIVE                       (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_SHUTDOWN                     ((uint32_t)0x3UL) 
#define MXC_S_GCR_PM_MODE_SHUTDOWN                     (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_BACKUP                       ((uint32_t)0x4UL) 
#define MXC_S_GCR_PM_MODE_BACKUP                       (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) 
#define MXC_F_GCR_PM_GPIOWK_EN_POS                     4 
#define MXC_F_GCR_PM_GPIOWK_EN                         ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) 
#define MXC_F_GCR_PM_RTCWK_EN_POS                      5 
#define MXC_F_GCR_PM_RTCWK_EN                          ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) 
#define MXC_F_GCR_PM_HFIOPD_POS                        15 
#define MXC_F_GCR_PM_HFIOPD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) 
#define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS                 0 
#define MXC_F_GCR_PCLK_DIS0_GPIO0D                     ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_DMAD_POS                   5 
#define MXC_F_GCR_PCLK_DIS0_DMAD                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) 
#define MXC_F_GCR_PCLK_DIS0_SPI0D_POS                  6 
#define MXC_F_GCR_PCLK_DIS0_SPI0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_SPI1D_POS                  7 
#define MXC_F_GCR_PCLK_DIS0_SPI1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_UART0D_POS                 9 
#define MXC_F_GCR_PCLK_DIS0_UART0D                     ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_UART1D_POS                 10 
#define MXC_F_GCR_PCLK_DIS0_UART1D                     ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_I2C0D_POS                  13 
#define MXC_F_GCR_PCLK_DIS0_I2C0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS                15 
#define MXC_F_GCR_PCLK_DIS0_TIMER0D                    ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS                16 
#define MXC_F_GCR_PCLK_DIS0_TIMER1D                    ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS                17 
#define MXC_F_GCR_PCLK_DIS0_TIMER2D                    ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) 
#define MXC_F_GCR_PCLK_DIS0_I2C1D_POS                  28 
#define MXC_F_GCR_PCLK_DIS0_I2C1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) 
#define MXC_F_GCR_MEM_CTRL_FWS_POS                     0 
#define MXC_F_GCR_MEM_CTRL_FWS                         ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) 
#define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS                 8 
#define MXC_F_GCR_MEM_CTRL_RAM0_LS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) 
#define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS                 9 
#define MXC_F_GCR_MEM_CTRL_RAM1_LS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) 
#define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS                 10 
#define MXC_F_GCR_MEM_CTRL_RAM2_LS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) 
#define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS                 11 
#define MXC_F_GCR_MEM_CTRL_RAM3_LS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) 
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS              12 
#define MXC_F_GCR_MEM_CTRL_ICACHE_RET                  ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) 
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS              0 
#define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO                  ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) 
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS            1 
#define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO                ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) 
#define MXC_F_GCR_SYS_STAT_ICECLOCK_POS                0 
#define MXC_F_GCR_SYS_STAT_ICECLOCK                    ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) 
#define MXC_F_GCR_RST1_I2C1_POS                        0 
#define MXC_F_GCR_RST1_I2C1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) 
#define MXC_F_GCR_PCLK_DIS1_FLCD_POS                   3 
#define MXC_F_GCR_PCLK_DIS1_FLCD                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) 
#define MXC_F_GCR_PCLK_DIS1_ICCD_POS                   11 
#define MXC_F_GCR_PCLK_DIS1_ICCD                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) 
#define MXC_F_GCR_EVTEN_DMAEVENT_POS                   0 
#define MXC_F_GCR_EVTEN_DMAEVENT                       ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) 
#define MXC_F_GCR_EVTEN_RX_EVT_POS                     1 
#define MXC_F_GCR_EVTEN_RX_EVT                         ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) 
#define MXC_F_GCR_REV_REVISION_POS                     0 
#define MXC_F_GCR_REV_REVISION                         ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) 
#define MXC_F_GCR_SYS_IE_ICEULIE_POS                   0 
#define MXC_F_GCR_SYS_IE_ICEULIE                       ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_GCR_REGS_H_