Boards Module

Board layout classes define the physical wiring between FPGA platforms and ADI evaluation boards — SPI bus assignments, GPIO mappings, and DTC include paths.

Board classes that support the unified model provide a to_board_model(cfg) method that produces a BoardModel from a pyadi-jif solver configuration. The model can be inspected and modified before rendering to DTS via BoardModelRenderer. See Board Model Module for the full API.

Board Layout Base

class adidt.boards.layout.layout

Bases: object

Common Layout Class for DT generation templates.

includes = ['']

template_filename: str | None = None

output_filename: str | None = None

use_plugin_mode: bool = True

platform_config: dict = {}

platform: str = ''

gen_dt_preprocess(**kwargs: Any) → dict[str, Any]: Pre-process template context before rendering; override to inject extra variables.

gen_dt(**kwargs)

Generate the DT file from configuration structs.

Raises:

Exception – If the template file does not exist.
Exception – If the output filename is not defined.

Parameters:

kwargs – Configuration structs.

gen_dt_from_model(model, config_source='board_model')

Render a BoardModel to a DTS file.

This is the BoardModel-based alternative to gen_dt(). It renders the model via BoardModelRenderer and writes a standalone DTS file with SPDX header and metadata.

Parameters:

model – A BoardModel instance.
config_source – Config source string for the metadata header.

Returns:

Path to the generated DTS file.

Return type:

str

gen_dt_from_config(cfg, config_source='jif_solver')

Generate DTS from raw solver config via BoardModel.

Convenience method that calls to_board_model() then gen_dt_from_model(). Subclasses must implement to_board_model(cfg).

Parameters:

cfg – Raw JIF solver configuration dict.
config_source – Config source string for metadata.

Returns:

Path to the generated DTS file.

Return type:

str

to_board_model(cfg: dict) → BoardModel: Build a BoardModel from config. Subclasses must override.

validate_and_default_fpga_config(cfg: dict) → dict

Validate and apply platform defaults for FPGA configuration.

Subclasses should override to add board-specific validation. The base implementation returns cfg unchanged.

map_jesd_subclass(name)

Map JESD204 subclass to integer.

Parameters:: name (str) – JESD subclass name.
Raises:: Exception – Invalid subclass name.
Returns:: JESD subclass integer.
Return type:: int

Evaluation Boards

DAQ2

class adidt.boards.daq2.daq2(platform='zcu102', kernel_path=None)

Bases: layout

clock = 'ad9523_1'

adc = 'ad9680'

dac = 'ad9144'

use_plugin_mode: bool = False

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/xilinx/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'default_fpga_adc_pll': 'XCVR_CPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'daq2_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts', 'base_dts_include': 'zynqmp-zcu102-rev10-fmcdaq2.dts', 'default_fpga_adc_pll': 'XCVR_CPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'daq2_zcu102.tmpl'}}

__init__(platform='zcu102', kernel_path=None)

Initialize DAQ2 board.

Parameters:

platform (str) – Target platform (‘zcu102’)
kernel_path (str, optional) – Path to Linux kernel source tree. If None, validation is skipped for backward compatibility.

Raises:

ValueError – If platform is not supported

template_filename: str | None = 'daq2.tmpl'

output_filename: str | None = 'daq2.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:: Include paths for dtc -i option
Return type:: list

validate_and_default_fpga_config(cfg: dict) → dict

Validate and apply platform defaults for FPGA configuration.

Parameters:: cfg (dict) – Configuration dictionary
Returns:: Configuration with FPGA defaults applied
Return type:: dict

make_ints(cfg, keys): Convert float-valued keys that are whole numbers to int in-place.

map_jesd_structs(cfg: dict) → tuple

Extract and annotate ADC and DAC JESD configuration dicts from the solver output.

Parameters:: cfg (dict) – Solver configuration containing converter_ADC/DAC and jesd_ADC/DAC keys.
Returns:: (adc dict, dac dict) each with a populated ‘jesd’ sub-dict.
Return type:: tuple

map_clocks_to_board_layout(cfg: dict) → tuple

Map JIF solver configuration to the DAQ2 board clock and JESD layout.

Parameters:: cfg (dict) – JIF solver configuration.
Returns:: (clock_config, adc_config, dac_config, fpga_config)
Return type:: tuple

to_board_model(cfg: dict) → BoardModel

Build a BoardModel from JIF solver configuration.

This maps the solver output through the existing board layout methods and produces a unified model that can be inspected, modified, and rendered via BoardModelRenderer.

Parameters:: cfg (dict) – JIF solver configuration (same dict passed to map_clocks_to_board_layout).
Returns:: Editable board model.
Return type:: BoardModel

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:: kwargs – Template rendering context
Returns:: Updated context with metadata
Return type:: dict

AD9081 FMC

class adidt.boards.ad9081_fmc.ad9081_fmc(platform='zcu102', kernel_path=None)

Bases: layout

AD9081 FMC board layout map for clocks and DSP

clock = 'HMC7044'

adc = 'ad9081_rx'

dac = 'ad9081_tx'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'vpk180': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vpk180-revA.dts', 'base_dts_include': 'versal-vpk180-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'ad9081_fmc_vpk180.tmpl'}, 'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'default_fpga_adc_pll': 'XCVR_QPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9081_fmc_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts', 'base_dts_include': 'zynqmp-zcu102-rev1.0.dts', 'default_fpga_adc_pll': 'XCVR_QPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'ad9081_fmc_zcu102.tmpl'}}

__init__(platform='zcu102', kernel_path=None)

Initialize AD9081 FMC board.

Parameters:

platform (str) – Target platform (‘zcu102’, ‘vpk180’, or ‘zc706’)
kernel_path (str, optional) – Path to Linux kernel source tree. If None, validation is skipped for backward compatibility.

Raises:

ValueError – If platform is not supported

template_filename: str | None = 'ad9081_fmc_zcu102.tmpl'

output_filename: str | None = 'ad9081_fmc_zcu102.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:: Include paths for dtc -i option
Return type:: list

validate_and_default_fpga_config(cfg: dict) → dict

Validate and apply platform defaults for FPGA configuration.

Parameters:: cfg (dict) – Configuration dictionary
Returns:: Configuration with FPGA defaults applied
Return type:: dict

make_ints(cfg, keys)

Convert keys in a dict to integers.

Parameters:

cfg (dict) – Configuration.
keys (list) – Keys to convert.

Returns:

Configuration with keys converted to integers.

Return type:

dict

map_jesd_structs(cfg: dict) → tuple

Map JIF configuration to integer structs.

Parameters:: cfg (dict) – JIF configuration.
Returns:: ADC JESD structs. dict: DAC JESD structs.
Return type:: dict

to_board_model(cfg: dict) → BoardModel

Build a BoardModel from JIF solver configuration.

This maps the solver output through the existing board layout methods and produces a unified model that can be inspected, modified, and rendered via BoardModelRenderer.

Parameters:: cfg (dict) – JIF solver configuration (same dict passed to map_clocks_to_board_layout).
Returns:: Editable board model.
Return type:: BoardModel

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:: kwargs – Template rendering context
Returns:: Updated context with metadata
Return type:: dict

map_clocks_to_board_layout(cfg: dict) → tuple

Map JIF configuration to board clock connection layout.

Parameters:: cfg (dict) – JIF configuration.
Returns:: Board clock connection layout.
Return type:: dict

AD9084 FMC

AD9084 FMC board device tree generation support.

This module provides device tree generation for the AD9084-FMCA-EBZ evaluation board on Versal platforms (VPK180, VCK190).

The AD9084 is a high-performance multi-channel RF transceiver that uses: - HMC7044 as the primary clock generator - ADF4382 as the device clock PLL - ADF4030 (AION) for JESD204C sysref distribution

Reference: linux/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts

class adidt.boards.ad9084_fmc.ad9084_fmc(platform='vpk180', kernel_path=None)

Bases: layout

AD9084 FMC board layout map for clocks and DSP

clock = 'HMC7044'

ext_clock = 'ADF4382'

sysref_provider = 'ADF4030'

adc = 'ad9084_rx'

dac = 'ad9084_tx'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'vck190': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vck190-revA.dts', 'base_dts_include': 'versal-vck190-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9084_fmc_vck190.tmpl'}, 'vcu118': {'arch': 'microblaze', 'base_dts_file': None, 'base_dts_include': 'vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts', 'default_fpga_adc_pll': 'XCVR_QPLL1', 'default_fpga_dac_pll': 'XCVR_QPLL1', 'jesd_phy': 'GTY', 'output_dir': None, 'spi_bus': 'axi_spi_2', 'template_filename': 'ad9084_fmc_vcu118.tmpl'}, 'vpk180': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vpk180-revA.dts', 'base_dts_include': 'versal-vpk180-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9084_fmc_vpk180.tmpl'}}

use_plugin_mode: bool = False

__init__(platform='vpk180', kernel_path=None)

Initialize AD9084 FMC board.

Parameters:

platform (str) – Target platform (‘vpk180’ or ‘vck190’)
kernel_path (str, optional) – Path to Linux kernel source tree. If None, uses LINUX_KERNEL_PATH env var or default path.

Raises:

ValueError – If platform is not supported
FileNotFoundError – If kernel path is invalid (when explicitly provided)

template_filename: str | None = 'ad9084_fmc_vpk180.tmpl'

output_filename: str | None = 'ad9084_fmc_vpk180.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:: Include paths for dtc -i option
Return type:: list

validate_and_default_fpga_config(cfg: dict) → dict

Validate and apply platform defaults for FPGA configuration.

Parameters:: cfg (dict) – Configuration dictionary
Returns:: Configuration with FPGA defaults applied
Return type:: dict

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:: kwargs – Template rendering context
Returns:: Updated context with metadata
Return type:: dict

to_board_model(cfg: dict) → BoardModel

Build a BoardModel from board configuration.

This maps the configuration through the existing board layout methods and produces a unified model that can be inspected, modified, and rendered via BoardModelRenderer.

Parameters:: cfg (dict) – Board configuration (same dict passed to map_clocks_to_board_layout).
Returns:: Editable board model.
Return type:: BoardModel

map_clocks_to_board_layout(cfg: dict) → tuple

Map configuration to board clock connection layout.

The AD9084 uses HMC7044 as the primary clock generator with the following channel assignments: - Channel 1: ADF4030_REFIN (125 MHz) - Channel 3: ADF4030_BSYNC0 (9.765 MHz) - Channel 8: CORE_CLK_TX (312.5 MHz) - Channel 9: CORE_CLK_RX (312.5 MHz) - Channel 10: FPGA_REFCLK (312.5 MHz) - Channel 11: CORE_CLK_RX_B (312.5 MHz) - Channel 12: CORE_CLK_TX_B (312.5 MHz)

Parameters:: cfg (dict) – Configuration dictionary
Returns:: (clock_config, adc_config, dac_config, fpga_config)
Return type:: tuple

ADRV9009 FMC

ADRV9009 FMC board device tree generation support (JSON-based).

This module provides JSON-based device tree generation for the ADRV9009 evaluation board on ZCU102 and ZC706 platforms.

The ADRV9009 is a highly integrated RF transceiver that uses: - AD9528 as the clock generator - JESD204B for high-speed data interface

This is a NEW implementation using JSON configuration (like AD9081), distinct from the existing profile-based implementations in adrv9009_pcbz.py.

Reference: linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts

class adidt.boards.adrv9009_fmc.adrv9009_fmc(platform='zcu102', kernel_path=None)

Bases: layout

ADRV9009 FMC board layout for JSON-based DT generation

clock = 'AD9528'

transceiver = 'ADRV9009'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/xilinx/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'clock_ref': 'clkc 16', 'default_fpga_orx_pll': 'XCVR_CPLL', 'default_fpga_rx_pll': 'XCVR_CPLL', 'default_fpga_tx_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'adrv9009_fmc_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts', 'base_dts_include': 'zynqmp-zcu102-rev1.0.dts', 'clock_ref': 'zynqmp_clk 71', 'default_fpga_orx_pll': 'XCVR_CPLL', 'default_fpga_rx_pll': 'XCVR_CPLL', 'default_fpga_tx_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'adrv9009_fmc_zcu102.tmpl'}}

use_plugin_mode: bool = False

__init__(platform='zcu102', kernel_path=None)

Initialize ADRV9009 FMC board.

Parameters:

platform (str) – Target platform (‘zcu102’ or ‘zc706’)
kernel_path (str, optional) – Path to Linux kernel source tree.

Raises:

ValueError – If platform is not supported
FileNotFoundError – If kernel path is invalid (when explicitly provided)

template_filename: str | None = 'adrv9009_fmc_zcu102.tmpl'

output_filename: str | None = 'adrv9009_fmc_zcu102.dts'

get_dtc_include_paths(): Get list of include paths for dtc compilation.

validate_and_default_fpga_config(cfg: dict) → dict: Validate and apply platform defaults for FPGA configuration.

to_board_model(cfg: dict) → BoardModel

Build a BoardModel from configuration.

This maps the configuration through the existing board layout methods and produces a unified model that can be inspected, modified, and rendered via BoardModelRenderer.

Parameters:: cfg (dict) – Configuration dictionary (same dict passed to map_clocks_to_board_layout).
Returns:: Editable board model.
Return type:: BoardModel

gen_dt_preprocess(**kwargs): Add metadata to template rendering context.

map_clocks_to_board_layout(cfg: dict) → tuple

Map configuration to board clock connection layout.

The ADRV9009 uses AD9528 as the clock generator with outputs: - Channel 13: DEV_CLK (device clock) - Channel 1: FMC_CLK (FPGA clock) - Channel 12: DEV_SYSREF (device sysref) - Channel 3: FMC_SYSREF (FPGA sysref)

Parameters:: cfg (dict) – Configuration dictionary
Returns:: (clock_config, rx_config, tx_config, orx_config, fpga_config)
Return type:: tuple

ADRV9009 PCB-Z

class adidt.boards.adrv9009_pcbz.adrv9009_pcbz

Bases: layout

ADRV9009-PCBZ FMC board layout map for clocks and DSP

template_filename: str | None = 'adi-adrv9009.dtsi'

output_filename: str | None = 'adi-adrv9009.dtsi'

profile = None

parse_profile(filename: Path)

Parse a profile file.

Parameters:: filename – Profile file name.
Returns:: Profile configuration.
Return type:: dict

parse_talInit(filename: Path)

Load JESD204 settings from a talise_config.c source file.

Parameters:: filename (Path) – Path to the talise_config.c file, or None to keep defaults.

gen_dt_preprocess(**kwargs): Build the Jinja2 template context from parsed clock and transceiver profiles.

ADRV9009 ZU11EG

class adidt.boards.adrv9009_zu11eg.adrv9009_zu11eg

Bases: layout

ADRV9009-ZU11EG SOM board layout map for clocks and DSP

clock = 'HMC7044'

adc = 'adrv9009_rx'

dac = 'adrv9009_tx'

template_filename: str | None = 'adrv9009_zu11eg.dts'

output_filename: str | None = 'adrv9009_zu11eg_out.dts'

profile = None

make_ints(cfg, keys)

Convert keys in a dict to integers.

Parameters:

cfg (dict) – Configuration.
keys (list) – Keys to convert.

Returns:

Configuration with keys converted to integers.

Return type:

dict

map_jesd_structs(cfg)

Map JIF configuration to integer structs.

Parameters:: cfg (dict) – JIF configuration.
Returns:: ADC JESD structs. dict: DAC JESD structs.
Return type:: dict

map_clocks_to_board_layout(cfg)

Map JIF configuration to board clock connection layout.

Parameters:: cfg (dict) – JIF configuration.
Returns:: Board clock connection layout.
Return type:: dict

parse_profile(filename)

Parse a profile file.

Parameters:: filename (str) – Profile file name.
Returns:: Profile configuration.
Return type:: dict

ADRV9361 Z7035

ADRV9361-Z7035 SOM board class for AD9361 SDR transceiver.

The ADRV9361-Z7035 is a System-on-Module pairing an AD9361 wideband SDR transceiver with a Zynq Z-7035 SoC. Like the FMComms boards it uses SPI + LVDS (no JESD204), so the device tree node is simple.

Two carrier variants are supported: - bob — breakout board (ADRV1CRR-BOB) - fmc — FMC carrier (ADRV1CRR-FMC)

class adidt.boards.adrv9361_z7035.adrv9361_z7035(platform: str = 'bob', kernel_path: str | None = None)

Bases: fmcomms_fmc

ADRV9361-Z7035 SOM board class.

PLATFORM_CONFIGS = {'bob': {'arch': 'arm', 'base_dts_include': 'zynq-adrv9361-z7035-bob.dts', 'output_dir': 'generated_dts', 'spi_bus': 'spi0'}, 'fmc': {'arch': 'arm', 'base_dts_include': 'zynq-adrv9361-z7035-fmc.dts', 'output_dir': 'generated_dts', 'spi_bus': 'spi0'}}

to_board_model(cfg: dict) → BoardModel

Build a BoardModel for the ADRV9361-Z7035 SOM.

Reuses the AD9361 SPI device pattern from fmcomms_fmc with board-specific compatible string.

ADRV9364 Z7020

ADRV9364-Z7020 SOM board class for AD9364 SDR transceiver.

The ADRV9364-Z7020 is a System-on-Module pairing an AD9364 (1x1 TRX) SDR transceiver with a Zynq Z-7020 SoC. It uses SPI + LVDS (no JESD204), identical to the ADRV9361-Z7035 but with a single TX/RX path.

Supported carrier: - bob — breakout board (ADRV1CRR-BOB)

class adidt.boards.adrv9364_z7020.adrv9364_z7020(platform: str = 'bob', kernel_path: str | None = None)

Bases: adrv9361_z7035

ADRV9364-Z7020 SOM board class.

PLATFORM_CONFIGS = {'bob': {'arch': 'arm', 'base_dts_include': 'zynq-adrv9364-z7020-bob.dts', 'output_dir': 'generated_dts', 'spi_bus': 'spi0'}}

to_board_model(cfg: dict) → BoardModel: Build a BoardModel for the ADRV9364-Z7020 SOM.