Parts Module

The parts module provides Python abstractions for configuring individual ADI components via their device tree properties.

Clock Device Tree Interface

class adidt.parts.clock_dt.clock_dt

Bases: object

Mixin with shared helpers for building clock-chip device tree nodes.

handle_64bit(prop, node, num)

Set a DT property to num, splitting into two 32-bit words when the value exceeds 31 bits.

set_clock_node(parent, clk, name, reg)

Append a new channel subnode to parent with standard clock properties.

setter(node, prop_name, value)

Set a property on node, appending it if it does not yet exist.

update_existing_clock_node(node, clk)

Update the channel-divider and driver defaults on an existing clock subnode.

set_vcxo(node, vcxo)

Set the adi,vcxo-frequency property on node, raising if the value is fractional.

get_prop_across_nodes(node, prop)

Return a list of a given property’s value from every direct child node.

get_node_by_prop(parent, prop, value)

Return the first child node of parent whose property matches value, or False.

get_used_clocks(node)

Return the list of clock nodes referenced by the ‘clocks’ phandle property of node.

Clock Generators and Distributors

HMC7044

class adidt.parts.hmc7044.hmc7044_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt, clock_dt

HMC7044 Device tree map class.

pulse_gen_modes = {'GEN_16_PULSE': 5, 'GEN_1_PULSE': 1, 'GEN_2_PULSE': 2, 'GEN_4_PULSE': 3, 'GEN_8_PULSE': 4, 'GEN_CONT_PULSE': 7, 'GEN_LEVEL_SENSITIVE': 0}
driver_modes = {'CML': 0, 'CMOS': 3, 'LVDS': 2, 'LVPECL': 1}
driver_impedances = {'100_OHM': 1, '50_OHM': 3, 'DISABLE': 0}
output_mux_modes = {'ANALOG_DELAY': 1, 'CH_DIV': 0, 'GROUP_PAIR': 3, 'VCO_CLOCK': 4}
cmos_outputs_reg_field_map = {0: {'N': 0, 'P': 1}, 1: {'N': 1, 'P': 0}, 2: {'N': 1, 'P': 0}, 3: {'N': 0, 'P': 1}, 4: {'N': 1, 'P': 0}, 5: {'N': 0, 'P': 1}, 6: {'N': 0, 'P': 1}, 7: {'N': 1, 'P': 0}, 8: {'N': 1, 'P': 0}, 9: {'N': 0, 'P': 1}, 10: {'N': 0, 'P': 1}, 11: {'N': 1, 'P': 0}, 12: {'N': 1, 'P': 0}, 13: {'N': 0, 'P': 1}}
set_clock_node(parent, clk, name, reg)

Append an HMC7044 channel subnode with divider and driver settings to parent.

set_dt_node_from_config(node: Node, config: Dict, append=False)

Set HMC7044 node from JIF configuration

Parameters:

  • node (fdt.Node) – Device tree parent node of hmc7044

  • config (Dict) – Configuration struct generated from JIF

  • append (boolean) – Enable appending to subnode, if false the existing are removed

AD9523-1

class adidt.parts.ad9523_1.ad9523_1_dt

Bases: clock_dt

AD9523-1 Device tree map class.

compatible_id = 'adi,ad9523-1'
set_dt_node_from_config(node: Node, config: Dict, append=False)

Set AD9523-1 node from JIF configuration

Parameters:

  • node (fdt.Node) – Device tree parent node of AD9523-1

  • config (Dict) – Configuration struct generated from JIF

  • append (boolean) – Enable appending to subnode, if false the existing are removed

AD9528

adidt.parts.ad9528.parse_profile(filename)

Parse an AD9528 Profile Configuration Wizard file into a structured dict.

Parameters:

filename – Path to the AD9528 profile (.txt) file.

Returns:

Parsed profile with keys ‘pll1’, ‘pll2’, ‘out’, and ‘sysref’.

Return type:

dict

AD9545

class adidt.parts.ad9545.ad9545_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt

AD9545 Device tree map class.

pll_clock_id = 1
out_clock_id = 0
set_clock_node(parent, clk, name, reg)

Append a minimal output-clk subnode to parent for the given register address.

pll_set_rate(pll_nr: int, rate: int, node: Node)

Rate change for PLLs is trickier, it is found in the assigned-clocks/assigned-clock-rates

output_set_rate(output_nr: int, rate: int, node: Node)

Rate change for PLLs is trickier, it is found in the assigned-clocks/assigned-clock-rates

set_source_priorities_from_config(node: Node, config: Dict)

Update PLL profile priority values from the JIF config for each configured PLL.

Parameters:

  • node (fdt.Node) – AD9545 device tree node.

  • config (Dict) – JIF configuration dict containing PLL0/PLL1 entries.

set_dt_node_from_config(node: Node, config: Dict, append=False)

Set AD9545 node from JIF configuration

Parameters:

  • node (fdt.Node) – Device tree parent node of ad9545

  • config (Dict) – Configuration struct generated from JIF

RF Transceivers

ADRV9009

adidt.parts.adrv9009.parse_talInit(file)

Parse a talise_config.c file and return the talInit configuration dict.

adidt.parts.adrv9009.handle_ints(val)

Convert a value to an unsigned 32-bit integer, correctly wrapping negatives.

adidt.parts.adrv9009.handle_channel_enable(data: dict, key: str, default: int = 0)

Translate a TAL_RX*/TAL_TX*/TAL_ORX* string value in data[key] to its integer code.

Parameters:

  • data (dict) – Profile dict to update in-place.

  • key (str) – Key whose value should be translated.

  • default (int) – Integer value to use when key is absent.

Raises:

ValueError – If the key’s string value is not a recognised channel-enable token.

adidt.parts.adrv9009.parse_profile(filename)

Parse an ADRV9009 Profile Configuration Wizard file into a structured dict.

Converts the ADI profile XML format to a dict with rx, tx, orx, lpbk, and clocks sub-dicts ready for use in device tree template rendering.

Parameters:

filename – Path to the profile (.xml) file.

Returns:

Parsed profile with keys ‘rx’, ‘tx’, ‘orx’, ‘lpbk’, ‘clocks’.

Return type:

dict

class adidt.parts.adrv9009.adrv9009_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt

ADRV9009 device tree map class.

set_dt_node_from_config(node: Node, config: Dict, profile: Dict, append=False)

Set ADRV9009 node from JIF configuration

Parameters:

  • node (fdt.Node) – Device tree parent node of adrv9009

  • config (Dict) – Configuration struct generated from JIF

  • append (boolean) – Enable appending to subnode, if false the existing are removed