pyadi-jif: Python interface for the ADI JESD Interface Framework

This project tries to simplify JESD204 configuration exploration and validation for ADI JESD based converters and clock chips with different FPGA vendors.

Contents:

• Installing PyADI-JIF
• Usage Flows
• Data converters
• Clock chips
• FPGAs
• Supported Parts
• JESD204 Definitions
• Reference APIs
• Drawings
• Developer documentation