AD463x

Overview

The purpose of this testbench is to validate the serial interface functionality of the projects/ad4630_fmc reference design.

The entire HDL documentation can be found here AD4630-FMC HDL project.

Block design

The testbench block design includes part of the AD4630-FMC HDL reference design, along with VIPs used for clocking, reset, PS and DDR simulations.

Block diagram

The data path and clock domains are depicted in the below diagram:

Configuration parameters and modes

The following parameters of this project that can be configured:

The CLK_MODE configuration parameter defines clocking mode of the device’s digital interface:

• 0 - SPI mode;

• 1 - Echo-clock or Master clock mode.

The NUM_OF_CHANNEL configuration parameter defines the number of ADC channels:

• 1 - AD403X devices;

• 2 - AD463X/ADAQ42XX devices (default).

The LANES_PER_CHANNEL configuration parameter defines the number of MISO lanes per channel of the SPI interface:

• 1 - 1 lane per channel: Interleaved mode or single lane per channel;

• 2 - 2 lanes per channel;

• 4 - 4 lanes per channel (default).

The CAPTURE_ZONE configuration parameter defines the capture zone of the next sample. There are two capture zones:

• 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns

• 2 - from the next consecutive CNV positive edge +20ns until the second next consecutive CNV positive edge -20ns

The DDR_EN configuration parameter defines the type of data transfer. In echo and master clock mode the SDI lines can have Single or Double Data Rates:

• 0 - MISO runs on SDR

• 1 - MISO runs on DDR.

The INTERLEAVE_MODE configuration parameter defines whether the interleaved mode is enabled or disabled. Interleaved mode can be only used for NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (AD463X). Enabling INTERLEAVE_MODE for any other configuration is invalid.

• 0 - interleave mode disabled, each channel has their own MISO lanes. (default);

• 1 - interleave mode enabled, the AD463X ADC share the same MISO lanes.

Configuration files

The following configuration files are available:

Configuration mode	NUM_OF_CHANNEL	CLK_MODE	CAPTURE_ZONE	LANES_PER_CHANNEL	DDR_EN	NO_REORDER
cfg_ch1_cm0_cz1_sdi1_ddr0_nr1	1	0	1	1	0	1
cfg_ch1_cm0_cz1_sdi2_ddr0_nr0	1	0	1	2	0	0
cfg_ch1_cm0_cz1_sdi4_ddr0_nr0	1	0	1	4	0	0
cfg_ch1_cm1_cz2_sdi1_ddr0_nr1	1	1	2	1	0	1
cfg_ch1_cm1_cz2_sdi2_ddr0_nr0	1	1	2	2	0	0
cfg_ch1_cm1_cz2_sdi2_ddr1_nr0	1	1	2	2	1	0
cfg_ch1_cm1_cz2_sdi4_ddr0_nr0	1	1	2	4	0	0
cfg_ch1_cm1_cz2_sdi4_ddr1_nr0	1	1	2	4	1	0
cfg_ch2_cm0_cz1_sdi1_ddr0_nr0	2	0	1	1	0	0
cfg_ch2_cm0_cz1_sdi1_ddr0_nr1	2	0	1	1	0	1
cfg_ch2_cm0_cz1_sdi2_ddr0_nr0	2	0	1	2	0	0
cfg_ch2_cm0_cz1_sdi4_ddr0_nr0	2	0	1	4	0	0
cfg_ch2_cm1_cz2_sdi1_ddr0_nr0	2	1	2	1	0	0
cfg_ch2_cm1_cz2_sdi1_ddr0_nr1	2	1	2	1	0	1
cfg_ch2_cm1_cz2_sdi2_ddr0_nr0	2	1	2	2	0	0
cfg_ch2_cm1_cz2_sdi2_ddr1_nr0	2	1	2	2	1	0
cfg_ch2_cm1_cz2_sdi4_ddr0_nr0	2	1	2	4	0	0
cfg_ch2_cm1_cz2_sdi4_ddr1_nr0	2	1	2	4	1	0

Tests

The following test program file is available:

Test program	Usage
test_program	Tests the serial interface capabilities.

Available configurations & tests combinations

The test program is compatible with all of the above mentioned configurations.

Clock scheme

The design supports the following interface and clock modes both in SDR and DDR:

Mode	1 Lane per channel	2 Lane per channel	4 lane per channel
SPI mode	yes	yes	yes
Echo Clock mode	yes	yes	yes

CPU/Memory interconnect addresses

Below are the CPU/Memory interconnect addresses used in this project:

Instance	Address
spi_ad463x_axi_regmap	0x44A0_0000
axi_ad463x_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
cnv_generator	0x44B0_0000
sync_generator*	0x44C0_0000

Legend

* instantiated, but only used for ADAQ4224 with isolated power supply

Interrupts

Below are the Programmable Logic interrupts used in this project:

Instance name	HDL
axi_ad463x_dma	13
spi_ad463x	12

Test stimulus

The test program is structured into several tests as follows:

Environment bringup

The steps of the environment bringup are:

• Create the environment

• Start the environment

• Start the clocks

• Assert the resets

Sanity test

This test is used to check the communication with the AXI REGMAP module of the AD463X SPI Engine interface, by reading the core VERSION register, along with writing and reading the SCRATCH register. This is also done for the PWM and DMA.

FIFO SPI test

The FIFO SPI test verifies the simple serial transfers, made through the Execution module. This task already generates two SPI transactions when interleaved mode is enabled.

The steps of this test are:

• A watchdog is initialized, which ensures that the simulation doesn’t run off into infinity. It also prints all successfull transfers and which one started hanging

• Generate a FIFO transaction

• Capture and compare the results, reading the register of the AXI SPI Engine

Offload SPI test

The Offload SPI test verifies the Offload module functionality.

The steps of this test are:

• Configure the DMA

• Configure the Offload module

• Start the Offload module

• Capture and compare the Offload SDI data

Stop the environment

• Stop the sequencers

• Stop the clocks

• Stop the watchdog

Building the testbench

The testbench is built upon ADI’s generic HDL reference design framework. ADI does not distribute compiled files of these projects so they must be built from the sources available here and here, with the specified hierarchy described Set up the Testbenches repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

Example 1

Build all the possible combinations of tests and configurations, using only the command line.

user@analog:~$

cd testbenches/project/ad463x

user@analog:~/testbenches/project/ad463x$

make

Example 2

Build all the possible combinations of tests and configurations, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/ad463x

user@analog:~/testbenches/project/ad463x$

make MODE=gui

Example 3

Build a particular combination of test and configuration, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/ad463x

user@analog:~/testbenches/project/ad463x$

make MODE=gui CFG=cfg_ch1_cm0_cz1_sdi1_ddr0_nr1 TST=test_program

The built projects can be found in the runs folder, where each configuration specific build has it’s own folder named after the configuration file’s name. Example: if the following command was run for a single configuration in the clean folder (no runs folder available):

make CFG=cfg_ch2_cm0_cz2_sdi4_ddr0_nr1

Then the subfolder under runs name will be:

cfg_ch2_cm0_cz2_sdi4_ddr0_nr1

Resources

HDL related dependencies forming the DUT

IP name	Source code link	Documentation link
AD463X_DATA_CAPTURE	library/ad463x_data_capture	—
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_AXIS_REORDER	library/spi_engine/spi_axis_reorder	—
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

Testbenches related dependencies

Common with most testbenches:

SV dependency name	Source code link	Documentation link
IRQ_HANDLER	library/utilities/irq_handler_pkg.sv	—
LOGGER_PKG	library/utilities/logger_pkg.sv	—
M_AXI_SEQUENCER	library/vip/amd/axi/m_axi_sequencer.sv	—
REG_ACCESSOR	library/regmaps/reg_accessor.sv	—
S_AXI_SEQUENCER	library/vip/amd/axi/s_axi_sequencer.sv	—
TEST_HARNESS_ENV	library/utilities/test_harness_env.sv	Test Harness
UTILS	library/utilities/utils.svh	—
WATCHDOG	library/drivers/common/watchdog.sv	Watchdog

Testbench specific dependencies:

SV dependency name	Source code link	Documentation link
ADI_REGMAP_CLKGEN_PKG	library/regmaps/adi_regmap_clkgen_pkg.sv	—
ADI_REGMAP_DMAC_PKG	library/regmaps/adi_regmap_dmac_pkg.sv	—
ADI_REGMAP_PKG	library/regmaps/adi_regmap_pkg.sv	—
ADI_REGMAP_PWM_GEN_PKG	library/regmaps/adi_regmap_pwm_gen_pkg.sv	—
ADI_REGMAP_SPI_ENGINE_PKG	library/regmaps/adi_regmap_spi_engine_pkg.sv	—
DMA_TRANS	library/drivers/dmac/dma_trans.sv	—
DMAC_API	library/drivers/dmac/dmac_api.sv	—
M_AXIS_SEQUENCER	library/vip/amd/axis/m_axis_sequencer.sv	—
S_AXIS_SEQUENCER	library/vip/amd/axis/s_axis_sequencer.sv	—

More information

• ADI Testbenches User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.