QUAD_ADAQ77681 HDL project

Overview

The ADAQ7768-1 is a 24-bit precision data acquisition (DAQ) μModule system that encapsulates signal conditioning, conversion, and processing blocks into one system-in-package (SiP) design for the rapid development of highly compact, high-performance precision DAQ systems.

The ADAQ7768-1 consists of a low-noise, low-bias current, high-bandwidth programmable gain instrumentation amplifier (PGIA) also capable of signal amplification and signal attenuation while maintaining high input impedance, a fourth-order, low-noise, linear phase anti-aliasing filter, a low-noise, low-distortion, high-bandwidth ADC driver plus an optional linearity boost buffer. Also, contains a high-performance medium bandwidth 24-bit Σ-Δ ADC with programmable digital filter,a low-noise, low-dropout linear regulator, reference buffers and critical passive components required for the signal chain.

The ADAQ7768-1 supports fully differential input signal with a maximum range of ±12.6 V. It has an input common-mode voltage range of ±12 V with excellent common-mode rejection ratio (CMRR). The input signal is fully buffered with very low input bias current of 2 pA typical. This allows easy input impedance matching and enables the ADAQ7768-1 to directly interface to sensors with high output impedance.

The analog-to-digital converter (ADC) inside the ADAQ7768-1 is a high-performance, 24-bit precision, single-channel sigma-delta converter with excellent AC performance and DC precision, and the throughput rate of 256 kSPS from a 16.384 MHz MCLK.

The ADAQ7768-1 device has an operating temperature range of −40°C to +85°C and is available in a 12.00 mm × 6.00 mm 84-ball CSP_BGA package with an 0.80 mm ball pitch, which makes it ideal for multiple channel applications.

Supported boards

QUAD_AD77681 EvalPlus Signal Chain Board

Supported devices

ADAQ7768-1

Supported carriers

ZedBoard on FMC slot

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

QUAD_ADAQ77681

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance	Zynq
quad_adaq77681_axi_regmap	0x44A0_0000
axi_qadc_dma	0x44A3_0000
mclk_clkgen	0x44B0_0000

I2C connections

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	quad_adaq77681	0

GPIOs

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
quad_adaq77681_out_drdy	INOUT	45	99
qadc_pgood[3:0]	INOUT	44:41	98:95
qadc_muxa[1:0]	INOUT	40:39	94:93
qadc_muxb[1:0]	INOUT	38:37	92:91
qadc_muxc[1:0]	INOUT	36:35	90:89
qadc_muxd[1:0]	INOUT	34:33	88:87
qadc_sync	INOUT	32	86

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_qadc_dma	13	57	89
quad_adaq77681	12	56	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

user@analog:~$ cd hdl/projects/quad_adaq77681/zed
user@analog:~/hdl/projects/quad_adaq77681/zed$ make

A more comprehensive build guide can be found in the Build an HDL project user guide.

HDL related

quad_adaq77681 HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	here
AXI_DMAC	library/axi_dmac	here
AXI_HDMI_TX	library/axi_hdmi_tx	here
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	here
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	here
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	here
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	here
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	here
SYSID_ROM	library/sysid_rom	here
UTIL_I2C_MIXER	library/util_i2c_mixer	—

SPI Engine Framework documentation

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.