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#define | MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) |
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#define | MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) |
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#define | MXC_R_UART_STAT ((uint32_t)0x00000008UL) |
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#define | MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) |
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#define | MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) |
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#define | MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) |
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#define | MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) |
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#define | MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) |
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#define | MXC_R_UART_DMA ((uint32_t)0x00000020UL) |
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#define | MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) |
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#define | MXC_F_UART_CTRL0_ENABLE_POS 0 |
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#define | MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) |
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#define | MXC_V_UART_CTRL0_ENABLE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_ENABLE_DIS (MXC_V_UART_CTRL0_ENABLE_DIS << MXC_F_UART_CTRL0_ENABLE_POS) |
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#define | MXC_V_UART_CTRL0_ENABLE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_ENABLE_EN (MXC_V_UART_CTRL0_ENABLE_EN << MXC_F_UART_CTRL0_ENABLE_POS) |
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#define | MXC_F_UART_CTRL0_PARITY_EN_POS 1 |
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#define | MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) |
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#define | MXC_V_UART_CTRL0_PARITY_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_PARITY_EN_DIS (MXC_V_UART_CTRL0_PARITY_EN_DIS << MXC_F_UART_CTRL0_PARITY_EN_POS) |
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#define | MXC_V_UART_CTRL0_PARITY_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_PARITY_EN_EN (MXC_V_UART_CTRL0_PARITY_EN_EN << MXC_F_UART_CTRL0_PARITY_EN_POS) |
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#define | MXC_F_UART_CTRL0_PARITY_MODE_POS 2 |
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#define | MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) |
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#define | MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) |
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#define | MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) |
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#define | MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) |
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#define | MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) |
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#define | MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) |
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#define | MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) |
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#define | MXC_F_UART_CTRL0_PARITY_LVL_POS 4 |
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#define | MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) |
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#define | MXC_V_UART_CTRL0_PARITY_LVL_ZERO ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_PARITY_LVL_ZERO (MXC_V_UART_CTRL0_PARITY_LVL_ZERO << MXC_F_UART_CTRL0_PARITY_LVL_POS) |
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#define | MXC_V_UART_CTRL0_PARITY_LVL_ONE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_PARITY_LVL_ONE (MXC_V_UART_CTRL0_PARITY_LVL_ONE << MXC_F_UART_CTRL0_PARITY_LVL_POS) |
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#define | MXC_F_UART_CTRL0_TXFLUSH_POS 5 |
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#define | MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) |
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#define | MXC_V_UART_CTRL0_TXFLUSH_NOP ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_TXFLUSH_NOP (MXC_V_UART_CTRL0_TXFLUSH_NOP << MXC_F_UART_CTRL0_TXFLUSH_POS) |
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#define | MXC_V_UART_CTRL0_TXFLUSH_FLUSH ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_TXFLUSH_FLUSH (MXC_V_UART_CTRL0_TXFLUSH_FLUSH << MXC_F_UART_CTRL0_TXFLUSH_POS) |
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#define | MXC_F_UART_CTRL0_RXFLUSH_POS 6 |
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#define | MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) |
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#define | MXC_V_UART_CTRL0_RXFLUSH_NOP ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_RXFLUSH_NOP (MXC_V_UART_CTRL0_RXFLUSH_NOP << MXC_F_UART_CTRL0_RXFLUSH_POS) |
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#define | MXC_V_UART_CTRL0_RXFLUSH_FLUSH ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_RXFLUSH_FLUSH (MXC_V_UART_CTRL0_RXFLUSH_FLUSH << MXC_F_UART_CTRL0_RXFLUSH_POS) |
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#define | MXC_F_UART_CTRL0_BITACC_POS 7 |
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#define | MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) |
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#define | MXC_V_UART_CTRL0_BITACC_FRAME ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_BITACC_FRAME (MXC_V_UART_CTRL0_BITACC_FRAME << MXC_F_UART_CTRL0_BITACC_POS) |
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#define | MXC_V_UART_CTRL0_BITACC_BIT ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_BITACC_BIT (MXC_V_UART_CTRL0_BITACC_BIT << MXC_F_UART_CTRL0_BITACC_POS) |
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#define | MXC_F_UART_CTRL0_SIZE_POS 8 |
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#define | MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) |
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#define | MXC_V_UART_CTRL0_SIZE_5BIT_DATA ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_SIZE_5BIT_DATA (MXC_V_UART_CTRL0_SIZE_5BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) |
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#define | MXC_V_UART_CTRL0_SIZE_6BIT_DATA ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_SIZE_6BIT_DATA (MXC_V_UART_CTRL0_SIZE_6BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) |
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#define | MXC_V_UART_CTRL0_SIZE_7BIT_DATA ((uint32_t)0x2UL) |
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#define | MXC_S_UART_CTRL0_SIZE_7BIT_DATA (MXC_V_UART_CTRL0_SIZE_7BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) |
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#define | MXC_V_UART_CTRL0_SIZE_8BIT_DATA ((uint32_t)0x3UL) |
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#define | MXC_S_UART_CTRL0_SIZE_8BIT_DATA (MXC_V_UART_CTRL0_SIZE_8BIT_DATA << MXC_F_UART_CTRL0_SIZE_POS) |
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#define | MXC_F_UART_CTRL0_STOP_POS 10 |
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#define | MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) |
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#define | MXC_V_UART_CTRL0_STOP_1_STOPBITS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_STOP_1_STOPBITS (MXC_V_UART_CTRL0_STOP_1_STOPBITS << MXC_F_UART_CTRL0_STOP_POS) |
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#define | MXC_V_UART_CTRL0_STOP_2_STOPBITS ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_STOP_2_STOPBITS (MXC_V_UART_CTRL0_STOP_2_STOPBITS << MXC_F_UART_CTRL0_STOP_POS) |
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#define | MXC_F_UART_CTRL0_FLOW_POS 11 |
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#define | MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) |
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#define | MXC_V_UART_CTRL0_FLOW_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_FLOW_DIS (MXC_V_UART_CTRL0_FLOW_DIS << MXC_F_UART_CTRL0_FLOW_POS) |
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#define | MXC_V_UART_CTRL0_FLOW_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_FLOW_EN (MXC_V_UART_CTRL0_FLOW_EN << MXC_F_UART_CTRL0_FLOW_POS) |
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#define | MXC_F_UART_CTRL0_FLOWPOL_POS 12 |
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#define | MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) |
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#define | MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_LOW ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_FLOWPOL_ACTIVE_LOW (MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_LOW << MXC_F_UART_CTRL0_FLOWPOL_POS) |
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#define | MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_FLOWPOL_ACTIVE_HIGH (MXC_V_UART_CTRL0_FLOWPOL_ACTIVE_HIGH << MXC_F_UART_CTRL0_FLOWPOL_POS) |
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#define | MXC_F_UART_CTRL0_NULLMOD_POS 13 |
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#define | MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) |
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#define | MXC_V_UART_CTRL0_NULLMOD_NORMAL ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_NULLMOD_NORMAL (MXC_V_UART_CTRL0_NULLMOD_NORMAL << MXC_F_UART_CTRL0_NULLMOD_POS) |
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#define | MXC_V_UART_CTRL0_NULLMOD_SWAPPED ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_NULLMOD_SWAPPED (MXC_V_UART_CTRL0_NULLMOD_SWAPPED << MXC_F_UART_CTRL0_NULLMOD_POS) |
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#define | MXC_F_UART_CTRL0_BREAK_POS 14 |
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#define | MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) |
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#define | MXC_V_UART_CTRL0_BREAK_NORMAL ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_BREAK_NORMAL (MXC_V_UART_CTRL0_BREAK_NORMAL << MXC_F_UART_CTRL0_BREAK_POS) |
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#define | MXC_V_UART_CTRL0_BREAK_BREAK ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_BREAK_BREAK (MXC_V_UART_CTRL0_BREAK_BREAK << MXC_F_UART_CTRL0_BREAK_POS) |
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#define | MXC_F_UART_CTRL0_CLK_SEL_POS 15 |
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#define | MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) |
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#define | MXC_V_UART_CTRL0_CLK_SEL_PERIPH_CLK ((uint32_t)0x0UL) |
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#define | MXC_S_UART_CTRL0_CLK_SEL_PERIPH_CLK (MXC_V_UART_CTRL0_CLK_SEL_PERIPH_CLK << MXC_F_UART_CTRL0_CLK_SEL_POS) |
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#define | MXC_V_UART_CTRL0_CLK_SEL_ALT_CLK ((uint32_t)0x1UL) |
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#define | MXC_S_UART_CTRL0_CLK_SEL_ALT_CLK (MXC_V_UART_CTRL0_CLK_SEL_ALT_CLK << MXC_F_UART_CTRL0_CLK_SEL_POS) |
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#define | MXC_F_UART_CTRL0_TO_CNT_POS 16 |
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#define | MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) |
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#define | MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 |
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#define | MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) |
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#define | MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 |
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#define | MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) |
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#define | MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 |
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#define | MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) |
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#define | MXC_F_UART_STAT_TX_BUSY_POS 0 |
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#define | MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) |
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#define | MXC_V_UART_STAT_TX_BUSY_IDLE ((uint32_t)0x0UL) |
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#define | MXC_S_UART_STAT_TX_BUSY_IDLE (MXC_V_UART_STAT_TX_BUSY_IDLE << MXC_F_UART_STAT_TX_BUSY_POS) |
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#define | MXC_V_UART_STAT_TX_BUSY_BUSY ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_TX_BUSY_BUSY (MXC_V_UART_STAT_TX_BUSY_BUSY << MXC_F_UART_STAT_TX_BUSY_POS) |
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#define | MXC_F_UART_STAT_RX_BUSY_POS 1 |
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#define | MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) |
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#define | MXC_V_UART_STAT_RX_BUSY_IDLE ((uint32_t)0x0UL) |
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#define | MXC_S_UART_STAT_RX_BUSY_IDLE (MXC_V_UART_STAT_RX_BUSY_IDLE << MXC_F_UART_STAT_RX_BUSY_POS) |
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#define | MXC_V_UART_STAT_RX_BUSY_BUSY ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_RX_BUSY_BUSY (MXC_V_UART_STAT_RX_BUSY_BUSY << MXC_F_UART_STAT_RX_BUSY_POS) |
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#define | MXC_F_UART_STAT_PARITY_POS 2 |
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#define | MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) |
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#define | MXC_V_UART_STAT_PARITY_0 ((uint32_t)0x0UL) |
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#define | MXC_S_UART_STAT_PARITY_0 (MXC_V_UART_STAT_PARITY_0 << MXC_F_UART_STAT_PARITY_POS) |
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#define | MXC_V_UART_STAT_PARITY_1 ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_PARITY_1 (MXC_V_UART_STAT_PARITY_1 << MXC_F_UART_STAT_PARITY_POS) |
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#define | MXC_F_UART_STAT_BREAK_POS 3 |
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#define | MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) |
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#define | MXC_V_UART_STAT_BREAK_RECV ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_BREAK_RECV (MXC_V_UART_STAT_BREAK_RECV << MXC_F_UART_STAT_BREAK_POS) |
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#define | MXC_F_UART_STAT_RX_EMPTY_POS 4 |
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#define | MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) |
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#define | MXC_V_UART_STAT_RX_EMPTY_EMPTY ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_RX_EMPTY_EMPTY (MXC_V_UART_STAT_RX_EMPTY_EMPTY << MXC_F_UART_STAT_RX_EMPTY_POS) |
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#define | MXC_F_UART_STAT_RX_FULL_POS 5 |
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#define | MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) |
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#define | MXC_V_UART_STAT_RX_FULL_FULL ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_RX_FULL_FULL (MXC_V_UART_STAT_RX_FULL_FULL << MXC_F_UART_STAT_RX_FULL_POS) |
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#define | MXC_F_UART_STAT_TX_EMPTY_POS 6 |
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#define | MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) |
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#define | MXC_V_UART_STAT_TX_EMPTY_EMPTY ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_TX_EMPTY_EMPTY (MXC_V_UART_STAT_TX_EMPTY_EMPTY << MXC_F_UART_STAT_TX_EMPTY_POS) |
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#define | MXC_F_UART_STAT_TX_FULL_POS 7 |
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#define | MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) |
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#define | MXC_V_UART_STAT_TX_FULL_FULL ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_TX_FULL_FULL (MXC_V_UART_STAT_TX_FULL_FULL << MXC_F_UART_STAT_TX_FULL_POS) |
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#define | MXC_F_UART_STAT_RX_NUM_POS 8 |
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#define | MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) |
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#define | MXC_F_UART_STAT_TX_NUM_POS 16 |
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#define | MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) |
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#define | MXC_F_UART_STAT_RX_TO_POS 24 |
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#define | MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) |
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#define | MXC_V_UART_STAT_RX_TO_EXPIRED ((uint32_t)0x1UL) |
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#define | MXC_S_UART_STAT_RX_TO_EXPIRED (MXC_V_UART_STAT_RX_TO_EXPIRED << MXC_F_UART_STAT_RX_TO_POS) |
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#define | MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 |
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#define | MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) |
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#define | MXC_V_UART_INT_EN_RX_FRAME_ERROR_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_RX_FRAME_ERROR_DIS (MXC_V_UART_INT_EN_RX_FRAME_ERROR_DIS << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS) |
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#define | MXC_V_UART_INT_EN_RX_FRAME_ERROR_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_RX_FRAME_ERROR_EN (MXC_V_UART_INT_EN_RX_FRAME_ERROR_EN << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS) |
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#define | MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 |
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#define | MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) |
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#define | MXC_V_UART_INT_EN_RX_PARITY_ERROR_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_RX_PARITY_ERROR_DIS (MXC_V_UART_INT_EN_RX_PARITY_ERROR_DIS << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS) |
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#define | MXC_V_UART_INT_EN_RX_PARITY_ERROR_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_RX_PARITY_ERROR_EN (MXC_V_UART_INT_EN_RX_PARITY_ERROR_EN << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS) |
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#define | MXC_F_UART_INT_EN_CTS_POS 2 |
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#define | MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) |
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#define | MXC_V_UART_INT_EN_CTS_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_CTS_DIS (MXC_V_UART_INT_EN_CTS_DIS << MXC_F_UART_INT_EN_CTS_POS) |
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#define | MXC_V_UART_INT_EN_CTS_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_CTS_EN (MXC_V_UART_INT_EN_CTS_EN << MXC_F_UART_INT_EN_CTS_POS) |
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#define | MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 |
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#define | MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) |
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#define | MXC_V_UART_INT_EN_RX_OVERRUN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_RX_OVERRUN_DIS (MXC_V_UART_INT_EN_RX_OVERRUN_DIS << MXC_F_UART_INT_EN_RX_OVERRUN_POS) |
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#define | MXC_V_UART_INT_EN_RX_OVERRUN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_RX_OVERRUN_EN (MXC_V_UART_INT_EN_RX_OVERRUN_EN << MXC_F_UART_INT_EN_RX_OVERRUN_POS) |
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#define | MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 |
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#define | MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) |
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#define | MXC_V_UART_INT_EN_RX_FIFO_LVL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_RX_FIFO_LVL_DIS (MXC_V_UART_INT_EN_RX_FIFO_LVL_DIS << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS) |
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#define | MXC_V_UART_INT_EN_RX_FIFO_LVL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_RX_FIFO_LVL_EN (MXC_V_UART_INT_EN_RX_FIFO_LVL_EN << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS) |
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#define | MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 |
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#define | MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) |
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#define | MXC_V_UART_INT_EN_TX_FIFO_AE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_TX_FIFO_AE_DIS (MXC_V_UART_INT_EN_TX_FIFO_AE_DIS << MXC_F_UART_INT_EN_TX_FIFO_AE_POS) |
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#define | MXC_V_UART_INT_EN_TX_FIFO_AE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_TX_FIFO_AE_EN (MXC_V_UART_INT_EN_TX_FIFO_AE_EN << MXC_F_UART_INT_EN_TX_FIFO_AE_POS) |
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#define | MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 |
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#define | MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) |
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#define | MXC_V_UART_INT_EN_TX_FIFO_LVL_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_TX_FIFO_LVL_DIS (MXC_V_UART_INT_EN_TX_FIFO_LVL_DIS << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS) |
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#define | MXC_V_UART_INT_EN_TX_FIFO_LVL_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_TX_FIFO_LVL_EN (MXC_V_UART_INT_EN_TX_FIFO_LVL_EN << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS) |
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#define | MXC_F_UART_INT_EN_BREAK_POS 7 |
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#define | MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) |
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#define | MXC_V_UART_INT_EN_BREAK_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_BREAK_DIS (MXC_V_UART_INT_EN_BREAK_DIS << MXC_F_UART_INT_EN_BREAK_POS) |
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#define | MXC_V_UART_INT_EN_BREAK_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_BREAK_EN (MXC_V_UART_INT_EN_BREAK_EN << MXC_F_UART_INT_EN_BREAK_POS) |
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#define | MXC_F_UART_INT_EN_RX_TO_POS 8 |
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#define | MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) |
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#define | MXC_V_UART_INT_EN_RX_TO_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_RX_TO_DIS (MXC_V_UART_INT_EN_RX_TO_DIS << MXC_F_UART_INT_EN_RX_TO_POS) |
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#define | MXC_V_UART_INT_EN_RX_TO_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_RX_TO_EN (MXC_V_UART_INT_EN_RX_TO_EN << MXC_F_UART_INT_EN_RX_TO_POS) |
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#define | MXC_F_UART_INT_EN_LAST_BREAK_POS 9 |
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#define | MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) |
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#define | MXC_V_UART_INT_EN_LAST_BREAK_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_INT_EN_LAST_BREAK_DIS (MXC_V_UART_INT_EN_LAST_BREAK_DIS << MXC_F_UART_INT_EN_LAST_BREAK_POS) |
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#define | MXC_V_UART_INT_EN_LAST_BREAK_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_EN_LAST_BREAK_EN (MXC_V_UART_INT_EN_LAST_BREAK_EN << MXC_F_UART_INT_EN_LAST_BREAK_POS) |
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#define | MXC_F_UART_INT_FL_FRAME_POS 0 |
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#define | MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) |
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#define | MXC_V_UART_INT_FL_FRAME_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_FRAME_ACTIVE (MXC_V_UART_INT_FL_FRAME_ACTIVE << MXC_F_UART_INT_FL_FRAME_POS) |
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#define | MXC_F_UART_INT_FL_PARITY_POS 1 |
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#define | MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) |
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#define | MXC_V_UART_INT_FL_PARITY_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_PARITY_ACTIVE (MXC_V_UART_INT_FL_PARITY_ACTIVE << MXC_F_UART_INT_FL_PARITY_POS) |
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#define | MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 |
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#define | MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) |
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#define | MXC_V_UART_INT_FL_CTS_CHANGE_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_CTS_CHANGE_ACTIVE (MXC_V_UART_INT_FL_CTS_CHANGE_ACTIVE << MXC_F_UART_INT_FL_CTS_CHANGE_POS) |
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#define | MXC_F_UART_INT_FL_RX_OVR_POS 3 |
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#define | MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) |
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#define | MXC_V_UART_INT_FL_RX_OVR_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_RX_OVR_ACTIVE (MXC_V_UART_INT_FL_RX_OVR_ACTIVE << MXC_F_UART_INT_FL_RX_OVR_POS) |
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#define | MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 |
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#define | MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) |
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#define | MXC_V_UART_INT_FL_RX_FIFO_LVL_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_RX_FIFO_LVL_ACTIVE (MXC_V_UART_INT_FL_RX_FIFO_LVL_ACTIVE << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS) |
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#define | MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 |
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#define | MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) |
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#define | MXC_V_UART_INT_FL_TX_FIFO_AE_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_TX_FIFO_AE_ACTIVE (MXC_V_UART_INT_FL_TX_FIFO_AE_ACTIVE << MXC_F_UART_INT_FL_TX_FIFO_AE_POS) |
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#define | MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 |
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#define | MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) |
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#define | MXC_V_UART_INT_FL_TX_FIFO_LVL_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_TX_FIFO_LVL_ACTIVE (MXC_V_UART_INT_FL_TX_FIFO_LVL_ACTIVE << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS) |
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#define | MXC_F_UART_INT_FL_BREAK_POS 7 |
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#define | MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) |
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#define | MXC_V_UART_INT_FL_BREAK_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_BREAK_ACTIVE (MXC_V_UART_INT_FL_BREAK_ACTIVE << MXC_F_UART_INT_FL_BREAK_POS) |
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#define | MXC_F_UART_INT_FL_RX_TO_POS 8 |
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#define | MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) |
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#define | MXC_V_UART_INT_FL_RX_TO_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_RX_TO_ACTIVE (MXC_V_UART_INT_FL_RX_TO_ACTIVE << MXC_F_UART_INT_FL_RX_TO_POS) |
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#define | MXC_F_UART_INT_FL_LAST_BREAK_POS 9 |
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#define | MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) |
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#define | MXC_V_UART_INT_FL_LAST_BREAK_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_UART_INT_FL_LAST_BREAK_ACTIVE (MXC_V_UART_INT_FL_LAST_BREAK_ACTIVE << MXC_F_UART_INT_FL_LAST_BREAK_POS) |
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#define | MXC_F_UART_BAUD0_IBAUD_POS 0 |
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#define | MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) |
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#define | MXC_F_UART_BAUD0_CLKDIV_POS 16 |
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#define | MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) |
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#define | MXC_V_UART_BAUD0_CLKDIV_DIV128 ((uint32_t)0x0UL) |
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#define | MXC_S_UART_BAUD0_CLKDIV_DIV128 (MXC_V_UART_BAUD0_CLKDIV_DIV128 << MXC_F_UART_BAUD0_CLKDIV_POS) |
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#define | MXC_V_UART_BAUD0_CLKDIV_DIV64 ((uint32_t)0x1UL) |
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#define | MXC_S_UART_BAUD0_CLKDIV_DIV64 (MXC_V_UART_BAUD0_CLKDIV_DIV64 << MXC_F_UART_BAUD0_CLKDIV_POS) |
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#define | MXC_V_UART_BAUD0_CLKDIV_DIV32 ((uint32_t)0x2UL) |
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#define | MXC_S_UART_BAUD0_CLKDIV_DIV32 (MXC_V_UART_BAUD0_CLKDIV_DIV32 << MXC_F_UART_BAUD0_CLKDIV_POS) |
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#define | MXC_V_UART_BAUD0_CLKDIV_DIV16 ((uint32_t)0x3UL) |
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#define | MXC_S_UART_BAUD0_CLKDIV_DIV16 (MXC_V_UART_BAUD0_CLKDIV_DIV16 << MXC_F_UART_BAUD0_CLKDIV_POS) |
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#define | MXC_V_UART_BAUD0_CLKDIV_DIV8 ((uint32_t)0x4UL) |
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#define | MXC_S_UART_BAUD0_CLKDIV_DIV8 (MXC_V_UART_BAUD0_CLKDIV_DIV8 << MXC_F_UART_BAUD0_CLKDIV_POS) |
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#define | MXC_F_UART_BAUD1_DBAUD_POS 0 |
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#define | MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0x7FUL << MXC_F_UART_BAUD1_DBAUD_POS)) |
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#define | MXC_F_UART_FIFO_FIFO_POS 0 |
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#define | MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) |
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#define | MXC_F_UART_DMA_TXDMA_EN_POS 0 |
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#define | MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) |
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#define | MXC_V_UART_DMA_TXDMA_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_DMA_TXDMA_EN_DIS (MXC_V_UART_DMA_TXDMA_EN_DIS << MXC_F_UART_DMA_TXDMA_EN_POS) |
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#define | MXC_V_UART_DMA_TXDMA_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_DMA_TXDMA_EN_EN (MXC_V_UART_DMA_TXDMA_EN_EN << MXC_F_UART_DMA_TXDMA_EN_POS) |
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#define | MXC_F_UART_DMA_RXDMA_EN_POS 1 |
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#define | MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) |
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#define | MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) |
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#define | MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) |
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#define | MXC_F_UART_DMA_TXDMA_LVL_POS 8 |
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#define | MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) |
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#define | MXC_F_UART_DMA_RXDMA_LVL_POS 16 |
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#define | MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) |
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#define | MXC_F_UART_TXFIFO_DATA_POS 0 |
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#define | MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) |
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