gcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t scon;                 
    __IO uint32_t rstr0;                
    __IO uint32_t clkcn;                
    __IO uint32_t pm;                   
    __R  uint32_t rsv_0x10_0x17[2];
    __IO uint32_t pckdiv;               
    __R  uint32_t rsv_0x1c_0x23[2];
    __IO uint32_t perckcn0;             
    __IO uint32_t memckcn;              
    __IO uint32_t memzcn;               
    __R  uint32_t rsv_0x30_0x3f[4];
    __IO uint32_t sysst;                
    __IO uint32_t rstr1;                
    __IO uint32_t perckcn1;             
    __IO uint32_t event_en;             
    __I  uint32_t revision;             
    __IO uint32_t syssie;               
    __R  uint32_t rsv_0x58_0x63[3];
    __IO uint32_t ecc_er;               
    __IO uint32_t ecc_ced;              
    __IO uint32_t ecc_irqen;            
    __IO uint32_t ecc_errad;            
    __IO uint32_t btle_ldocr;           
    __IO uint32_t btle_ldodcr;          
    __R  uint32_t rsv_0x7c;
    __IO uint32_t gp0;                  
    __IO uint32_t apb_async;            
} mxc_gcr_regs_t;
 
/* Register offsets for module GCR */
#define MXC_R_GCR_SCON                     ((uint32_t)0x00000000UL) 
#define MXC_R_GCR_RSTR0                    ((uint32_t)0x00000004UL) 
#define MXC_R_GCR_CLKCN                    ((uint32_t)0x00000008UL) 
#define MXC_R_GCR_PM                       ((uint32_t)0x0000000CUL) 
#define MXC_R_GCR_PCKDIV                   ((uint32_t)0x00000018UL) 
#define MXC_R_GCR_PERCKCN0                 ((uint32_t)0x00000024UL) 
#define MXC_R_GCR_MEMCKCN                  ((uint32_t)0x00000028UL) 
#define MXC_R_GCR_MEMZCN                   ((uint32_t)0x0000002CUL) 
#define MXC_R_GCR_SYSST                    ((uint32_t)0x00000040UL) 
#define MXC_R_GCR_RSTR1                    ((uint32_t)0x00000044UL) 
#define MXC_R_GCR_PERCKCN1                 ((uint32_t)0x00000048UL) 
#define MXC_R_GCR_EVENT_EN                 ((uint32_t)0x0000004CUL) 
#define MXC_R_GCR_REVISION                 ((uint32_t)0x00000050UL) 
#define MXC_R_GCR_SYSSIE                   ((uint32_t)0x00000054UL) 
#define MXC_R_GCR_ECC_ER                   ((uint32_t)0x00000064UL) 
#define MXC_R_GCR_ECC_CED                  ((uint32_t)0x00000068UL) 
#define MXC_R_GCR_ECC_IRQEN                ((uint32_t)0x0000006CUL) 
#define MXC_R_GCR_ECC_ERRAD                ((uint32_t)0x00000070UL) 
#define MXC_R_GCR_BTLE_LDOCR               ((uint32_t)0x00000074UL) 
#define MXC_R_GCR_BTLE_LDODCR              ((uint32_t)0x00000078UL) 
#define MXC_R_GCR_GP0                      ((uint32_t)0x00000080UL) 
#define MXC_R_GCR_APB_ASYNC                ((uint32_t)0x00000084UL) 
#define MXC_F_GCR_SCON_BSTAPEN_POS                     0 
#define MXC_F_GCR_SCON_BSTAPEN                         ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) 
#define MXC_F_GCR_SCON_SBUSARB_POS                     1 
#define MXC_F_GCR_SCON_SBUSARB                         ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) 
#define MXC_V_GCR_SCON_SBUSARB_FIX                     ((uint32_t)0x0UL) 
#define MXC_S_GCR_SCON_SBUSARB_FIX                     (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) 
#define MXC_V_GCR_SCON_SBUSARB_ROUND                   ((uint32_t)0x1UL) 
#define MXC_S_GCR_SCON_SBUSARB_ROUND                   (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) 
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS             4 
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                 ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) 
#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS                6 
#define MXC_F_GCR_SCON_CCACHE_FLUSH                    ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) 
#define MXC_F_GCR_SCON_DCACHE_FLUSH_POS                7 
#define MXC_F_GCR_SCON_DCACHE_FLUSH                    ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS)) 
#define MXC_F_GCR_SCON_SRCC_DIS_POS                    9 
#define MXC_F_GCR_SCON_SRCC_DIS                        ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SRCC_DIS_POS)) 
#define MXC_F_GCR_SCON_CCHK_POS                        13 
#define MXC_F_GCR_SCON_CCHK                            ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) 
#define MXC_F_GCR_SCON_CHKRES_POS                      15 
#define MXC_F_GCR_SCON_CHKRES                          ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) 
#define MXC_F_GCR_SCON_OVR_POS                         16 
#define MXC_F_GCR_SCON_OVR                             ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) 
#define MXC_V_GCR_SCON_OVR_0_9V                        ((uint32_t)0x0UL) 
#define MXC_S_GCR_SCON_OVR_0_9V                        (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) 
#define MXC_V_GCR_SCON_OVR_1_0V                        ((uint32_t)0x1UL) 
#define MXC_S_GCR_SCON_OVR_1_0V                        (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) 
#define MXC_V_GCR_SCON_OVR_1_1V                        ((uint32_t)0x2UL) 
#define MXC_S_GCR_SCON_OVR_1_1V                        (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) 
#define MXC_F_GCR_RSTR0_DMA_POS                        0 
#define MXC_F_GCR_RSTR0_DMA                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) 
#define MXC_F_GCR_RSTR0_WDT0_POS                       1 
#define MXC_F_GCR_RSTR0_WDT0                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT0_POS)) 
#define MXC_F_GCR_RSTR0_GPIO0_POS                      2 
#define MXC_F_GCR_RSTR0_GPIO0                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) 
#define MXC_F_GCR_RSTR0_GPIO1_POS                      3 
#define MXC_F_GCR_RSTR0_GPIO1                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) 
#define MXC_F_GCR_RSTR0_TIMER0_POS                     5 
#define MXC_F_GCR_RSTR0_TIMER0                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) 
#define MXC_F_GCR_RSTR0_TIMER1_POS                     6 
#define MXC_F_GCR_RSTR0_TIMER1                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) 
#define MXC_F_GCR_RSTR0_TIMER2_POS                     7 
#define MXC_F_GCR_RSTR0_TIMER2                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) 
#define MXC_F_GCR_RSTR0_TIMER3_POS                     8 
#define MXC_F_GCR_RSTR0_TIMER3                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) 
#define MXC_F_GCR_RSTR0_TIMER4_POS                     9 
#define MXC_F_GCR_RSTR0_TIMER4                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER4_POS)) 
#define MXC_F_GCR_RSTR0_TIMER5_POS                     10 
#define MXC_F_GCR_RSTR0_TIMER5                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER5_POS)) 
#define MXC_F_GCR_RSTR0_UART0_POS                      11 
#define MXC_F_GCR_RSTR0_UART0                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) 
#define MXC_F_GCR_RSTR0_UART1_POS                      12 
#define MXC_F_GCR_RSTR0_UART1                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) 
#define MXC_F_GCR_RSTR0_SPI1_POS                       13 
#define MXC_F_GCR_RSTR0_SPI1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) 
#define MXC_F_GCR_RSTR0_SPI2_POS                       14 
#define MXC_F_GCR_RSTR0_SPI2                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI2_POS)) 
#define MXC_F_GCR_RSTR0_I2C0_POS                       16 
#define MXC_F_GCR_RSTR0_I2C0                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) 
#define MXC_F_GCR_RSTR0_RTC_POS                        17 
#define MXC_F_GCR_RSTR0_RTC                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) 
#define MXC_F_GCR_RSTR0_CRYPTO_POS                     18 
#define MXC_F_GCR_RSTR0_CRYPTO                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) 
#define MXC_F_GCR_RSTR0_SMPHR_POS                      22 
#define MXC_F_GCR_RSTR0_SMPHR                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) 
#define MXC_F_GCR_RSTR0_USB_POS                        23 
#define MXC_F_GCR_RSTR0_USB                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_USB_POS)) 
#define MXC_F_GCR_RSTR0_ADC_POS                        26 
#define MXC_F_GCR_RSTR0_ADC                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_ADC_POS)) 
#define MXC_F_GCR_RSTR0_DMA1_POS                       27 
#define MXC_F_GCR_RSTR0_DMA1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA1_POS)) 
#define MXC_F_GCR_RSTR0_UART2_POS                      28 
#define MXC_F_GCR_RSTR0_UART2                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART2_POS)) 
#define MXC_F_GCR_RSTR0_SRST_POS                       29 
#define MXC_F_GCR_RSTR0_SRST                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) 
#define MXC_F_GCR_RSTR0_PRST_POS                       30 
#define MXC_F_GCR_RSTR0_PRST                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) 
#define MXC_F_GCR_RSTR0_SYSTEM_POS                     31 
#define MXC_F_GCR_RSTR0_SYSTEM                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) 
#define MXC_F_GCR_CLKCN_PSC_POS                        6 
#define MXC_F_GCR_CLKCN_PSC                            ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) 
#define MXC_V_GCR_CLKCN_PSC_DIV1                       ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV1                       (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV2                       ((uint32_t)0x1UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV2                       (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV4                       ((uint32_t)0x2UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV4                       (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV8                       ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV8                       (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV16                      ((uint32_t)0x4UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV16                      (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV32                      ((uint32_t)0x5UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV32                      (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV64                      ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV64                      (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_V_GCR_CLKCN_PSC_DIV128                     ((uint32_t)0x7UL) 
#define MXC_S_GCR_CLKCN_PSC_DIV128                     (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) 
#define MXC_F_GCR_CLKCN_CLKSEL_POS                     9 
#define MXC_F_GCR_CLKCN_CLKSEL                         ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) 
#define MXC_V_GCR_CLKCN_CLKSEL_HIRC                    ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                    (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_V_GCR_CLKCN_CLKSEL_XTAL32M                 ((uint32_t)0x2UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_XTAL32M                 (MXC_V_GCR_CLKCN_CLKSEL_XTAL32M << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_V_GCR_CLKCN_CLKSEL_LIRC8                   ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_LIRC8                   (MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_V_GCR_CLKCN_CLKSEL_HIRC96                  ((uint32_t)0x4UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_HIRC96                  (MXC_V_GCR_CLKCN_CLKSEL_HIRC96 << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_V_GCR_CLKCN_CLKSEL_HIRC8                   ((uint32_t)0x5UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_HIRC8                   (MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_V_GCR_CLKCN_CLKSEL_XTAL32K                 ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLKCN_CLKSEL_XTAL32K                 (MXC_V_GCR_CLKCN_CLKSEL_XTAL32K << MXC_F_GCR_CLKCN_CLKSEL_POS) 
#define MXC_F_GCR_CLKCN_CKRDY_POS                      13 
#define MXC_F_GCR_CLKCN_CKRDY                          ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) 
#define MXC_F_GCR_CLKCN_CCD_POS                        15 
#define MXC_F_GCR_CLKCN_CCD                            ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CCD_POS)) 
#define MXC_F_GCR_CLKCN_X32M_EN_POS                    16 
#define MXC_F_GCR_CLKCN_X32M_EN                        ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32M_EN_POS)) 
#define MXC_F_GCR_CLKCN_X32K_EN_POS                    17 
#define MXC_F_GCR_CLKCN_X32K_EN                        ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) 
#define MXC_F_GCR_CLKCN_HIRC_EN_POS                    18 
#define MXC_F_GCR_CLKCN_HIRC_EN                        ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) 
#define MXC_F_GCR_CLKCN_HIRC96M_EN_POS                 19 
#define MXC_F_GCR_CLKCN_HIRC96M_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC96M_EN_POS)) 
#define MXC_F_GCR_CLKCN_HIRC8M_EN_POS                  20 
#define MXC_F_GCR_CLKCN_HIRC8M_EN                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) 
#define MXC_F_GCR_CLKCN_HIRC8M_VS_POS                  21 
#define MXC_F_GCR_CLKCN_HIRC8M_VS                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) 
#define MXC_F_GCR_CLKCN_X32M_RDY_POS                   24 
#define MXC_F_GCR_CLKCN_X32M_RDY                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32M_RDY_POS)) 
#define MXC_F_GCR_CLKCN_X32K_RDY_POS                   25 
#define MXC_F_GCR_CLKCN_X32K_RDY                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) 
#define MXC_F_GCR_CLKCN_HIRC_RDY_POS                   26 
#define MXC_F_GCR_CLKCN_HIRC_RDY                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) 
#define MXC_F_GCR_CLKCN_HIRC96M_RDY_POS                27 
#define MXC_F_GCR_CLKCN_HIRC96M_RDY                    ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC96M_RDY_POS)) 
#define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS                 28 
#define MXC_F_GCR_CLKCN_HIRC8M_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) 
#define MXC_F_GCR_PM_MODE_POS                          0 
#define MXC_F_GCR_PM_MODE                              ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) 
#define MXC_V_GCR_PM_MODE_ACTIVE                       ((uint32_t)0x0UL) 
#define MXC_S_GCR_PM_MODE_ACTIVE                       (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_DEEPSLEEP                    ((uint32_t)0x2UL) 
#define MXC_S_GCR_PM_MODE_DEEPSLEEP                    (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_SHUTDOWN                     ((uint32_t)0x3UL) 
#define MXC_S_GCR_PM_MODE_SHUTDOWN                     (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_BACKUP                       ((uint32_t)0x4UL) 
#define MXC_S_GCR_PM_MODE_BACKUP                       (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) 
#define MXC_F_GCR_PM_GPIOWKEN_POS                      4 
#define MXC_F_GCR_PM_GPIOWKEN                          ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) 
#define MXC_F_GCR_PM_RTCWKEN_POS                       5 
#define MXC_F_GCR_PM_RTCWKEN                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) 
#define MXC_F_GCR_PM_USBWKEN_POS                       6 
#define MXC_F_GCR_PM_USBWKEN                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_USBWKEN_POS)) 
#define MXC_F_GCR_PM_WUTWKEN_POS                       7 
#define MXC_F_GCR_PM_WUTWKEN                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUTWKEN_POS)) 
#define MXC_F_GCR_PM_COMPWKEN_POS                      8 
#define MXC_F_GCR_PM_COMPWKEN                          ((uint32_t)(0x1UL << MXC_F_GCR_PM_COMPWKEN_POS)) 
#define MXC_F_GCR_PM_HIRCPD_POS                        15 
#define MXC_F_GCR_PM_HIRCPD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) 
#define MXC_F_GCR_PM_HIRC96MPD_POS                     16 
#define MXC_F_GCR_PM_HIRC96MPD                         ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC96MPD_POS)) 
#define MXC_F_GCR_PM_HIRC8MPD_POS                      17 
#define MXC_F_GCR_PM_HIRC8MPD                          ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) 
#define MXC_F_GCR_PM_XTALPB_POS                        20 
#define MXC_F_GCR_PM_XTALPB                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_XTALPB_POS)) 
#define MXC_F_GCR_PCKDIV_SDHCFRQ_POS                   7 
#define MXC_F_GCR_PCKDIV_SDHCFRQ                       ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_SDHCFRQ_POS)) 
#define MXC_F_GCR_PCKDIV_ADCFRQ_POS                    10 
#define MXC_F_GCR_PCKDIV_ADCFRQ                        ((uint32_t)(0xFUL << MXC_F_GCR_PCKDIV_ADCFRQ_POS)) 
#define MXC_F_GCR_PCKDIV_AONCD_POS                     14 
#define MXC_F_GCR_PCKDIV_AONCD                         ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) 
#define MXC_V_GCR_PCKDIV_AONCD_DIV_4                   ((uint32_t)0x0UL) 
#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                   (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) 
#define MXC_V_GCR_PCKDIV_AONCD_DIV_8                   ((uint32_t)0x1UL) 
#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                   (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) 
#define MXC_V_GCR_PCKDIV_AONCD_DIV_16                  ((uint32_t)0x2UL) 
#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                  (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) 
#define MXC_V_GCR_PCKDIV_AONCD_DIV_32                  ((uint32_t)0x3UL) 
#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                  (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) 
#define MXC_F_GCR_PERCKCN0_GPIO0D_POS                  0 
#define MXC_F_GCR_PERCKCN0_GPIO0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) 
#define MXC_F_GCR_PERCKCN0_GPIO1D_POS                  1 
#define MXC_F_GCR_PERCKCN0_GPIO1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) 
#define MXC_F_GCR_PERCKCN0_USBD_POS                    3 
#define MXC_F_GCR_PERCKCN0_USBD                        ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_USBD_POS)) 
#define MXC_F_GCR_PERCKCN0_DMAD_POS                    5 
#define MXC_F_GCR_PERCKCN0_DMAD                        ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) 
#define MXC_F_GCR_PERCKCN0_SPI1D_POS                   6 
#define MXC_F_GCR_PERCKCN0_SPI1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) 
#define MXC_F_GCR_PERCKCN0_SPI2D_POS                   7 
#define MXC_F_GCR_PERCKCN0_SPI2D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI2D_POS)) 
#define MXC_F_GCR_PERCKCN0_UART0D_POS                  9 
#define MXC_F_GCR_PERCKCN0_UART0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) 
#define MXC_F_GCR_PERCKCN0_UART1D_POS                  10 
#define MXC_F_GCR_PERCKCN0_UART1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) 
#define MXC_F_GCR_PERCKCN0_I2C0D_POS                   13 
#define MXC_F_GCR_PERCKCN0_I2C0D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) 
#define MXC_F_GCR_PERCKCN0_CRYPTOD_POS                 14 
#define MXC_F_GCR_PERCKCN0_CRYPTOD                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER0D_POS                 15 
#define MXC_F_GCR_PERCKCN0_TIMER0D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER0D_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER1D_POS                 16 
#define MXC_F_GCR_PERCKCN0_TIMER1D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER1D_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER2D_POS                 17 
#define MXC_F_GCR_PERCKCN0_TIMER2D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER2D_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER3D_POS                 18 
#define MXC_F_GCR_PERCKCN0_TIMER3D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER3D_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER4D_POS                 19 
#define MXC_F_GCR_PERCKCN0_TIMER4D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER4D_POS)) 
#define MXC_F_GCR_PERCKCN0_TIMER5D_POS                 20 
#define MXC_F_GCR_PERCKCN0_TIMER5D                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER5D_POS)) 
#define MXC_F_GCR_PERCKCN0_ADCD_POS                    23 
#define MXC_F_GCR_PERCKCN0_ADCD                        ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_ADCD_POS)) 
#define MXC_F_GCR_PERCKCN0_I2C1D_POS                   28 
#define MXC_F_GCR_PERCKCN0_I2C1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) 
#define MXC_F_GCR_PERCKCN0_PTD_POS                     29 
#define MXC_F_GCR_PERCKCN0_PTD                         ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_PTD_POS)) 
#define MXC_F_GCR_PERCKCN0_SPIXIPD_POS                 30 
#define MXC_F_GCR_PERCKCN0_SPIXIPD                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPIXIPD_POS)) 
#define MXC_F_GCR_PERCKCN0_SPIMD_POS                   31 
#define MXC_F_GCR_PERCKCN0_SPIMD                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPIMD_POS)) 
#define MXC_F_GCR_MEMCKCN_FWS_POS                      0 
#define MXC_F_GCR_MEMCKCN_FWS                          ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS                16 
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS                17 
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS                18 
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS                19 
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS                20 
#define MXC_F_GCR_MEMCKCN_SYSRAM4LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM5LS_POS                21 
#define MXC_F_GCR_MEMCKCN_SYSRAM5LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM5LS_POS)) 
#define MXC_F_GCR_MEMCKCN_SYSRAM6LS_POS                22 
#define MXC_F_GCR_MEMCKCN_SYSRAM6LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM6LS_POS)) 
#define MXC_F_GCR_MEMCKCN_ICACHELS_POS                 24 
#define MXC_F_GCR_MEMCKCN_ICACHELS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) 
#define MXC_F_GCR_MEMCKCN_ICACHEXIPLS_POS              25 
#define MXC_F_GCR_MEMCKCN_ICACHEXIPLS                  ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHEXIPLS_POS)) 
#define MXC_F_GCR_MEMCKCN_SCACHELS_POS                 26 
#define MXC_F_GCR_MEMCKCN_SCACHELS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SCACHELS_POS)) 
#define MXC_F_GCR_MEMCKCN_CRYPTOLS_POS                 27 
#define MXC_F_GCR_MEMCKCN_CRYPTOLS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_CRYPTOLS_POS)) 
#define MXC_F_GCR_MEMCKCN_USBLS_POS                    28 
#define MXC_F_GCR_MEMCKCN_USBLS                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_USBLS_POS)) 
#define MXC_F_GCR_MEMCKCN_ROM0LS_POS                   29 
#define MXC_F_GCR_MEMCKCN_ROM0LS                       ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROM0LS_POS)) 
#define MXC_F_GCR_MEMCKCN_ROM1LS_POS                   30 
#define MXC_F_GCR_MEMCKCN_ROM1LS                       ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROM1LS_POS)) 
#define MXC_F_GCR_MEMCKCN_ICACHE1LS_POS                31 
#define MXC_F_GCR_MEMCKCN_ICACHE1LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHE1LS_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM0Z_POS                    0 
#define MXC_F_GCR_MEMZCN_SRAM0Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM1Z_POS                    1 
#define MXC_F_GCR_MEMZCN_SRAM1Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM2_POS                     2 
#define MXC_F_GCR_MEMZCN_SRAM2                         ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM3Z_POS                    3 
#define MXC_F_GCR_MEMZCN_SRAM3Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM4Z_POS                    4 
#define MXC_F_GCR_MEMZCN_SRAM4Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM5Z_POS                    5 
#define MXC_F_GCR_MEMZCN_SRAM5Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM5Z_POS)) 
#define MXC_F_GCR_MEMZCN_SRAM6Z_POS                    6 
#define MXC_F_GCR_MEMZCN_SRAM6Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM6Z_POS)) 
#define MXC_F_GCR_MEMZCN_ICACHEZ_POS                   8 
#define MXC_F_GCR_MEMZCN_ICACHEZ                       ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) 
#define MXC_F_GCR_MEMZCN_ICACHEXIPZ_POS                9 
#define MXC_F_GCR_MEMZCN_ICACHEXIPZ                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEXIPZ_POS)) 
#define MXC_F_GCR_MEMZCN_SCACHEDATAZ_POS               10 
#define MXC_F_GCR_MEMZCN_SCACHEDATAZ                   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SCACHEDATAZ_POS)) 
#define MXC_F_GCR_MEMZCN_SCACHETAGZ_POS                11 
#define MXC_F_GCR_MEMZCN_SCACHETAGZ                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SCACHETAGZ_POS)) 
#define MXC_F_GCR_MEMZCN_CRYPTOZ_POS                   12 
#define MXC_F_GCR_MEMZCN_CRYPTOZ                       ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_CRYPTOZ_POS)) 
#define MXC_F_GCR_MEMZCN_USBFIFOZ_POS                  13 
#define MXC_F_GCR_MEMZCN_USBFIFOZ                      ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_USBFIFOZ_POS)) 
#define MXC_F_GCR_MEMZCN_ICACHE1Z_POS                  14 
#define MXC_F_GCR_MEMZCN_ICACHE1Z                      ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHE1Z_POS)) 
#define MXC_F_GCR_SYSST_ICELOCK_POS                    0 
#define MXC_F_GCR_SYSST_ICELOCK                        ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) 
#define MXC_F_GCR_SYSST_CODEINTERR_POS                 1 
#define MXC_F_GCR_SYSST_CODEINTERR                     ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) 
#define MXC_F_GCR_SYSST_SCMEMF_POS                     5 
#define MXC_F_GCR_SYSST_SCMEMF                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) 
#define MXC_F_GCR_RSTR1_I2C1_POS                       0 
#define MXC_F_GCR_RSTR1_I2C1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) 
#define MXC_F_GCR_RSTR1_PT_POS                         1 
#define MXC_F_GCR_RSTR1_PT                             ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PT_POS)) 
#define MXC_F_GCR_RSTR1_SPIXIP_POS                     3 
#define MXC_F_GCR_RSTR1_SPIXIP                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXIP_POS)) 
#define MXC_F_GCR_RSTR1_XSPIM_POS                      4 
#define MXC_F_GCR_RSTR1_XSPIM                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_XSPIM_POS)) 
#define MXC_F_GCR_RSTR1_SDHC_POS                       6 
#define MXC_F_GCR_RSTR1_SDHC                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SDHC_POS)) 
#define MXC_F_GCR_RSTR1_OWIRE_POS                      7 
#define MXC_F_GCR_RSTR1_OWIRE                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_OWIRE_POS)) 
#define MXC_F_GCR_RSTR1_WDT1_POS                       8 
#define MXC_F_GCR_RSTR1_WDT1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) 
#define MXC_F_GCR_RSTR1_SPI0_POS                       9 
#define MXC_F_GCR_RSTR1_SPI0                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPI0_POS)) 
#define MXC_F_GCR_RSTR1_SPIXMEM_POS                    15 
#define MXC_F_GCR_RSTR1_SPIXMEM                        ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXMEM_POS)) 
#define MXC_F_GCR_RSTR1_SMPHR_POS                      16 
#define MXC_F_GCR_RSTR1_SMPHR                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SMPHR_POS)) 
#define MXC_F_GCR_RSTR1_WDT2_POS                       17 
#define MXC_F_GCR_RSTR1_WDT2                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT2_POS)) 
#define MXC_F_GCR_RSTR1_BTLE_POS                       18 
#define MXC_F_GCR_RSTR1_BTLE                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_BTLE_POS)) 
#define MXC_F_GCR_RSTR1_AUDIO_POS                      19 
#define MXC_F_GCR_RSTR1_AUDIO                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_AUDIO_POS)) 
#define MXC_F_GCR_RSTR1_I2C2_POS                       20 
#define MXC_F_GCR_RSTR1_I2C2                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C2_POS)) 
#define MXC_F_GCR_RSTR1_RPU_POS                        21 
#define MXC_F_GCR_RSTR1_RPU                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_RPU_POS)) 
#define MXC_F_GCR_RSTR1_HTMR0_POS                      22 
#define MXC_F_GCR_RSTR1_HTMR0                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR0_POS)) 
#define MXC_F_GCR_RSTR1_HTMR1_POS                      23 
#define MXC_F_GCR_RSTR1_HTMR1                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR1_POS)) 
#define MXC_F_GCR_RSTR1_DVS_POS                        24 
#define MXC_F_GCR_RSTR1_DVS                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_DVS_POS)) 
#define MXC_F_GCR_RSTR1_SIMO_POS                       25 
#define MXC_F_GCR_RSTR1_SIMO                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SIMO_POS)) 
#define MXC_F_GCR_PERCKCN1_BTLED_POS                   0 
#define MXC_F_GCR_PERCKCN1_BTLED                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_BTLED_POS)) 
#define MXC_F_GCR_PERCKCN1_UART2D_POS                  1 
#define MXC_F_GCR_PERCKCN1_UART2D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_UART2D_POS)) 
#define MXC_F_GCR_PERCKCN1_TRNGD_POS                   2 
#define MXC_F_GCR_PERCKCN1_TRNGD                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) 
#define MXC_F_GCR_PERCKCN1_SCACHED_POS                 7 
#define MXC_F_GCR_PERCKCN1_SCACHED                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SCACHED_POS)) 
#define MXC_F_GCR_PERCKCN1_SDMAD_POS                   8 
#define MXC_F_GCR_PERCKCN1_SDMAD                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SDMAD_POS)) 
#define MXC_F_GCR_PERCKCN1_SMPHRD_POS                  9 
#define MXC_F_GCR_PERCKCN1_SMPHRD                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SMPHRD_POS)) 
#define MXC_F_GCR_PERCKCN1_SDHCD_POS                   10 
#define MXC_F_GCR_PERCKCN1_SDHCD                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SDHCD_POS)) 
#define MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS              12 
#define MXC_F_GCR_PERCKCN1_ICACHEXIPD                  ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS)) 
#define MXC_F_GCR_PERCKCN1_OWIRED_POS                  13 
#define MXC_F_GCR_PERCKCN1_OWIRED                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_OWIRED_POS)) 
#define MXC_F_GCR_PERCKCN1_SPI0D_POS                   14 
#define MXC_F_GCR_PERCKCN1_SPI0D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPI0D_POS)) 
#define MXC_F_GCR_PERCKCN1_SPIXIPDD_POS                20 
#define MXC_F_GCR_PERCKCN1_SPIXIPDD                    ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPIXIPDD_POS)) 
#define MXC_F_GCR_PERCKCN1_DMA1D_POS                   21 
#define MXC_F_GCR_PERCKCN1_DMA1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_DMA1D_POS)) 
#define MXC_F_GCR_PERCKCN1_AUDIOD_POS                  23 
#define MXC_F_GCR_PERCKCN1_AUDIOD                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_AUDIOD_POS)) 
#define MXC_F_GCR_PERCKCN1_I2C2D_POS                   24 
#define MXC_F_GCR_PERCKCN1_I2C2D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_I2C2D_POS)) 
#define MXC_F_GCR_PERCKCN1_HTMR0D_POS                  25 
#define MXC_F_GCR_PERCKCN1_HTMR0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_HTMR0D_POS)) 
#define MXC_F_GCR_PERCKCN1_HTMR1D_POS                  26 
#define MXC_F_GCR_PERCKCN1_HTMR1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_HTMR1D_POS)) 
#define MXC_F_GCR_PERCKCN1_WDT0D_POS                   27 
#define MXC_F_GCR_PERCKCN1_WDT0D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT0D_POS)) 
#define MXC_F_GCR_PERCKCN1_WDT1D_POS                   28 
#define MXC_F_GCR_PERCKCN1_WDT1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT1D_POS)) 
#define MXC_F_GCR_PERCKCN1_WDT2D_POS                   29 
#define MXC_F_GCR_PERCKCN1_WDT2D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_WDT2D_POS)) 
#define MXC_F_GCR_PERCKCN1_CPU1D_POS                   31 
#define MXC_F_GCR_PERCKCN1_CPU1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CPU1D_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU0DMAEVENT_POS            0 
#define MXC_F_GCR_EVENT_EN_CPU0DMAEVENT                ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMAEVENT_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS           1 
#define MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT               ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0DMA1EVENT_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS             2 
#define MXC_F_GCR_EVENT_EN_CPU0TXEVENT                 ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU0TXEVENT_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU1DMAEVENT_POS            3 
#define MXC_F_GCR_EVENT_EN_CPU1DMAEVENT                ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMAEVENT_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS           4 
#define MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT               ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1DMA1EVENT_POS)) 
#define MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS             5 
#define MXC_F_GCR_EVENT_EN_CPU1TXEVENT                 ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_CPU1TXEVENT_POS)) 
#define MXC_F_GCR_REVISION_REVISION_POS                0 
#define MXC_F_GCR_REVISION_REVISION                    ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) 
#define MXC_F_GCR_SYSSIE_ICEULIE_POS                   0 
#define MXC_F_GCR_SYSSIE_ICEULIE                       ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) 
#define MXC_F_GCR_SYSSIE_CIEIE_POS                     1 
#define MXC_F_GCR_SYSSIE_CIEIE                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) 
#define MXC_F_GCR_SYSSIE_SCMFIE_POS                    5 
#define MXC_F_GCR_SYSSIE_SCMFIE                        ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS             0 
#define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS             1 
#define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS             2 
#define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS             3 
#define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS             4 
#define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS             5 
#define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS             6 
#define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_IC0ECCERR_POS                 8 
#define MXC_F_GCR_ECC_ER_IC0ECCERR                     ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC0ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_IC1ECCERR_POS                 9 
#define MXC_F_GCR_ECC_ER_IC1ECCERR                     ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC1ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_ICXIPECCERR_POS               10 
#define MXC_F_GCR_ECC_ER_ICXIPECCERR                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_ICXIPECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_FL0ECCERR_POS                 11 
#define MXC_F_GCR_ECC_ER_FL0ECCERR                     ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL0ECCERR_POS)) 
#define MXC_F_GCR_ECC_ER_FL1ECCERR_POS                 12 
#define MXC_F_GCR_ECC_ER_FL1ECCERR                     ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL1ECCERR_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED_POS           0 
#define MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM0ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED_POS           1 
#define MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM1ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED_POS           2 
#define MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM2ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED_POS           3 
#define MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM3ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED_POS           4 
#define MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM4ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED_POS           5 
#define MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM5ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_IC0ECCNDED_POS               8 
#define MXC_F_GCR_ECC_CED_IC0ECCNDED                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC0ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_IC1ECCNDED_POS               9 
#define MXC_F_GCR_ECC_CED_IC1ECCNDED                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC1ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_ICXIPECCNDED_POS             10 
#define MXC_F_GCR_ECC_CED_ICXIPECCNDED                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_ICXIPECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_FL0ECCNDED_POS               11 
#define MXC_F_GCR_ECC_CED_FL0ECCNDED                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL0ECCNDED_POS)) 
#define MXC_F_GCR_ECC_CED_FL1ECCNDED_POS               12 
#define MXC_F_GCR_ECC_CED_FL1ECCNDED                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL1ECCNDED_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN_POS           0 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM0ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN_POS           1 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM1ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN_POS           2 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM2ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN_POS           3 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM3ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN_POS           4 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM4ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN_POS           5 
#define MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN               ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_SYSRAM5ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_IC0ECCEN_POS               8 
#define MXC_F_GCR_ECC_IRQEN_IC0ECCEN                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_IC0ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_IC1ECCEN_POS               9 
#define MXC_F_GCR_ECC_IRQEN_IC1ECCEN                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_IC1ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS             10 
#define MXC_F_GCR_ECC_IRQEN_ICXIPECCEN                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_ICXIPECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS               11 
#define MXC_F_GCR_ECC_IRQEN_FL0ECCEN                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL0ECCEN_POS)) 
#define MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS               12 
#define MXC_F_GCR_ECC_IRQEN_FL1ECCEN                   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_IRQEN_FL1ECCEN_POS)) 
#define MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS            0 
#define MXC_F_GCR_ECC_ERRAD_DATARAMADDR                ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_DATARAMADDR_POS)) 
#define MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS            14 
#define MXC_F_GCR_ECC_ERRAD_DATARAMBANK                ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMBANK_POS)) 
#define MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS             15 
#define MXC_F_GCR_ECC_ERRAD_DATARAMERR                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_DATARAMERR_POS)) 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS             16 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMADDR                 ((uint32_t)(0x1FFFUL << MXC_F_GCR_ECC_ERRAD_TAGRAMADDR_POS)) 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS             30 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMBANK                 ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMBANK_POS)) 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS              31 
#define MXC_F_GCR_ECC_ERRAD_TAGRAMERR                  ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ERRAD_TAGRAMERR_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS               0 
#define MXC_F_GCR_BTLE_LDOCR_LDORXEN                   ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS           1 
#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD               ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS             2 
#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL                 ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)) 
#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85            ((uint32_t)0x0UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_85            (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9             ((uint32_t)0x1UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_9             (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0             ((uint32_t)0x2UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_0             (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1             ((uint32_t)0x3UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_1             (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS               4 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN                   ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS            5 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD                ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS             6 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL                 ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) 
#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85            ((uint32_t)0x0UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85            (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9             ((uint32_t)0x1UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9             (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0             ((uint32_t)0x2UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_0             (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) 
#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1             ((uint32_t)0x3UL) 
#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1             (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS              8 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP                  ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS            9 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH                ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS              10 
#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP                  ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS            11 
#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH                ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS            12 
#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY                ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS            13 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY                ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS       14 
#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY           ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS)) 
#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS       15 
#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY           ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) 
#define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS            0 
#define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT                ((uint32_t)(0xFFUL << MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS)) 
#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS          8 
#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT              ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS)) 
#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS          20 
#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT              ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) 
#define MXC_F_GCR_GP0_GPR0_POS                         0 
#define MXC_F_GCR_GP0_GPR0                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_GP0_GPR0_POS)) 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS           0 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C0               ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C0_POS)) 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS           1 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C1               ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C1_POS)) 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS           2 
#define MXC_F_GCR_APB_ASYNC_APBASYNCI2C2               ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCI2C2_POS)) 
#define MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS             3 
#define MXC_F_GCR_APB_ASYNC_APBASYNCPT                 ((uint32_t)(0x1UL << MXC_F_GCR_APB_ASYNC_APBASYNCPT_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_GCR_REGS_H_