Implementation of AD9361 Driver. More...

#include <limits.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include "ad9361.h"
#include "ad9361_ext_band_ctrl.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_delay.h"
#include "ad9361_util.h"
#include "no_os_util.h"
#include "no_os_alloc.h"
#include "app_config.h"

Include dependency graph for ad9361.c:

Macros
#define	diff_abs(x, y)

#define	NO_GAIN_TABLE ((uint32_t)-1)

#define	SYNTH_LUT_SIZE 53

#define	SIZE_FULL_TABLE 77

#define	SIZE_SPLIT_TABLE 41

#define	ad9361_spi_readf(spi, reg, mask)

#define	ad9361_spi_writef(spi, reg, mask, val)

Functions
int32_t	ad9361_spi_readm (struct no_os_spi_desc spi, uint32_t reg, uint8_t rbuf, uint32_t num)

int32_t	ad9361_spi_read (struct no_os_spi_desc *spi, uint32_t reg)

int32_t	ad9361_reg_read (struct ad9361_rf_phy phy, uint32_t reg, uint32_t val)

int32_t	ad9361_spi_write (struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)

int32_t	ad9361_reg_write (struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)

uint32_t	ad9361_validate_rf_bw (struct ad9361_rf_phy *phy, uint32_t bw)

int32_t	ad9361_validate_rfpll (struct ad9361_rf_phy *phy, bool is_tx, uint64_t freq)

int32_t	ad9361_find_opt (uint8_t field, uint32_t size, uint32_t ret_start)

int32_t	ad9361_1rx1tx_channel_map (struct ad9361_rf_phy *phy, bool tx, int32_t channel)

int32_t	ad9361_reset (struct ad9361_rf_phy *phy)

int32_t	ad9361_en_dis_tx (struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)

int32_t	ad9361_en_dis_rx (struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)

int32_t	ad9361_bist_loopback (struct ad9361_rf_phy *phy, int32_t mode)

void	ad9361_get_bist_loopback (struct ad9361_rf_phy phy, int32_t mode)

int32_t	ad9361_bist_prbs (struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)

void	ad9361_get_bist_prbs (struct ad9361_rf_phy phy, enum ad9361_bist_mode mode)

int32_t	ad9361_bist_tone (struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)

void	ad9361_get_bist_tone (struct ad9361_rf_phy phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t *mask)

uint32_t	ad9361_gt (struct ad9361_rf_phy *phy)

uint32_t	ad9361_to_clk (uint64_t freq)

uint64_t	ad9361_from_clk (uint32_t freq)

int32_t	ad9361_set_tx_atten (struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)

int32_t	ad9361_get_tx_atten (struct ad9361_rf_phy *phy, uint32_t tx_num)

int32_t	ad9361_tx_mute (struct ad9361_rf_phy *phy, uint32_t state)

int32_t	ad9361_get_rx_gain (struct ad9361_rf_phy phy, uint32_t rx_id, struct rf_rx_gain rx_gain)

uint8_t	ad9361_ensm_get_state (struct ad9361_rf_phy *phy)

void	ad9361_ensm_force_state (struct ad9361_rf_phy *phy, uint8_t ensm_state)

void	ad9361_ensm_restore_state (struct ad9361_rf_phy *phy, uint8_t ensm_state)

void	ad9361_ensm_restore_prev_state (struct ad9361_rf_phy *phy)

int32_t	ad9361_set_rx_gain (struct ad9361_rf_phy phy, uint32_t rx_id, struct rf_rx_gain rx_gain)

int32_t	ad9361_set_gain_ctrl_mode (struct ad9361_rf_phy phy, struct rf_gain_ctrl gain_ctrl)

int32_t	ad9361_read_rssi (struct ad9361_rf_phy phy, struct rf_rssi rssi)

int32_t	ad9361_tracking_control (struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)

int	ad9361_synth_lo_powerdown (struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)

int32_t	ad9361_set_dcxo_tune (struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)

int32_t	ad9361_rf_port_setup (struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)

int32_t	ad9361_auxdac_get (struct ad9361_rf_phy *phy, int32_t dac)

int32_t	ad9361_get_temp (struct ad9361_rf_phy *phy)

int32_t	ad9361_get_auxadc (struct ad9361_rf_phy *phy)

int32_t	ad9361_ensm_set_state (struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)

int32_t	ad9361_set_trx_clock_chain (struct ad9361_rf_phy phy, uint32_t rx_path_clks, uint32_t *tx_path_clks)

int32_t	ad9361_get_trx_clock_chain (struct ad9361_rf_phy phy, uint32_t rx_path_clks, uint32_t *tx_path_clks)

int32_t	ad9361_calculate_rf_clock_chain (struct ad9361_rf_phy phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t rx_path_clks, uint32_t *tx_path_clks)

int32_t	ad9361_set_trx_clock_chain_freq (struct ad9361_rf_phy *phy, uint32_t freq)

int32_t	ad9361_set_ensm_mode (struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)

int32_t	ad9361_fastlock_load (struct ad9361_rf_phy phy, bool tx, uint32_t profile, uint8_t values)

int32_t	ad9361_fastlock_store (struct ad9361_rf_phy *phy, bool tx, uint32_t profile)

int32_t	ad9361_fastlock_recall (struct ad9361_rf_phy *phy, bool tx, uint32_t profile)

int32_t	ad9361_fastlock_save (struct ad9361_rf_phy phy, bool tx, uint32_t profile, uint8_t values)

int32_t	ad9361_mcs (struct ad9361_rf_phy *phy, int32_t step)

void	ad9361_clear_state (struct ad9361_rf_phy *phy)

int32_t	ad9361_setup (struct ad9361_rf_phy *phy)

int32_t	ad9361_do_calib_run (struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)

int32_t	ad9361_update_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)

int32_t	ad9361_load_fir_filter_coef (struct ad9361_rf_phy phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, int16_t coef)

int32_t	ad9361_parse_fir (struct ad9361_rf_phy phy, char data, uint32_t size)

int32_t	ad9361_validate_enable_fir (struct ad9361_rf_phy *phy)

uint32_t	ad9361_clk_factor_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)

int32_t	ad9361_clk_factor_round_rate (struct refclk_scale clk_priv, uint32_t rate, uint32_t prate)

int32_t	ad9361_clk_factor_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)

uint32_t	ad9361_bbpll_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)

int32_t	ad9361_bbpll_round_rate (struct refclk_scale clk_priv, uint32_t rate, uint32_t prate)

int32_t	ad9361_bbpll_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)

uint32_t	ad9361_rfpll_int_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)

int32_t	ad9361_rfpll_int_round_rate (struct refclk_scale clk_priv, uint32_t rate, uint32_t prate)

int32_t	ad9361_rfpll_int_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)

uint32_t	ad9361_rfpll_dummy_recalc_rate (struct refclk_scale *clk_priv)

int32_t	ad9361_rfpll_dummy_set_rate (struct refclk_scale *clk_priv, uint32_t rate)

uint32_t	ad9361_rfpll_recalc_rate (struct refclk_scale *clk_priv)

int32_t	ad9361_rfpll_round_rate (struct refclk_scale *clk_priv, uint32_t rate)

int32_t	ad9361_rfpll_set_rate (struct refclk_scale *clk_priv, uint32_t rate)

int32_t	ad9361_clk_mux_set_parent (struct refclk_scale *clk_priv, uint8_t index)

int32_t	ad9361_register_clocks (struct ad9361_rf_phy *phy)

int32_t	ad9361_unregister_clocks (struct ad9361_rf_phy *phy)

int32_t	ad9361_rssi_gain_step_calib (struct ad9361_rf_phy *phy)

int32_t	ad9361_rssi_program_lna_gain (struct ad9361_rf_phy *phy)

int32_t	ad9361_rssi_write_err_tbl (struct ad9361_rf_phy *phy)

int32_t	ad9361_read_clock_data_delays (struct ad9361_rf_phy *phy)

int32_t	ad9361_write_clock_data_delays (struct ad9361_rf_phy *phy)

int32_t	ad9361_get_dig_tune_data (struct ad9361_rf_phy phy, struct ad9361_dig_tune_data data)

int32_t	ad9361_write_bist_reg (struct ad9361_rf_phy *phy, uint32_t val)

int32_t	ad9361_ensm_mode_disable_pinctrl (struct ad9361_rf_phy *phy)

int32_t	ad9361_ensm_mode_restore_pinctrl (struct ad9361_rf_phy *phy)

int32_t	ad9361_set_cal_sw (struct ad9361_rf_phy *phy, uint32_t val)

Variables
const bool	has_split_gt = HAVE_SPLIT_GAIN_TABLE

struct gain_table_info	ad9361_adi_gt_info []

const char *	ad9361_ensm_states []

Detailed Description

Implementation of AD9361 Driver.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ ad9361_spi_readf

#define ad9361_spi_readf	(	spi,
		reg,
		mask )

Value:

__ad9361_spi_readf(spi, reg, mask, find_first_bit(mask))

find_first_bit

uint32_t find_first_bit(uint32_t word)

find_first_bit

Definition ad9361_util.c:272

SPI register bits read.

Parameters

spi
reg	The register address.
mask	The bits mask.

Returns: The bits value or negative error code in case of failure.

◆ ad9361_spi_writef

#define ad9361_spi_writef	(	spi,
		reg,
		mask,
		val )

Value:

__ad9361_spi_writef(spi, reg, mask, find_first_bit(mask), val)

SPI register bits write.

Parameters

spi
reg	The register address.
mask	The bits mask.
val	The bits value.

Returns: 0 in case of success, negative error code otherwise.

◆ diff_abs

#define diff_abs	(		x,
			y )

Value:

((x) > (y) ? (x - y) : (y - x))

◆ NO_GAIN_TABLE

#define NO_GAIN_TABLE ((uint32_t)-1)

◆ SIZE_FULL_TABLE

#define SIZE_FULL_TABLE 77

◆ SIZE_SPLIT_TABLE

#define SIZE_SPLIT_TABLE 41

◆ SYNTH_LUT_SIZE

#define SYNTH_LUT_SIZE 53

Function Documentation

◆ ad9361_1rx1tx_channel_map()

int32_t ad9361_1rx1tx_channel_map	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		int32_t	channel )

Select the channel mapping in 1rx1tx mode.

Parameters

phy	The AD9361 state structure.
tx	TX
channel	Channel

Returns: The channel number.

◆ ad9361_auxdac_get()

int32_t ad9361_auxdac_get	(	struct ad9361_rf_phy *	phy,
		int32_t	dac )

Get the Aux DAC value.

Parameters

phy	The AD9361 state structure.
dac	The DAC.

Returns: The value in case of success, negative error code otherwise.

◆ ad9361_bbpll_recalc_rate()

uint32_t ad9361_bbpll_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns: The clock rate.

◆ ad9361_bbpll_round_rate()

int32_t ad9361_bbpll_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns: The closest possible clock rate that can be set.

◆ ad9361_bbpll_set_rate()

int32_t ad9361_bbpll_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_bist_loopback()

int32_t ad9361_bist_loopback	(	struct ad9361_rf_phy *	phy,
		int32_t	mode )

BIST loopback mode.

Parameters

phy	The AD9361 state structure.
mode	BIST loopback mode.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_bist_prbs()

int32_t ad9361_bist_prbs	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode	mode )

BIST mode.

Parameters

phy	The AD9361 state structure.
mode	Bist mode.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_bist_tone()

int32_t ad9361_bist_tone	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode	mode,
		uint32_t	freq_Hz,
		uint32_t	level_dB,
		uint32_t	mask )

BIST tone.

Parameters

phy	The AD9361 state structure.
mode	Bist tone mode.
freq_Hz	Bist tone frequency.
level_dB	Bist tone level.
mask	Bist reg mask.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_calculate_rf_clock_chain()

int32_t ad9361_calculate_rf_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_sample_rate,
		uint32_t	rate_gov,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Calculate the RX and TX path rates to obtain the desired sample rate.

Parameters

phy	The AD9361 state structure.
tx_sample_rate	The desired sample rate.
rate_gov	The rate governor option.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_clear_state()

void ad9361_clear_state ( struct ad9361_rf_phy * phy )

Clear state.

Parameters

phy	The AD9361 state structure.

◆ ad9361_clk_factor_recalc_rate()

uint32_t ad9361_clk_factor_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns: The clock rate.

◆ ad9361_clk_factor_round_rate()

int32_t ad9361_clk_factor_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns: The closest possible clock rate that can be set.

◆ ad9361_clk_factor_set_rate()

int32_t ad9361_clk_factor_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_clk_mux_set_parent()

int32_t ad9361_clk_mux_set_parent	(	struct refclk_scale *	clk_priv,
		uint8_t	index )

Set clock mux parent.

Parameters

clk_priv	The refclk_scale structure.
index	Index - Enable (1) external LO, disable (0) = use internal PLL.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_do_calib_run()

int32_t ad9361_do_calib_run	(	struct ad9361_rf_phy *	phy,
		uint32_t	cal,
		int32_t	arg )

Perform the selected calibration

Parameters

phy	The AD9361 state structure.
cal	The selected calibration.
arg	The argument of the calibration.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_en_dis_rx()

int32_t ad9361_en_dis_rx	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_if,
		uint32_t	enable )

Enable/disable the desired RX channel.

Parameters

phy	The AD9361 state structure.
rx_if	The desired channel number [1, 2].
enable	Enable/disable option.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_en_dis_tx()

int32_t ad9361_en_dis_tx	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_if,
		uint32_t	enable )

Enable/disable the desired TX channel.

Parameters

phy	The AD9361 state structure.
tx_if	The desired channel number [1, 2].
enable	Enable/disable option.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_ensm_force_state()

void ad9361_ensm_force_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state )

Force Enable State Machine (ENSM) to the desired state (internally used only).

Parameters

phy	The AD9361 state structure.
ensm_state	The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH].

◆ ad9361_ensm_get_state()

uint8_t ad9361_ensm_get_state ( struct ad9361_rf_phy * phy )

Get Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.

Returns: The state.

◆ ad9361_ensm_mode_disable_pinctrl()

int32_t ad9361_ensm_mode_disable_pinctrl ( struct ad9361_rf_phy * phy )

Temporarily disable ENSM pin control by forcing TDD SPI mode. Useful before calibration sequences that must use SPI-driven state.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_ensm_mode_restore_pinctrl()

int32_t ad9361_ensm_mode_restore_pinctrl ( struct ad9361_rf_phy * phy )

Restore ENSM pin control to the state configured in pdata.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_ensm_restore_prev_state()

void ad9361_ensm_restore_prev_state ( struct ad9361_rf_phy * phy )

Restore the previous Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.

◆ ad9361_ensm_restore_state()

void ad9361_ensm_restore_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state )

Restore an Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.
ensm_state	The state.

◆ ad9361_ensm_set_state()

int32_t ad9361_ensm_set_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state,
		bool	pinctrl )

Set the desired Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.
ensm_state	The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH].
pinctrl	Set true, will enable the ENSM pin control.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_fastlock_load()

int32_t ad9361_fastlock_load	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile,
		uint8_t *	values )

Fastlock load values.

Parameters

phy	The AD9361 state structure.
tx
profile
values

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_fastlock_recall()

int32_t ad9361_fastlock_recall	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile )

Fastlock recall.

Parameters

phy	The AD9361 state structure.
tx
profile

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_fastlock_save()

int32_t ad9361_fastlock_save	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile,
		uint8_t *	values )

Fastlock save.

Parameters

phy	The AD9361 state structure.
tx
profile
values

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_fastlock_store()

int32_t ad9361_fastlock_store	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile )

Fastlock store.

Parameters

phy	The AD9361 state structure.
tx
profile

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_find_opt()

int32_t ad9361_find_opt	(	uint8_t *	field,
		uint32_t	size,
		uint32_t *	ret_start )

Find optimal value.

Parameters

field
size
ret_start

Returns: The optimal delay in case of success, negative error code otherwise.

◆ ad9361_from_clk()

uint64_t ad9361_from_clk ( uint32_t freq )

Shift back the frequency value, so it reflects the real value. Note: PLL operates between 47 .. 6000 MHz which is > 2^32.

Parameters

freq	The frequency value [Hz].

Returns: The shifted frequency value.

◆ ad9361_get_auxadc()

int32_t ad9361_get_auxadc ( struct ad9361_rf_phy * phy )

Get the Aux ADC value.

Parameters

phy	The AD9361 state structure.

Returns: The value in case of success, negative error code otherwise.

◆ ad9361_get_bist_loopback()

void ad9361_get_bist_loopback	(	struct ad9361_rf_phy *	phy,
		int32_t *	mode )

Get BIST loopback mode.

Parameters

phy	The AD9361 state structure.
mode	BIST loopback mode.

◆ ad9361_get_bist_prbs()

void ad9361_get_bist_prbs	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode *	mode )

Get BIST mode settings.

Parameters

phy	The AD9361 state structure.
mode	Bist mode.

◆ ad9361_get_bist_tone()

void ad9361_get_bist_tone	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode *	mode,
		uint32_t *	freq_Hz,
		uint32_t *	level_dB,
		uint32_t *	mask )

Get BIST tone settings.

Parameters

phy	The AD9361 state structure.
mode	Bist tone mode.
freq_Hz	Bist tone frequency.
level_dB	Bist tone level.
mask	Bist reg mask.

◆ ad9361_get_dig_tune_data()

int32_t ad9361_get_dig_tune_data	(	struct ad9361_rf_phy *	phy,
		struct ad9361_dig_tune_data *	data )

Return the current digital interface tuning state.

Parameters

phy	The AD9361 state structure.
data	Output: populated with skip_mode and current delay register values.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_get_rx_gain()

int32_t ad9361_get_rx_gain	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_id,
		struct rf_rx_gain *	rx_gain )

Get current RX gain for the selected channel.

Parameters

phy	The AD9361 state structure.
rx_id	The desired channel number (0, 1).
rx_gain	A rf_rx_gain struct to store the RF gain.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_get_temp()

int32_t ad9361_get_temp ( struct ad9361_rf_phy * phy )

Get the measured temperature of the device.

Parameters

phy	The AD9361 state structure.

Returns: The measured temperature of the device.

◆ ad9361_get_trx_clock_chain()

int32_t ad9361_get_trx_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Get the RX and TX path rates.

Parameters

phy	The AD9361 state structure.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_get_tx_atten()

int32_t ad9361_get_tx_atten	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_num )

Get the attenuation for the selected TX channel.

Parameters

phy	The AD9361 state structure.
tx_num	The selected channel [1, 2].

Returns: The attenuation value [mdB] or negative error code in case of failure.

◆ ad9361_gt()

uint32_t ad9361_gt ( struct ad9361_rf_phy * phy )

Return the current gain table index.

Parameters

phy	The AD9361 state structure.

Returns: The current gain table index or 0 if the table was not chosen.

◆ ad9361_load_fir_filter_coef()

int32_t ad9361_load_fir_filter_coef	(	struct ad9361_rf_phy *	phy,
		enum fir_dest	dest,
		int32_t	gain_dB,
		uint32_t	ntaps,
		int16_t *	coef )

Load the FIR filter coefficients.

Parameters

phy	The AD9361 state structure.
dest	Destination identifier (RX1,2 / TX1,2).
gain_dB	Gain option.
ntaps	Number of filter Taps.
coef	Pointer to filter coefficients.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_mcs()

int32_t ad9361_mcs	(	struct ad9361_rf_phy *	phy,
		int32_t	step )

Multi Chip Sync (MCS) config.

Parameters

phy	The AD9361 state structure.
step	MCS step.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_parse_fir()

int32_t ad9361_parse_fir	(	struct ad9361_rf_phy *	phy,
		char *	data,
		uint32_t	size )

Parse the FIR filter file/buffer.

Parameters

phy	The AD9361 state structure.
data	Pointer to buffer.
size	Buffer size.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_read_clock_data_delays()

int32_t ad9361_read_clock_data_delays ( struct ad9361_rf_phy * phy )

Read the current RX and TX clock/data delay register values back into pdata. Call this after ad9361_dig_tune() to persist the tuned values.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_read_rssi()

int32_t ad9361_read_rssi	(	struct ad9361_rf_phy *	phy,
		struct rf_rssi *	rssi )

Get the RSSI.

Parameters

phy	The AD9361 state structure.
rssi	A rf_rssi struct to store the RSSI.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_reg_read()

int32_t ad9361_reg_read	(	struct ad9361_rf_phy *	phy,
		uint32_t	reg,
		uint32_t *	val )

IIO SPI register read.

Parameters

phy	The AD9361 state structure.
reg	The register address.
val	The value read from register address.

Returns: The register value or negative error code in case of failure.

◆ ad9361_reg_write()

int32_t ad9361_reg_write	(	struct ad9361_rf_phy *	phy,
		uint32_t	reg,
		uint32_t	val )

IIO SPI register write.

Parameters

phy	The AD9361 state structure.
reg	The register address.
val	The value of the register.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_register_clocks()

int32_t ad9361_register_clocks ( struct ad9361_rf_phy * phy )

Register and initialize all the system clocks.

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_reset()

int32_t ad9361_reset ( struct ad9361_rf_phy * phy )

AD9361 Device Reset

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rf_port_setup()

int32_t ad9361_rf_port_setup	(	struct ad9361_rf_phy *	phy,
		bool	is_out,
		uint32_t	rx_inputs,
		uint32_t	txb )

Setup the RF port. Note: val 0 (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced 1 (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced 2 (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced

3 RX1A_N and RX2A_N enabled; unbalanced 4 RX1A_P and RX2A_P enabled; unbalanced 5 RX1B_N and RX2B_N enabled; unbalanced 6 RX1B_P and RX2B_P enabled; unbalanced 7 RX1C_N and RX2C_N enabled; unbalanced 8 RX1C_P and RX2C_P enabled; unbalanced 9 TX_MON1 10 TX_MON2 11 TX_MON1 & TX_MON2

Parameters

phy	The AD9361 state structure.
is_out	TX RF output port enabled.
rx_inputs	RX input option identifier
txb	TX output option identifier

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rfpll_dummy_recalc_rate()

uint32_t ad9361_rfpll_dummy_recalc_rate ( struct refclk_scale * clk_priv )

Recalculate the clock rate.

Parameters

clk_priv The refclk_scale structure.

Returns: The clock rate.

◆ ad9361_rfpll_dummy_set_rate()

int32_t ad9361_rfpll_dummy_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rfpll_int_recalc_rate()

uint32_t ad9361_rfpll_int_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns: The clock rate.

◆ ad9361_rfpll_int_round_rate()

int32_t ad9361_rfpll_int_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns: The closest possible clock rate that can be set.

◆ ad9361_rfpll_int_set_rate()

int32_t ad9361_rfpll_int_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rfpll_recalc_rate()

uint32_t ad9361_rfpll_recalc_rate ( struct refclk_scale * clk_priv )

Recalculate the clock rate.

Parameters

clk_priv The refclk_scale structure.

Returns: The clock rate.

◆ ad9361_rfpll_round_rate()

int32_t ad9361_rfpll_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns: The closest possible clock rate that can be set.

◆ ad9361_rfpll_set_rate()

int32_t ad9361_rfpll_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rssi_gain_step_calib()

int32_t ad9361_rssi_gain_step_calib ( struct ad9361_rf_phy * phy )

Perform an RSSI gain step calibration. Note: Before running the function, provide a single tone within the channel bandwidth and monitor the received data. Adjust the tone amplitude until the received data is within a few dB of full scale but not overloading.

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_rssi_program_lna_gain()

int32_t ad9361_rssi_program_lna_gain ( struct ad9361_rf_phy * phy )

Program the LNA gain step values from pdata->rssi_gain_step_calib_reg_val into the AD9361 gain-step calibration table.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_rssi_write_err_tbl()

int32_t ad9361_rssi_write_err_tbl ( struct ad9361_rf_phy * phy )

Write the pre-loaded LNA and mixer error tables from pdata into hardware.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_set_cal_sw()

int32_t ad9361_set_cal_sw	(	struct ad9361_rf_phy *	phy,
		uint32_t	val )

Drive the external calibration switch GPIOs (cal-sw1, cal-sw2). Bit 0 of val controls cal-sw1, bit 1 controls cal-sw2. These GPIOs route signals for TX quad / LO calibration on boards that have external calibration switch hardware.

Parameters

phy	The AD9361 state structure.
val	2-bit value: bit0 = cal_sw1, bit1 = cal_sw2.

Returns: 0 on success, -ENODEV if GPIOs are not configured.

◆ ad9361_set_dcxo_tune()

int32_t ad9361_set_dcxo_tune	(	struct ad9361_rf_phy *	phy,
		uint32_t	coarse,
		uint32_t	fine )

Setup the DCXO tune.

Parameters

phy	The AD9361 state structure.
coarse	The DCXO tune coarse.
fine	The DCXO tune fine.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_ensm_mode()

int32_t ad9361_set_ensm_mode	(	struct ad9361_rf_phy *	phy,
		bool	fdd,
		bool	pinctrl )

Internal ENSM mode options helper function.

Parameters

phy	The AD9361 state structure.
fdd
pinctrl

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_gain_ctrl_mode()

int32_t ad9361_set_gain_ctrl_mode	(	struct ad9361_rf_phy *	phy,
		struct rf_gain_ctrl *	gain_ctrl )

Set the gain control mode.

Parameters

phy	The AD9361 state structure.
gain_ctrl	A rf_gain_ctrl struct that contains the the desired channel information and the gain control mode.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_rx_gain()

int32_t ad9361_set_rx_gain	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_id,
		struct rf_rx_gain *	rx_gain )

Set the RX gain for the selected channel.

Parameters

phy	The AD9361 state structure.
rx_id	The desired channel number (0, 1).
rx_gain	The rf_rx_gain struct containing the RF gain.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_trx_clock_chain()

int32_t ad9361_set_trx_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Set the RX and TX path rates.

Parameters

phy	The AD9361 state structure.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_trx_clock_chain_freq()

int32_t ad9361_set_trx_clock_chain_freq	(	struct ad9361_rf_phy *	phy,
		uint32_t	freq )

Set the desired sample rate.

Parameters

phy	The AD9361 state structure.
freq	The desired sample rate.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_set_tx_atten()

int32_t ad9361_set_tx_atten	(	struct ad9361_rf_phy *	phy,
		uint32_t	atten_mdb,
		bool	tx1,
		bool	tx2,
		bool	immed )

Set the attenuation for the selected TX channels.

Parameters

phy	The AD9361 state structure.
atten_mdb	Attenuation value [mdB].
tx1	Set true, the attenuation of the TX1 will be affected.
tx2	Set true, the attenuation of the TX2 will be affected.
immed	Set true, an immediate update will take place.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_setup()

int32_t ad9361_setup ( struct ad9361_rf_phy * phy )

Setup the AD9361 device.

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_spi_read()

int32_t ad9361_spi_read	(	struct no_os_spi_desc *	spi,
		uint32_t	reg )

SPI register read.

Parameters

spi
reg	The register address.

Returns: The register value or negative error code in case of failure.

◆ ad9361_spi_readm()

int32_t ad9361_spi_readm	(	struct no_os_spi_desc *	spi,
		uint32_t	reg,
		uint8_t *	rbuf,
		uint32_t	num )

SPI multiple bytes register read.

Parameters

spi
reg	The register address.
rbuf	The data buffer.
num	The number of bytes to read.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_spi_write()

int32_t ad9361_spi_write	(	struct no_os_spi_desc *	spi,
		uint32_t	reg,
		uint32_t	val )

SPI register write.

Parameters

spi
reg	The register address.
val	The value of the register.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_synth_lo_powerdown()

int ad9361_synth_lo_powerdown	(	struct ad9361_rf_phy *	phy,
		enum synth_pd_ctrl	rx,
		enum synth_pd_ctrl	tx )

Power down the TX and/or RX Local Oscillators.

Parameters

phy	The AD9361 state structure.
rx	The RX LO setting.
tx	The TX LO setting.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_to_clk()

uint32_t ad9361_to_clk ( uint64_t freq )

Shift the real frequency value, so it fits type unsigned long Note: PLL operates between 47 .. 6000 MHz which is > 2^32.

Parameters

freq	The frequency value [Hz].

Returns: The shifted frequency value.

◆ ad9361_tracking_control()

int32_t ad9361_tracking_control	(	struct ad9361_rf_phy *	phy,
		bool	bbdc_track,
		bool	rfdc_track,
		bool	rxquad_track )

Setup RX tracking calibrations.

Parameters

phy	The AD9361 state structure.
bbdc_track	Set true, will enable the BBDC tracking.
rfdc_track	Set true, will enable the RFDC tracking.
rxquad_track	Set true, will enable the RXQUAD tracking.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_tx_mute()

int32_t ad9361_tx_mute	(	struct ad9361_rf_phy *	phy,
		uint32_t	state )

Mute TX.

Parameters

phy	The AD9361 state structure.
state	The state - 0 mute; 1 - unmute.

Returns: 0 in case of success

◆ ad9361_unregister_clocks()

int32_t ad9361_unregister_clocks ( struct ad9361_rf_phy * phy )

Unregister all the system clocks.

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_update_rf_bandwidth()

int32_t ad9361_update_rf_bandwidth	(	struct ad9361_rf_phy *	phy,
		uint32_t	rf_rx_bw,
		uint32_t	rf_tx_bw )

Set the RF bandwidth.

Parameters

phy	The AD9361 state structure.
rf_rx_bw	The desired RX bandwidth [Hz].
rf_tx_bw	The desired TX bandwidth [Hz].

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_validate_enable_fir()

int32_t ad9361_validate_enable_fir ( struct ad9361_rf_phy * phy )

Validate FIR filter configuration - on pass enable.

Parameters

phy	The AD9361 state structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_validate_rf_bw()

uint32_t ad9361_validate_rf_bw	(	struct ad9361_rf_phy *	phy,
		uint32_t	bw )

Validate RF BW frequency.

Parameters

phy	The AD9361 state structure.
bw	The RF BW frequency.

Returns: The validated RF BW frequency.

◆ ad9361_validate_rfpll()

int32_t ad9361_validate_rfpll	(	struct ad9361_rf_phy *	phy,
		bool	is_tx,
		uint64_t	freq )

Validate RF PLL frequency.

Parameters

phy	The AD9361 state structure.
is_tx	TX enabled.
freq	The RF PLL frequency.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9361_write_bist_reg()

int32_t ad9361_write_bist_reg	(	struct ad9361_rf_phy *	phy,
		uint32_t	val )

Write directly to the AD9361 BIST configuration register.

Parameters

phy	The AD9361 state structure.
val	Value to write.

Returns: 0 on success, negative error code otherwise.

◆ ad9361_write_clock_data_delays()

int32_t ad9361_write_clock_data_delays ( struct ad9361_rf_phy * phy )

Write the saved RX and TX clock/data delay values from pdata to hardware. Call this at startup to restore previously tuned values and skip dig_tune.

Parameters

phy	The AD9361 state structure.

Returns: 0 on success, negative error code otherwise.

Variable Documentation

◆ ad9361_adi_gt_info

struct gain_table_info ad9361_adi_gt_info[]

◆ ad9361_ensm_states

const char* ad9361_ensm_states[]

Initial value:

= {
    "sleep", "", "", "", "", "alert", "tx", "tx flush",
    "rx", "rx_flush", "fdd", "fdd_flush"
}

State machine modes.

◆ has_split_gt

const bool has_split_gt = HAVE_SPLIT_GAIN_TABLE

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ ad9361_spi_readf

◆ ad9361_spi_writef

◆ diff_abs

◆ NO_GAIN_TABLE

◆ SIZE_FULL_TABLE

◆ SIZE_SPLIT_TABLE

◆ SYNTH_LUT_SIZE

Function Documentation

◆ ad9361_1rx1tx_channel_map()

◆ ad9361_auxdac_get()

◆ ad9361_bbpll_recalc_rate()

◆ ad9361_bbpll_round_rate()

◆ ad9361_bbpll_set_rate()

◆ ad9361_bist_loopback()

◆ ad9361_bist_prbs()

◆ ad9361_bist_tone()

◆ ad9361_calculate_rf_clock_chain()

◆ ad9361_clear_state()

◆ ad9361_clk_factor_recalc_rate()

◆ ad9361_clk_factor_round_rate()

◆ ad9361_clk_factor_set_rate()

◆ ad9361_clk_mux_set_parent()

◆ ad9361_do_calib_run()

◆ ad9361_en_dis_rx()

◆ ad9361_en_dis_tx()

◆ ad9361_ensm_force_state()

◆ ad9361_ensm_get_state()

◆ ad9361_ensm_mode_disable_pinctrl()

◆ ad9361_ensm_mode_restore_pinctrl()

◆ ad9361_ensm_restore_prev_state()

◆ ad9361_ensm_restore_state()

◆ ad9361_ensm_set_state()

◆ ad9361_fastlock_load()

◆ ad9361_fastlock_recall()

◆ ad9361_fastlock_save()

◆ ad9361_fastlock_store()

◆ ad9361_find_opt()

◆ ad9361_from_clk()

◆ ad9361_get_auxadc()

◆ ad9361_get_bist_loopback()

◆ ad9361_get_bist_prbs()

◆ ad9361_get_bist_tone()

◆ ad9361_get_dig_tune_data()

◆ ad9361_get_rx_gain()

◆ ad9361_get_temp()

◆ ad9361_get_trx_clock_chain()

◆ ad9361_get_tx_atten()

◆ ad9361_gt()

◆ ad9361_load_fir_filter_coef()

◆ ad9361_mcs()

◆ ad9361_parse_fir()

◆ ad9361_read_clock_data_delays()

◆ ad9361_read_rssi()

◆ ad9361_reg_read()

◆ ad9361_reg_write()

◆ ad9361_register_clocks()

◆ ad9361_reset()

◆ ad9361_rf_port_setup()

◆ ad9361_rfpll_dummy_recalc_rate()

◆ ad9361_rfpll_dummy_set_rate()

◆ ad9361_rfpll_int_recalc_rate()

◆ ad9361_rfpll_int_round_rate()

◆ ad9361_rfpll_int_set_rate()

◆ ad9361_rfpll_recalc_rate()

◆ ad9361_rfpll_round_rate()

◆ ad9361_rfpll_set_rate()

◆ ad9361_rssi_gain_step_calib()

◆ ad9361_rssi_program_lna_gain()

◆ ad9361_rssi_write_err_tbl()

◆ ad9361_set_cal_sw()

◆ ad9361_set_dcxo_tune()

◆ ad9361_set_ensm_mode()

◆ ad9361_set_gain_ctrl_mode()

◆ ad9361_set_rx_gain()

◆ ad9361_set_trx_clock_chain()