LTC6952

LTC6952 Ultralow Jitter, 4.5GHz PLL, JESD204B/JESD204C Linux Driver.

Supported Devices

Description

The LTC6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider.

The LTC6952’s eleven outputs can be configured is up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications.

This is a Linux industrial I/O (Linux Industrial I/O Subsystem) subsystem driver, targeting serial interface PLL Synthesizers. The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc). See Linux Industrial I/O Subsystem for more information.

Source Code

Status

Source	Mainlined?
drivers/iio/frequency/ltc6952.c	No

Files

Function	File
driver	drivers/iio/frequency/ltc6952.c
Documentation	Documentation/devicetree/bindings/iio/frequency/adi,ltc6952.yaml

Enabling the driver

Configure kernel with make menuconfig (alternatively use make xconfig or make qconfig)

Note

The LTC6952 Driver depends on CONFIG_SPI

Linux Kernel Configuration
    Device Drivers  --->
    <*>  Industrial I/O support --->
             Frequency Synthesizers DDS/PLL  --->
                 Clock Generator/Distribution  --->
                 <*> Analog Devices LTC6952 Clock Ultralow Jitter with JESD204B/C

Adding a device tree entry

Available properties

Required properties:

compatible: Should be adi,ltc6952.
reg: SPI chip select number.
spi-max-frequency: Max SPI frequency to use (<= 20000000).
adi,vco-frequency-hz: The frequency of the VCO.
adi,ref-frequency-hz: Reference input frequency. This is fed in the reference divider.
clock-output-names: An array of 11 elements, representing the names of the output clocks.

Adding channels

Channels can be specified using child nodes. The following properties are applicable to them:

reg: The identifier of the channel.
adi,extended-name: Descriptive channel name.
adi,divider: Channel divider. This divides the incoming VCO frequency.
adi,digital-delay: Each output divider can have the start time of the output delayed by integer multiples of half of the VCO period after a synchronization event.
adi,analog-delay: Each output has a fine analog delay feature to further adjust its output delay time (tADELx) in small steps.

Device tree example

The following example instantiates the LTC6962 driver for a LTC6962 device connected on the SPI bus to the chip-select line 0.

ltc6952@0 {
       compatible = "adi,ltc6952";
       reg = <0>;
       #address-cells = <1>;
       #size-cells = <0>;
       spi-max-frequency = <10000000>;
       clock-output-names = "ltc6952_out0", "ltc6952_out1", "ltc6952_out2",
         "ltc6952_out3", "ltc6952_out4", "ltc6952_out5", "ltc6952_out6",
         "ltc6952_out7", "ltc6952_out8", "ltc6952_out9", "ltc6952_out10";
       #clock-cells = <1>;
       adi,vco-frequency-hz = <4000000000>;
       adi,ref-frequency-hz = <100000000>;
       ltc6952_c0: channel@0 {
         reg = <0>;
         adi,extended-name = "REF_CLK";
         adi,divider = <10>;
         adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
       ltc6952_c1: channel@1 {
         reg = <1>;
         adi,extended-name = "TEST_CLK";
         adi,divider = <10>;
       };
     };