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| #define | MXC_R_GCR_SCON ((uint32_t)0x00000000UL) |
| |
| #define | MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) |
| |
| #define | MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) |
| |
| #define | MXC_R_GCR_PMR ((uint32_t)0x0000000CUL) |
| |
| #define | MXC_R_GCR_PCLK_DIV ((uint32_t)0x00000018UL) |
| |
| #define | MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) |
| |
| #define | MXC_R_GCR_MEM_CLK ((uint32_t)0x00000028UL) |
| |
| #define | MXC_R_GCR_MEM_ZERO ((uint32_t)0x0000002CUL) |
| |
| #define | MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) |
| |
| #define | MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) |
| |
| #define | MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) |
| |
| #define | MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL) |
| |
| #define | MXC_R_GCR_REV ((uint32_t)0x00000050UL) |
| |
| #define | MXC_R_GCR_SYS_STAT_IE ((uint32_t)0x00000054UL) |
| |
| #define | MXC_F_GCR_SCON_BSTAPEN_POS 0 |
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| #define | MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) |
| |
| #define | MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_BSTAPEN_DIS (MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) |
| |
| #define | MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_BSTAPEN_EN (MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) |
| |
| #define | MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 |
| |
| #define | MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) |
| |
| #define | MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) |
| |
| #define | MXC_V_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) |
| |
| #define | MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 |
| |
| #define | MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) |
| |
| #define | MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) |
| |
| #define | MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) |
| |
| #define | MXC_F_GCR_SCON_DCACHE_FLUSH_POS 7 |
| |
| #define | MXC_F_GCR_SCON_DCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS)) |
| |
| #define | MXC_V_GCR_SCON_DCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_DCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_DCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS) |
| |
| #define | MXC_V_GCR_SCON_DCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_DCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_DCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_DCACHE_FLUSH_POS) |
| |
| #define | MXC_F_GCR_SCON_DCACHE_DIS_POS 9 |
| |
| #define | MXC_F_GCR_SCON_DCACHE_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_DIS_POS)) |
| |
| #define | MXC_V_GCR_SCON_DCACHE_DIS_ENABLED ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_DCACHE_DIS_ENABLED (MXC_V_GCR_SCON_DCACHE_DIS_ENABLED << MXC_F_GCR_SCON_DCACHE_DIS_POS) |
| |
| #define | MXC_V_GCR_SCON_DCACHE_DIS_DISABLED ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_DCACHE_DIS_DISABLED (MXC_V_GCR_SCON_DCACHE_DIS_DISABLED << MXC_F_GCR_SCON_DCACHE_DIS_POS) |
| |
| #define | MXC_F_GCR_SCON_CCHK_POS 13 |
| |
| #define | MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) |
| |
| #define | MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_CCHK_COMPLETE (MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) |
| |
| #define | MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) |
| |
| #define | MXC_F_GCR_SCON_CHKRES_POS 15 |
| |
| #define | MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) |
| |
| #define | MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_CHKRES_PASS (MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) |
| |
| #define | MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_CHKRES_FAIL (MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) |
| |
| #define | MXC_F_GCR_SCON_OVR_POS 16 |
| |
| #define | MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) |
| |
| #define | MXC_V_GCR_SCON_OVR_0V9 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SCON_OVR_0V9 (MXC_V_GCR_SCON_OVR_0V9 << MXC_F_GCR_SCON_OVR_POS) |
| |
| #define | MXC_V_GCR_SCON_OVR_1V ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SCON_OVR_1V (MXC_V_GCR_SCON_OVR_1V << MXC_F_GCR_SCON_OVR_POS) |
| |
| #define | MXC_V_GCR_SCON_OVR_1V1 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_GCR_SCON_OVR_1V1 (MXC_V_GCR_SCON_OVR_1V1 << MXC_F_GCR_SCON_OVR_POS) |
| |
| #define | MXC_F_GCR_RST0_DMA_POS 0 |
| |
| #define | MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) |
| |
| #define | MXC_F_GCR_RST0_WDT0_POS 1 |
| |
| #define | MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) |
| |
| #define | MXC_F_GCR_RST0_GPIO0_POS 2 |
| |
| #define | MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) |
| |
| #define | MXC_F_GCR_RST0_GPIO1_POS 3 |
| |
| #define | MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) |
| |
| #define | MXC_F_GCR_RST0_GPIO2_POS 4 |
| |
| #define | MXC_F_GCR_RST0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO2_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER0_POS 5 |
| |
| #define | MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER1_POS 6 |
| |
| #define | MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER2_POS 7 |
| |
| #define | MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER3_POS 8 |
| |
| #define | MXC_F_GCR_RST0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER3_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER4_POS 9 |
| |
| #define | MXC_F_GCR_RST0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER4_POS)) |
| |
| #define | MXC_F_GCR_RST0_TIMER5_POS 10 |
| |
| #define | MXC_F_GCR_RST0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER5_POS)) |
| |
| #define | MXC_F_GCR_RST0_UART0_POS 11 |
| |
| #define | MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) |
| |
| #define | MXC_F_GCR_RST0_UART1_POS 12 |
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| #define | MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) |
| |
| #define | MXC_F_GCR_RST0_SPI0_POS 13 |
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| #define | MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) |
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| #define | MXC_F_GCR_RST0_SPI1_POS 14 |
| |
| #define | MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) |
| |
| #define | MXC_F_GCR_RST0_SPI2_POS 15 |
| |
| #define | MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) |
| |
| #define | MXC_F_GCR_RST0_I2C0_POS 16 |
| |
| #define | MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) |
| |
| #define | MXC_F_GCR_RST0_RTC_POS 17 |
| |
| #define | MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) |
| |
| #define | MXC_F_GCR_RST0_TPU_POS 18 |
| |
| #define | MXC_F_GCR_RST0_TPU ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TPU_POS)) |
| |
| #define | MXC_F_GCR_RST0_HBC_POS 21 |
| |
| #define | MXC_F_GCR_RST0_HBC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_HBC_POS)) |
| |
| #define | MXC_F_GCR_RST0_TFT_POS 22 |
| |
| #define | MXC_F_GCR_RST0_TFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TFT_POS)) |
| |
| #define | MXC_F_GCR_RST0_USB_POS 23 |
| |
| #define | MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) |
| |
| #define | MXC_F_GCR_RST0_ADC_POS 26 |
| |
| #define | MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) |
| |
| #define | MXC_F_GCR_RST0_UART2_POS 28 |
| |
| #define | MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) |
| |
| #define | MXC_F_GCR_RST0_SOFT_POS 29 |
| |
| #define | MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) |
| |
| #define | MXC_F_GCR_RST0_PERIPH_POS 30 |
| |
| #define | MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) |
| |
| #define | MXC_F_GCR_RST0_SYS_POS 31 |
| |
| #define | MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS 6 |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 ((uint32_t)0x5UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 ((uint32_t)0x6UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 ((uint32_t)0x7UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS 9 |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSOSC_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN ((uint32_t)0x2UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_NANORING ((uint32_t)0x3UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_NANORING (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_NANORING << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 ((uint32_t)0x5UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_X32K ((uint32_t)0x6UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_X32K (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_X32K << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS 13 |
| |
| #define | MXC_F_GCR_CLK_CTRL_SYSOSC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS)) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_BUSY ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_RDY_BUSY (MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_BUSY << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_READY ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_SYSOSC_RDY_READY (MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_READY << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS) |
| |
| #define | MXC_F_GCR_CLK_CTRL_CCD_POS 15 |
| |
| #define | MXC_F_GCR_CLK_CTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CCD_POS)) |
| |
| #define | MXC_V_GCR_CLK_CTRL_CCD_NON_DIV ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_CCD_NON_DIV (MXC_V_GCR_CLK_CTRL_CCD_NON_DIV << MXC_F_GCR_CLK_CTRL_CCD_POS) |
| |
| #define | MXC_V_GCR_CLK_CTRL_CCD_DIV ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_CLK_CTRL_CCD_DIV (MXC_V_GCR_CLK_CTRL_CCD_DIV << MXC_F_GCR_CLK_CTRL_CCD_POS) |
| |
| #define | MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 |
| |
| #define | MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_CRYPTO_EN_POS 18 |
| |
| #define | MXC_F_GCR_CLK_CTRL_CRYPTO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CRYPTO_EN_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC96_EN_POS 19 |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC96_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC96_EN_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_EN_POS 20 |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_EN_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_VS_POS 21 |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_VS_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 |
| |
| #define | MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_CRYPTO_RDY_POS 26 |
| |
| #define | MXC_F_GCR_CLK_CTRL_CRYPTO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CRYPTO_RDY_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC96_RDY_POS 27 |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC96_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC96_RDY_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_RDY_POS 28 |
| |
| #define | MXC_F_GCR_CLK_CTRL_HIRC8_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_RDY_POS)) |
| |
| #define | MXC_F_GCR_CLK_CTRL_NANORING_RDY_POS 29 |
| |
| #define | MXC_F_GCR_CLK_CTRL_NANORING_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_NANORING_RDY_POS)) |
| |
| #define | MXC_F_GCR_PMR_MODE_POS 0 |
| |
| #define | MXC_F_GCR_PMR_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PMR_MODE_POS)) |
| |
| #define | MXC_V_GCR_PMR_MODE_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PMR_MODE_ACTIVE (MXC_V_GCR_PMR_MODE_ACTIVE << MXC_F_GCR_PMR_MODE_POS) |
| |
| #define | MXC_V_GCR_PMR_MODE_SHUTDOWN ((uint32_t)0x3UL) |
| |
| #define | MXC_S_GCR_PMR_MODE_SHUTDOWN (MXC_V_GCR_PMR_MODE_SHUTDOWN << MXC_F_GCR_PMR_MODE_POS) |
| |
| #define | MXC_V_GCR_PMR_MODE_BACKUP ((uint32_t)0x4UL) |
| |
| #define | MXC_S_GCR_PMR_MODE_BACKUP (MXC_V_GCR_PMR_MODE_BACKUP << MXC_F_GCR_PMR_MODE_POS) |
| |
| #define | MXC_F_GCR_PMR_GPIOWKEN_POS 4 |
| |
| #define | MXC_F_GCR_PMR_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_GPIOWKEN_POS)) |
| |
| #define | MXC_F_GCR_PMR_RTCWKEN_POS 5 |
| |
| #define | MXC_F_GCR_PMR_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_RTCWKEN_POS)) |
| |
| #define | MXC_F_GCR_PMR_USBWKEN_POS 6 |
| |
| #define | MXC_F_GCR_PMR_USBWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_USBWKEN_POS)) |
| |
| #define | MXC_F_GCR_PMR_CRYPTOPD_POS 15 |
| |
| #define | MXC_F_GCR_PMR_CRYPTOPD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_CRYPTOPD_POS)) |
| |
| #define | MXC_V_GCR_PMR_CRYPTOPD_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PMR_CRYPTOPD_ACTIVE (MXC_V_GCR_PMR_CRYPTOPD_ACTIVE << MXC_F_GCR_PMR_CRYPTOPD_POS) |
| |
| #define | MXC_V_GCR_PMR_CRYPTOPD_DEEPSLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PMR_CRYPTOPD_DEEPSLEEP (MXC_V_GCR_PMR_CRYPTOPD_DEEPSLEEP << MXC_F_GCR_PMR_CRYPTOPD_POS) |
| |
| #define | MXC_F_GCR_PMR_HIRC96PD_POS 16 |
| |
| #define | MXC_F_GCR_PMR_HIRC96PD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC96PD_POS)) |
| |
| #define | MXC_V_GCR_PMR_HIRC96PD_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PMR_HIRC96PD_ACTIVE (MXC_V_GCR_PMR_HIRC96PD_ACTIVE << MXC_F_GCR_PMR_HIRC96PD_POS) |
| |
| #define | MXC_V_GCR_PMR_HIRC96PD_DEEPSLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PMR_HIRC96PD_DEEPSLEEP (MXC_V_GCR_PMR_HIRC96PD_DEEPSLEEP << MXC_F_GCR_PMR_HIRC96PD_POS) |
| |
| #define | MXC_F_GCR_PMR_HIRC8PD_POS 17 |
| |
| #define | MXC_F_GCR_PMR_HIRC8PD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC8PD_POS)) |
| |
| #define | MXC_V_GCR_PMR_HIRC8PD_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PMR_HIRC8PD_ACTIVE (MXC_V_GCR_PMR_HIRC8PD_ACTIVE << MXC_F_GCR_PMR_HIRC8PD_POS) |
| |
| #define | MXC_V_GCR_PMR_HIRC8PD_DEEPSLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PMR_HIRC8PD_DEEPSLEEP (MXC_V_GCR_PMR_HIRC8PD_DEEPSLEEP << MXC_F_GCR_PMR_HIRC8PD_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS 7 |
| |
| #define | MXC_F_GCR_PCLK_DIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIV_SDHCFRQ_60M ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_SDHCFRQ_60M (MXC_V_GCR_PCLK_DIV_SDHCFRQ_60M << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_SDHCFRQ_50M ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_SDHCFRQ_50M (MXC_V_GCR_PCLK_DIV_SDHCFRQ_50M << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIV_ADCFRQ_POS 10 |
| |
| #define | MXC_F_GCR_PCLK_DIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV2 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV2 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV3 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV3 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV4 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV4 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV5 ((uint32_t)0x5UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV5 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV5 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV6 ((uint32_t)0x6UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV6 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV6 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV7 ((uint32_t)0x7UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV7 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV7 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV8 ((uint32_t)0x8UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV8 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV8 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV9 ((uint32_t)0x9UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV9 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV9 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV10 ((uint32_t)0xAUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV10 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV10 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV11 ((uint32_t)0xBUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV11 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV11 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV12 ((uint32_t)0xCUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV12 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV12 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV13 ((uint32_t)0xDUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV13 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV13 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV14 ((uint32_t)0xEUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV14 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV14 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV15 ((uint32_t)0xFUL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV15 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV15 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIV_AONDIV_POS 14 |
| |
| #define | MXC_F_GCR_PCLK_DIV_AONDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIV_AONDIV_DIV4 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_AONDIV_DIV4 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_AONDIV_DIV8 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_AONDIV_DIV8 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_AONDIV_DIV16 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_AONDIV_DIV16 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIV_AONDIV_DIV32 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_GCR_PCLK_DIV_AONDIV_DIV32 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO0_POS 0 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO0_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO0_EN (MXC_V_GCR_PCLK_DIS0_GPIO0_EN << MXC_F_GCR_PCLK_DIS0_GPIO0_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO0_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO0_DIS (MXC_V_GCR_PCLK_DIS0_GPIO0_DIS << MXC_F_GCR_PCLK_DIS0_GPIO0_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO1_POS 1 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO1_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO1_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO1_EN (MXC_V_GCR_PCLK_DIS0_GPIO1_EN << MXC_F_GCR_PCLK_DIS0_GPIO1_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO1_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO1_DIS (MXC_V_GCR_PCLK_DIS0_GPIO1_DIS << MXC_F_GCR_PCLK_DIS0_GPIO1_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO2_POS 2 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO2_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO2_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO2_EN (MXC_V_GCR_PCLK_DIS0_GPIO2_EN << MXC_F_GCR_PCLK_DIS0_GPIO2_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_GPIO2_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_GPIO2_DIS (MXC_V_GCR_PCLK_DIS0_GPIO2_DIS << MXC_F_GCR_PCLK_DIS0_GPIO2_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_USB_POS 3 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_USB_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_USB_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_USB_EN (MXC_V_GCR_PCLK_DIS0_USB_EN << MXC_F_GCR_PCLK_DIS0_USB_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_USB_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_USB_DIS (MXC_V_GCR_PCLK_DIS0_USB_DIS << MXC_F_GCR_PCLK_DIS0_USB_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_TFT_POS 4 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_TFT ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TFT_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_TFT_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TFT_EN (MXC_V_GCR_PCLK_DIS0_TFT_EN << MXC_F_GCR_PCLK_DIS0_TFT_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_TFT_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TFT_DIS (MXC_V_GCR_PCLK_DIS0_TFT_DIS << MXC_F_GCR_PCLK_DIS0_TFT_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_DMA_POS 5 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMA_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_DMA_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_DMA_EN (MXC_V_GCR_PCLK_DIS0_DMA_EN << MXC_F_GCR_PCLK_DIS0_DMA_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_DMA_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_DMA_DIS (MXC_V_GCR_PCLK_DIS0_DMA_DIS << MXC_F_GCR_PCLK_DIS0_DMA_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI0_POS 6 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI0_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI0_EN (MXC_V_GCR_PCLK_DIS0_SPI0_EN << MXC_F_GCR_PCLK_DIS0_SPI0_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI0_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI0_DIS (MXC_V_GCR_PCLK_DIS0_SPI0_DIS << MXC_F_GCR_PCLK_DIS0_SPI0_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI1_POS 7 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI1_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI1_EN (MXC_V_GCR_PCLK_DIS0_SPI1_EN << MXC_F_GCR_PCLK_DIS0_SPI1_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI1_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI1_DIS (MXC_V_GCR_PCLK_DIS0_SPI1_DIS << MXC_F_GCR_PCLK_DIS0_SPI1_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI2_POS 8 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI2_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI2_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI2_EN (MXC_V_GCR_PCLK_DIS0_SPI2_EN << MXC_F_GCR_PCLK_DIS0_SPI2_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPI2_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPI2_DIS (MXC_V_GCR_PCLK_DIS0_SPI2_DIS << MXC_F_GCR_PCLK_DIS0_SPI2_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_UART0_POS 9 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_UART0_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_UART0_EN (MXC_V_GCR_PCLK_DIS0_UART0_EN << MXC_F_GCR_PCLK_DIS0_UART0_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_UART0_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_UART0_DIS (MXC_V_GCR_PCLK_DIS0_UART0_DIS << MXC_F_GCR_PCLK_DIS0_UART0_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_UART1_POS 10 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_UART1_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_UART1_EN (MXC_V_GCR_PCLK_DIS0_UART1_EN << MXC_F_GCR_PCLK_DIS0_UART1_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_UART1_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_UART1_DIS (MXC_V_GCR_PCLK_DIS0_UART1_DIS << MXC_F_GCR_PCLK_DIS0_UART1_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_I2C0_POS 13 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_I2C0_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_I2C0_EN (MXC_V_GCR_PCLK_DIS0_I2C0_EN << MXC_F_GCR_PCLK_DIS0_I2C0_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_I2C0_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_I2C0_DIS (MXC_V_GCR_PCLK_DIS0_I2C0_DIS << MXC_F_GCR_PCLK_DIS0_I2C0_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_TPU_POS 14 |
| |
| #define | MXC_F_GCR_PCLK_DIS0_TPU ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TPU_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TPU_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TPU_EN (MXC_V_GCR_PCLK_DIS0_TPU_EN << MXC_F_GCR_PCLK_DIS0_TPU_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TPU_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TPU_DIS (MXC_V_GCR_PCLK_DIS0_TPU_DIS << MXC_F_GCR_PCLK_DIS0_TPU_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER0_POS 15 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER0_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TIMER0_EN (MXC_V_GCR_PCLK_DIS0_TIMER0_EN << MXC_F_GCR_PCLK_DIS0_TIMER0_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER0_DIS ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TIMER0_DIS (MXC_V_GCR_PCLK_DIS0_TIMER0_DIS << MXC_F_GCR_PCLK_DIS0_TIMER0_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER1_POS 16 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER1_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TIMER1_EN (MXC_V_GCR_PCLK_DIS0_TIMER1_EN << MXC_F_GCR_PCLK_DIS0_TIMER1_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER1_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER1_DIS (MXC_V_GCR_PCLK_DIS0_TIMER1_DIS << MXC_F_GCR_PCLK_DIS0_TIMER1_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER2_POS 17 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER2_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TIMER2_EN (MXC_V_GCR_PCLK_DIS0_TIMER2_EN << MXC_F_GCR_PCLK_DIS0_TIMER2_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER2_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER2_DIS (MXC_V_GCR_PCLK_DIS0_TIMER2_DIS << MXC_F_GCR_PCLK_DIS0_TIMER2_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER3_POS 18 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER3_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER3_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER3_EN (MXC_V_GCR_PCLK_DIS0_TIMER3_EN << MXC_F_GCR_PCLK_DIS0_TIMER3_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER3_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER3_DIS (MXC_V_GCR_PCLK_DIS0_TIMER3_DIS << MXC_F_GCR_PCLK_DIS0_TIMER3_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER4_POS 19 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER4_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER4_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_TIMER4_EN (MXC_V_GCR_PCLK_DIS0_TIMER4_EN << MXC_F_GCR_PCLK_DIS0_TIMER4_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER4_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER4_DIS (MXC_V_GCR_PCLK_DIS0_TIMER4_DIS << MXC_F_GCR_PCLK_DIS0_TIMER4_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER5_POS 20 |
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| #define | MXC_F_GCR_PCLK_DIS0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER5_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER5_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER5_EN (MXC_V_GCR_PCLK_DIS0_TIMER5_EN << MXC_F_GCR_PCLK_DIS0_TIMER5_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_TIMER5_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_TIMER5_DIS (MXC_V_GCR_PCLK_DIS0_TIMER5_DIS << MXC_F_GCR_PCLK_DIS0_TIMER5_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_ADC_POS 23 |
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| #define | MXC_F_GCR_PCLK_DIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_ADC_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_ADC_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS0_ADC_EN (MXC_V_GCR_PCLK_DIS0_ADC_EN << MXC_F_GCR_PCLK_DIS0_ADC_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_ADC_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_ADC_DIS (MXC_V_GCR_PCLK_DIS0_ADC_DIS << MXC_F_GCR_PCLK_DIS0_ADC_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_I2C1_POS 28 |
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| #define | MXC_F_GCR_PCLK_DIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_I2C1_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_I2C1_EN (MXC_V_GCR_PCLK_DIS0_I2C1_EN << MXC_F_GCR_PCLK_DIS0_I2C1_POS) |
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| #define | MXC_V_GCR_PCLK_DIS0_I2C1_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_I2C1_DIS (MXC_V_GCR_PCLK_DIS0_I2C1_DIS << MXC_F_GCR_PCLK_DIS0_I2C1_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_PT_POS 29 |
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| #define | MXC_F_GCR_PCLK_DIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_PT_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_PT_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_PT_EN (MXC_V_GCR_PCLK_DIS0_PT_EN << MXC_F_GCR_PCLK_DIS0_PT_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_PT_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_PT_DIS (MXC_V_GCR_PCLK_DIS0_PT_DIS << MXC_F_GCR_PCLK_DIS0_PT_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS 30 |
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| #define | MXC_F_GCR_PCLK_DIS0_SPIXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS0_SPIXIPF_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPIXIPF_EN (MXC_V_GCR_PCLK_DIS0_SPIXIPF_EN << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPIXIPF_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPIXIPF_DIS (MXC_V_GCR_PCLK_DIS0_SPIXIPF_DIS << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS) |
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| #define | MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS 31 |
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| #define | MXC_F_GCR_PCLK_DIS0_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPIXIPM_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPIXIPM_EN (MXC_V_GCR_PCLK_DIS0_SPIXIPM_EN << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS0_SPIXIPM_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS0_SPIXIPM_DIS (MXC_V_GCR_PCLK_DIS0_SPIXIPM_DIS << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS) |
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| #define | MXC_F_GCR_MEM_CLK_FWS_POS 0 |
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| #define | MXC_F_GCR_MEM_CLK_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CLK_FWS_POS)) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS 16 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS 17 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS 18 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS 19 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS 20 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM4LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM4LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM4LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS 21 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM5LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM5LS_ACTIVE ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_MEM_CLK_SYSRAM5LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM5LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS 22 |
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| #define | MXC_F_GCR_MEM_CLK_SYSRAM6LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM6LS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_SYSRAM6LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM6LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_ICACHELS_POS 24 |
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| #define | MXC_F_GCR_MEM_CLK_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHELS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_ICACHELS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ICACHELS_ACTIVE (MXC_V_GCR_MEM_CLK_ICACHELS_ACTIVE << MXC_F_GCR_MEM_CLK_ICACHELS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ICACHELS_POS) |
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| #define | MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS 25 |
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| #define | MXC_F_GCR_MEM_CLK_ICACHEXIPLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS)) |
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| #define | MXC_V_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE (MXC_V_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS) |
| |
| #define | MXC_V_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS) |
| |
| #define | MXC_F_GCR_MEM_CLK_SCACHELS_POS 26 |
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| #define | MXC_F_GCR_MEM_CLK_SCACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SCACHELS_POS)) |
| |
| #define | MXC_V_GCR_MEM_CLK_SCACHELS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_SCACHELS_ACTIVE (MXC_V_GCR_MEM_CLK_SCACHELS_ACTIVE << MXC_F_GCR_MEM_CLK_SCACHELS_POS) |
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| #define | MXC_V_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SCACHELS_POS) |
| |
| #define | MXC_F_GCR_MEM_CLK_CRYPTOLS_POS 27 |
| |
| #define | MXC_F_GCR_MEM_CLK_CRYPTOLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS)) |
| |
| #define | MXC_V_GCR_MEM_CLK_CRYPTOLS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_CRYPTOLS_ACTIVE (MXC_V_GCR_MEM_CLK_CRYPTOLS_ACTIVE << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS) |
| |
| #define | MXC_V_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS) |
| |
| #define | MXC_F_GCR_MEM_CLK_USBLS_POS 28 |
| |
| #define | MXC_F_GCR_MEM_CLK_USBLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_USBLS_POS)) |
| |
| #define | MXC_V_GCR_MEM_CLK_USBLS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_USBLS_ACTIVE (MXC_V_GCR_MEM_CLK_USBLS_ACTIVE << MXC_F_GCR_MEM_CLK_USBLS_POS) |
| |
| #define | MXC_V_GCR_MEM_CLK_USBLS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_USBLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_USBLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_USBLS_POS) |
| |
| #define | MXC_F_GCR_MEM_CLK_ROMLS_POS 29 |
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| #define | MXC_F_GCR_MEM_CLK_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROMLS_POS)) |
| |
| #define | MXC_V_GCR_MEM_CLK_ROMLS_ACTIVE ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ROMLS_ACTIVE (MXC_V_GCR_MEM_CLK_ROMLS_ACTIVE << MXC_F_GCR_MEM_CLK_ROMLS_POS) |
| |
| #define | MXC_V_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ROMLS_POS) |
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| #define | MXC_F_GCR_MEM_ZERO_SRAM0Z_POS 0 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM0Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM0Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM0Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM0Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM0Z_START (MXC_V_GCR_MEM_ZERO_SRAM0Z_START << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM1Z_POS 1 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM1Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM1Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM1Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM1Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM1Z_START (MXC_V_GCR_MEM_ZERO_SRAM1Z_START << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM2Z_POS 2 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM2Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM2Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM2Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM2Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM2Z_START (MXC_V_GCR_MEM_ZERO_SRAM2Z_START << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM3Z_POS 3 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM3Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM3Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM3Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM3Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM3Z_START (MXC_V_GCR_MEM_ZERO_SRAM3Z_START << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM4Z_POS 4 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM4Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM4Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM4Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM4Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM4Z_START (MXC_V_GCR_MEM_ZERO_SRAM4Z_START << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM5Z_POS 5 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM5Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM5Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM5Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM5Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM5Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM5Z_START (MXC_V_GCR_MEM_ZERO_SRAM5Z_START << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM6Z_POS 6 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SRAM6Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM6Z_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM6Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM6Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SRAM6Z_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SRAM6Z_START (MXC_V_GCR_MEM_ZERO_SRAM6Z_START << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_ICACHEZ_POS 8 |
| |
| #define | MXC_F_GCR_MEM_ZERO_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_ICACHEZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_ICACHEZ_NOP (MXC_V_GCR_MEM_ZERO_ICACHEZ_NOP << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_ICACHEZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_ICACHEZ_START (MXC_V_GCR_MEM_ZERO_ICACHEZ_START << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS 9 |
| |
| #define | MXC_F_GCR_MEM_ZERO_ICACHEXIPZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_ICACHEXIPZ_NOP (MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_NOP << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_ICACHEXIPZ_START (MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_START << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS 10 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SCACHEDATAZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SCACHEDATAZ_NOP (MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_NOP << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SCACHEDATAZ_START (MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_START << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS 11 |
| |
| #define | MXC_F_GCR_MEM_ZERO_SCACHETAGZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SCACHETAGZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SCACHETAGZ_NOP (MXC_V_GCR_MEM_ZERO_SCACHETAGZ_NOP << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_SCACHETAGZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_SCACHETAGZ_START (MXC_V_GCR_MEM_ZERO_SCACHETAGZ_START << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS 12 |
| |
| #define | MXC_F_GCR_MEM_ZERO_CRYPTOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_CRYPTOZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_CRYPTOZ_NOP (MXC_V_GCR_MEM_ZERO_CRYPTOZ_NOP << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_CRYPTOZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_CRYPTOZ_START (MXC_V_GCR_MEM_ZERO_CRYPTOZ_START << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS) |
| |
| #define | MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS 13 |
| |
| #define | MXC_F_GCR_MEM_ZERO_USBFIFOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS)) |
| |
| #define | MXC_V_GCR_MEM_ZERO_USBFIFOZ_NOP ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_USBFIFOZ_NOP (MXC_V_GCR_MEM_ZERO_USBFIFOZ_NOP << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS) |
| |
| #define | MXC_V_GCR_MEM_ZERO_USBFIFOZ_START ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_MEM_ZERO_USBFIFOZ_START (MXC_V_GCR_MEM_ZERO_USBFIFOZ_START << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS) |
| |
| #define | MXC_F_GCR_SYS_STAT_ICELOCK_POS 0 |
| |
| #define | MXC_F_GCR_SYS_STAT_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICELOCK_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_ICELOCK_UNLOCKED ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_ICELOCK_UNLOCKED (MXC_V_GCR_SYS_STAT_ICELOCK_UNLOCKED << MXC_F_GCR_SYS_STAT_ICELOCK_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_ICELOCK_LOCKED ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_ICELOCK_LOCKED (MXC_V_GCR_SYS_STAT_ICELOCK_LOCKED << MXC_F_GCR_SYS_STAT_ICELOCK_POS) |
| |
| #define | MXC_F_GCR_SYS_STAT_CODEINTERR_POS 1 |
| |
| #define | MXC_F_GCR_SYS_STAT_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_CODEINTERR_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_CODEINTERR_NOERR ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_CODEINTERR_NOERR (MXC_V_GCR_SYS_STAT_CODEINTERR_NOERR << MXC_F_GCR_SYS_STAT_CODEINTERR_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_CODEINTERR_ERR ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_CODEINTERR_ERR (MXC_V_GCR_SYS_STAT_CODEINTERR_ERR << MXC_F_GCR_SYS_STAT_CODEINTERR_POS) |
| |
| #define | MXC_F_GCR_SYS_STAT_SCMEMF_POS 5 |
| |
| #define | MXC_F_GCR_SYS_STAT_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_SCMEMF_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_SCMEMF_NOERR ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_SCMEMF_NOERR (MXC_V_GCR_SYS_STAT_SCMEMF_NOERR << MXC_F_GCR_SYS_STAT_SCMEMF_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_SCMEMF_MEMFAULT ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_SCMEMF_MEMFAULT (MXC_V_GCR_SYS_STAT_SCMEMF_MEMFAULT << MXC_F_GCR_SYS_STAT_SCMEMF_POS) |
| |
| #define | MXC_F_GCR_RST1_I2C1_POS 0 |
| |
| #define | MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) |
| |
| #define | MXC_F_GCR_RST1_PT_POS 1 |
| |
| #define | MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) |
| |
| #define | MXC_F_GCR_RST1_SPIXIP_POS 3 |
| |
| #define | MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) |
| |
| #define | MXC_F_GCR_RST1_XSPIM_POS 4 |
| |
| #define | MXC_F_GCR_RST1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS)) |
| |
| #define | MXC_F_GCR_RST1_GPIO3_POS 5 |
| |
| #define | MXC_F_GCR_RST1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_GPIO3_POS)) |
| |
| #define | MXC_F_GCR_RST1_SDHC_POS 6 |
| |
| #define | MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS)) |
| |
| #define | MXC_F_GCR_RST1_OWIRE_POS 7 |
| |
| #define | MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) |
| |
| #define | MXC_F_GCR_RST1_WDT1_POS 8 |
| |
| #define | MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) |
| |
| #define | MXC_F_GCR_RST1_SPI3_POS 9 |
| |
| #define | MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) |
| |
| #define | MXC_F_GCR_RST1_I2S_POS 10 |
| |
| #define | MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) |
| |
| #define | MXC_F_GCR_RST1_XIPR_POS 15 |
| |
| #define | MXC_F_GCR_RST1_XIPR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS)) |
| |
| #define | MXC_F_GCR_RST1_SEMA_POS 16 |
| |
| #define | MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_UART2_POS 1 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_UART2_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_UART2_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_UART2_EN (MXC_V_GCR_PCLK_DIS1_UART2_EN << MXC_F_GCR_PCLK_DIS1_UART2_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_UART2_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_UART2_DIS (MXC_V_GCR_PCLK_DIS1_UART2_DIS << MXC_F_GCR_PCLK_DIS1_UART2_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_TRNG_POS 2 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_TRNG_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_TRNG_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_TRNG_EN (MXC_V_GCR_PCLK_DIS1_TRNG_EN << MXC_F_GCR_PCLK_DIS1_TRNG_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_TRNG_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_TRNG_DIS (MXC_V_GCR_PCLK_DIS1_TRNG_DIS << MXC_F_GCR_PCLK_DIS1_TRNG_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SFLC_POS 3 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SFLC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SFLC_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SFLC_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SFLC_EN (MXC_V_GCR_PCLK_DIS1_SFLC_EN << MXC_F_GCR_PCLK_DIS1_SFLC_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SFLC_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SFLC_DIS (MXC_V_GCR_PCLK_DIS1_SFLC_DIS << MXC_F_GCR_PCLK_DIS1_SFLC_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_HBC_POS 4 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_HBC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HBC_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_HBC_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_HBC_EN (MXC_V_GCR_PCLK_DIS1_HBC_EN << MXC_F_GCR_PCLK_DIS1_HBC_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_HBC_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_HBC_DIS (MXC_V_GCR_PCLK_DIS1_HBC_DIS << MXC_F_GCR_PCLK_DIS1_HBC_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_GPIO3_POS 6 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_GPIO3_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_GPIO3_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_GPIO3_EN (MXC_V_GCR_PCLK_DIS1_GPIO3_EN << MXC_F_GCR_PCLK_DIS1_GPIO3_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_GPIO3_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_GPIO3_DIS (MXC_V_GCR_PCLK_DIS1_GPIO3_DIS << MXC_F_GCR_PCLK_DIS1_GPIO3_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SCACHE_POS 7 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SCACHE_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SCACHE_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SCACHE_EN (MXC_V_GCR_PCLK_DIS1_SCACHE_EN << MXC_F_GCR_PCLK_DIS1_SCACHE_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SCACHE_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SCACHE_DIS (MXC_V_GCR_PCLK_DIS1_SCACHE_DIS << MXC_F_GCR_PCLK_DIS1_SCACHE_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SDMA_POS 8 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SDMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDMA_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SDMA_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SDMA_EN (MXC_V_GCR_PCLK_DIS1_SDMA_EN << MXC_F_GCR_PCLK_DIS1_SDMA_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SDMA_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SDMA_DIS (MXC_V_GCR_PCLK_DIS1_SDMA_DIS << MXC_F_GCR_PCLK_DIS1_SDMA_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SEMA_POS 9 |
| |
| #define | MXC_F_GCR_PCLK_DIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SEMA_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SEMA_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SEMA_EN (MXC_V_GCR_PCLK_DIS1_SEMA_EN << MXC_F_GCR_PCLK_DIS1_SEMA_POS) |
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| #define | MXC_V_GCR_PCLK_DIS1_SEMA_DIS ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_PCLK_DIS1_SEMA_DIS (MXC_V_GCR_PCLK_DIS1_SEMA_DIS << MXC_F_GCR_PCLK_DIS1_SEMA_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_SDHC_POS 10 |
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| #define | MXC_F_GCR_PCLK_DIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDHC_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS1_SDHC_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS1_SDHC_EN (MXC_V_GCR_PCLK_DIS1_SDHC_EN << MXC_F_GCR_PCLK_DIS1_SDHC_POS) |
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| #define | MXC_V_GCR_PCLK_DIS1_SDHC_DIS ((uint32_t)0x1UL) |
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| #define | MXC_S_GCR_PCLK_DIS1_SDHC_DIS (MXC_V_GCR_PCLK_DIS1_SDHC_DIS << MXC_F_GCR_PCLK_DIS1_SDHC_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_ICACHE_POS 11 |
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| #define | MXC_F_GCR_PCLK_DIS1_ICACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHE_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS1_ICACHE_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS1_ICACHE_EN (MXC_V_GCR_PCLK_DIS1_ICACHE_EN << MXC_F_GCR_PCLK_DIS1_ICACHE_POS) |
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| #define | MXC_V_GCR_PCLK_DIS1_ICACHE_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_ICACHE_DIS (MXC_V_GCR_PCLK_DIS1_ICACHE_DIS << MXC_F_GCR_PCLK_DIS1_ICACHE_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS 12 |
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| #define | MXC_F_GCR_PCLK_DIS1_ICACHEXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_ICACHEXIPF_EN (MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_EN << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS) |
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| #define | MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_ICACHEXIPF_DIS (MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_DIS << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_OW_POS 13 |
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| #define | MXC_F_GCR_PCLK_DIS1_OW ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_OW_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS1_OW_EN ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_PCLK_DIS1_OW_EN (MXC_V_GCR_PCLK_DIS1_OW_EN << MXC_F_GCR_PCLK_DIS1_OW_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_OW_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_OW_DIS (MXC_V_GCR_PCLK_DIS1_OW_DIS << MXC_F_GCR_PCLK_DIS1_OW_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_SPI3_POS 14 |
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| #define | MXC_F_GCR_PCLK_DIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPI3_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS1_SPI3_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SPI3_EN (MXC_V_GCR_PCLK_DIS1_SPI3_EN << MXC_F_GCR_PCLK_DIS1_SPI3_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SPI3_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SPI3_DIS (MXC_V_GCR_PCLK_DIS1_SPI3_DIS << MXC_F_GCR_PCLK_DIS1_SPI3_POS) |
| |
| #define | MXC_F_GCR_PCLK_DIS1_I2S_POS 15 |
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| #define | MXC_F_GCR_PCLK_DIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_I2S_POS)) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_I2S_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_I2S_EN (MXC_V_GCR_PCLK_DIS1_I2S_EN << MXC_F_GCR_PCLK_DIS1_I2S_POS) |
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| #define | MXC_V_GCR_PCLK_DIS1_I2S_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_I2S_DIS (MXC_V_GCR_PCLK_DIS1_I2S_DIS << MXC_F_GCR_PCLK_DIS1_I2S_POS) |
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| #define | MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS 20 |
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| #define | MXC_F_GCR_PCLK_DIS1_SPIXIPR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS)) |
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| #define | MXC_V_GCR_PCLK_DIS1_SPIXIPR_EN ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SPIXIPR_EN (MXC_V_GCR_PCLK_DIS1_SPIXIPR_EN << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS) |
| |
| #define | MXC_V_GCR_PCLK_DIS1_SPIXIPR_DIS ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_PCLK_DIS1_SPIXIPR_DIS (MXC_V_GCR_PCLK_DIS1_SPIXIPR_DIS << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS) |
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| #define | MXC_F_GCR_EVENT_EN_DMAEVENT_POS 0 |
| |
| #define | MXC_F_GCR_EVENT_EN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_DMAEVENT_POS)) |
| |
| #define | MXC_V_GCR_EVENT_EN_DMAEVENT_DIS ((uint32_t)0x0UL) |
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| #define | MXC_S_GCR_EVENT_EN_DMAEVENT_DIS (MXC_V_GCR_EVENT_EN_DMAEVENT_DIS << MXC_F_GCR_EVENT_EN_DMAEVENT_POS) |
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| #define | MXC_V_GCR_EVENT_EN_DMAEVENT_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_EVENT_EN_DMAEVENT_EN (MXC_V_GCR_EVENT_EN_DMAEVENT_EN << MXC_F_GCR_EVENT_EN_DMAEVENT_POS) |
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| #define | MXC_F_GCR_EVENT_EN_RXEVENT_POS 1 |
| |
| #define | MXC_F_GCR_EVENT_EN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_RXEVENT_POS)) |
| |
| #define | MXC_V_GCR_EVENT_EN_RXEVENT_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_EVENT_EN_RXEVENT_DIS (MXC_V_GCR_EVENT_EN_RXEVENT_DIS << MXC_F_GCR_EVENT_EN_RXEVENT_POS) |
| |
| #define | MXC_V_GCR_EVENT_EN_RXEVENT_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_EVENT_EN_RXEVENT_EN (MXC_V_GCR_EVENT_EN_RXEVENT_EN << MXC_F_GCR_EVENT_EN_RXEVENT_POS) |
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| #define | MXC_F_GCR_EVENT_EN_TXEVENT_POS 2 |
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| #define | MXC_F_GCR_EVENT_EN_TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_TXEVENT_POS)) |
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| #define | MXC_V_GCR_EVENT_EN_TXEVENT_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_EVENT_EN_TXEVENT_DIS (MXC_V_GCR_EVENT_EN_TXEVENT_DIS << MXC_F_GCR_EVENT_EN_TXEVENT_POS) |
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| #define | MXC_V_GCR_EVENT_EN_TXEVENT_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_EVENT_EN_TXEVENT_EN (MXC_V_GCR_EVENT_EN_TXEVENT_EN << MXC_F_GCR_EVENT_EN_TXEVENT_POS) |
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| #define | MXC_F_GCR_REV_REVISION_POS 0 |
| |
| #define | MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS 0 |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_ICEULIE_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_ICEULIE_DIS (MXC_V_GCR_SYS_STAT_IE_ICEULIE_DIS << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_ICEULIE_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_ICEULIE_EN (MXC_V_GCR_SYS_STAT_IE_ICEULIE_EN << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS) |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_CIEIE_POS 1 |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_CIEIE_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_CIEIE_DIS (MXC_V_GCR_SYS_STAT_IE_CIEIE_DIS << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_CIEIE_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_CIEIE_EN (MXC_V_GCR_SYS_STAT_IE_CIEIE_EN << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS) |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS 5 |
| |
| #define | MXC_F_GCR_SYS_STAT_IE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS)) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_SCMFIE_DIS ((uint32_t)0x0UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_SCMFIE_DIS (MXC_V_GCR_SYS_STAT_IE_SCMFIE_DIS << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS) |
| |
| #define | MXC_V_GCR_SYS_STAT_IE_SCMFIE_EN ((uint32_t)0x1UL) |
| |
| #define | MXC_S_GCR_SYS_STAT_IE_SCMFIE_EN (MXC_V_GCR_SYS_STAT_IE_SCMFIE_EN << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS) |
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1.9.4