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#define | MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) |
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#define | MXC_R_I2C_STAT ((uint32_t)0x00000004UL) |
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#define | MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) |
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#define | MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) |
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#define | MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) |
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#define | MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) |
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#define | MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) |
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#define | MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) |
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#define | MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) |
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#define | MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) |
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#define | MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) |
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#define | MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) |
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#define | MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) |
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#define | MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) |
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#define | MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) |
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#define | MXC_R_I2C_SLV_ADDR ((uint32_t)0x00000044UL) |
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#define | MXC_R_I2C_DMA ((uint32_t)0x00000048UL) |
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#define | MXC_F_I2C_CTRL0_I2CEN_POS 0 |
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#define | MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) |
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#define | MXC_V_I2C_CTRL0_I2CEN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_I2CEN_DIS (MXC_V_I2C_CTRL0_I2CEN_DIS << MXC_F_I2C_CTRL0_I2CEN_POS) |
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#define | MXC_V_I2C_CTRL0_I2CEN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_I2CEN_EN (MXC_V_I2C_CTRL0_I2CEN_EN << MXC_F_I2C_CTRL0_I2CEN_POS) |
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#define | MXC_F_I2C_CTRL0_MST_POS 1 |
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#define | MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) |
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#define | MXC_V_I2C_CTRL0_MST_SLAVE_MODE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_MST_SLAVE_MODE (MXC_V_I2C_CTRL0_MST_SLAVE_MODE << MXC_F_I2C_CTRL0_MST_POS) |
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#define | MXC_V_I2C_CTRL0_MST_MASTER_MODE ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_MST_MASTER_MODE (MXC_V_I2C_CTRL0_MST_MASTER_MODE << MXC_F_I2C_CTRL0_MST_POS) |
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#define | MXC_F_I2C_CTRL0_GCEN_POS 2 |
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#define | MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) |
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#define | MXC_V_I2C_CTRL0_GCEN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_GCEN_DIS (MXC_V_I2C_CTRL0_GCEN_DIS << MXC_F_I2C_CTRL0_GCEN_POS) |
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#define | MXC_V_I2C_CTRL0_GCEN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_GCEN_EN (MXC_V_I2C_CTRL0_GCEN_EN << MXC_F_I2C_CTRL0_GCEN_POS) |
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#define | MXC_F_I2C_CTRL0_IRXM_POS 3 |
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#define | MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) |
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#define | MXC_V_I2C_CTRL0_IRXM_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_IRXM_DIS (MXC_V_I2C_CTRL0_IRXM_DIS << MXC_F_I2C_CTRL0_IRXM_POS) |
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#define | MXC_V_I2C_CTRL0_IRXM_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_IRXM_EN (MXC_V_I2C_CTRL0_IRXM_EN << MXC_F_I2C_CTRL0_IRXM_POS) |
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#define | MXC_F_I2C_CTRL0_ACK_POS 4 |
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#define | MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) |
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#define | MXC_V_I2C_CTRL0_ACK_ACK ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_ACK_ACK (MXC_V_I2C_CTRL0_ACK_ACK << MXC_F_I2C_CTRL0_ACK_POS) |
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#define | MXC_V_I2C_CTRL0_ACK_NACK ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_ACK_NACK (MXC_V_I2C_CTRL0_ACK_NACK << MXC_F_I2C_CTRL0_ACK_POS) |
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#define | MXC_F_I2C_CTRL0_SCL_OUT_POS 6 |
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#define | MXC_F_I2C_CTRL0_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_OUT_POS)) |
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#define | MXC_V_I2C_CTRL0_SCL_OUT_LOW ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SCL_OUT_LOW (MXC_V_I2C_CTRL0_SCL_OUT_LOW << MXC_F_I2C_CTRL0_SCL_OUT_POS) |
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#define | MXC_V_I2C_CTRL0_SCL_OUT_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SCL_OUT_HIGH (MXC_V_I2C_CTRL0_SCL_OUT_HIGH << MXC_F_I2C_CTRL0_SCL_OUT_POS) |
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#define | MXC_F_I2C_CTRL0_SDA_OUT_POS 7 |
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#define | MXC_F_I2C_CTRL0_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_OUT_POS)) |
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#define | MXC_V_I2C_CTRL0_SDA_OUT_LOW ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SDA_OUT_LOW (MXC_V_I2C_CTRL0_SDA_OUT_LOW << MXC_F_I2C_CTRL0_SDA_OUT_POS) |
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#define | MXC_V_I2C_CTRL0_SDA_OUT_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SDA_OUT_HIGH (MXC_V_I2C_CTRL0_SDA_OUT_HIGH << MXC_F_I2C_CTRL0_SDA_OUT_POS) |
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#define | MXC_F_I2C_CTRL0_SCL_POS 8 |
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#define | MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) |
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#define | MXC_V_I2C_CTRL0_SCL_LOW ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SCL_LOW (MXC_V_I2C_CTRL0_SCL_LOW << MXC_F_I2C_CTRL0_SCL_POS) |
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#define | MXC_V_I2C_CTRL0_SCL_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SCL_HIGH (MXC_V_I2C_CTRL0_SCL_HIGH << MXC_F_I2C_CTRL0_SCL_POS) |
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#define | MXC_F_I2C_CTRL0_SDA_POS 9 |
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#define | MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) |
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#define | MXC_V_I2C_CTRL0_SDA_LOW ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SDA_LOW (MXC_V_I2C_CTRL0_SDA_LOW << MXC_F_I2C_CTRL0_SDA_POS) |
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#define | MXC_V_I2C_CTRL0_SDA_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SDA_HIGH (MXC_V_I2C_CTRL0_SDA_HIGH << MXC_F_I2C_CTRL0_SDA_POS) |
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#define | MXC_F_I2C_CTRL0_SWOE_POS 10 |
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#define | MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) |
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#define | MXC_V_I2C_CTRL0_SWOE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SWOE_DIS (MXC_V_I2C_CTRL0_SWOE_DIS << MXC_F_I2C_CTRL0_SWOE_POS) |
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#define | MXC_V_I2C_CTRL0_SWOE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SWOE_EN (MXC_V_I2C_CTRL0_SWOE_EN << MXC_F_I2C_CTRL0_SWOE_POS) |
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#define | MXC_F_I2C_CTRL0_READ_POS 11 |
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#define | MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) |
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#define | MXC_V_I2C_CTRL0_READ_WRITE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_READ_WRITE (MXC_V_I2C_CTRL0_READ_WRITE << MXC_F_I2C_CTRL0_READ_POS) |
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#define | MXC_V_I2C_CTRL0_READ_READ ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_READ_READ (MXC_V_I2C_CTRL0_READ_READ << MXC_F_I2C_CTRL0_READ_POS) |
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#define | MXC_F_I2C_CTRL0_SCL_STRD_POS 12 |
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#define | MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) |
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#define | MXC_V_I2C_CTRL0_SCL_STRD_EN ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SCL_STRD_EN (MXC_V_I2C_CTRL0_SCL_STRD_EN << MXC_F_I2C_CTRL0_SCL_STRD_POS) |
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#define | MXC_V_I2C_CTRL0_SCL_STRD_DIS ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SCL_STRD_DIS (MXC_V_I2C_CTRL0_SCL_STRD_DIS << MXC_F_I2C_CTRL0_SCL_STRD_POS) |
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#define | MXC_F_I2C_CTRL0_SCL_PPM_POS 13 |
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#define | MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) |
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#define | MXC_V_I2C_CTRL0_SCL_PPM_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_CTRL0_SCL_PPM_DIS (MXC_V_I2C_CTRL0_SCL_PPM_DIS << MXC_F_I2C_CTRL0_SCL_PPM_POS) |
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#define | MXC_V_I2C_CTRL0_SCL_PPM_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_CTRL0_SCL_PPM_EN (MXC_V_I2C_CTRL0_SCL_PPM_EN << MXC_F_I2C_CTRL0_SCL_PPM_POS) |
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#define | MXC_F_I2C_STAT_BUSY_POS 0 |
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#define | MXC_F_I2C_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STAT_BUSY_POS)) |
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#define | MXC_V_I2C_STAT_BUSY_IDLE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_BUSY_IDLE (MXC_V_I2C_STAT_BUSY_IDLE << MXC_F_I2C_STAT_BUSY_POS) |
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#define | MXC_V_I2C_STAT_BUSY_BUSY ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_BUSY_BUSY (MXC_V_I2C_STAT_BUSY_BUSY << MXC_F_I2C_STAT_BUSY_POS) |
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#define | MXC_F_I2C_STAT_RXE_POS 1 |
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#define | MXC_F_I2C_STAT_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STAT_RXE_POS)) |
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#define | MXC_V_I2C_STAT_RXE_NOT_EMPTY ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_RXE_NOT_EMPTY (MXC_V_I2C_STAT_RXE_NOT_EMPTY << MXC_F_I2C_STAT_RXE_POS) |
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#define | MXC_V_I2C_STAT_RXE_EMPTY ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_RXE_EMPTY (MXC_V_I2C_STAT_RXE_EMPTY << MXC_F_I2C_STAT_RXE_POS) |
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#define | MXC_F_I2C_STAT_RXF_POS 2 |
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#define | MXC_F_I2C_STAT_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STAT_RXF_POS)) |
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#define | MXC_V_I2C_STAT_RXF_NOT_FULL ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_RXF_NOT_FULL (MXC_V_I2C_STAT_RXF_NOT_FULL << MXC_F_I2C_STAT_RXF_POS) |
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#define | MXC_V_I2C_STAT_RXF_FULL ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_RXF_FULL (MXC_V_I2C_STAT_RXF_FULL << MXC_F_I2C_STAT_RXF_POS) |
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#define | MXC_F_I2C_STAT_TXE_POS 3 |
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#define | MXC_F_I2C_STAT_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STAT_TXE_POS)) |
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#define | MXC_V_I2C_STAT_TXE_NOT_EMPTY ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_TXE_NOT_EMPTY (MXC_V_I2C_STAT_TXE_NOT_EMPTY << MXC_F_I2C_STAT_TXE_POS) |
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#define | MXC_V_I2C_STAT_TXE_EMPTY ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_TXE_EMPTY (MXC_V_I2C_STAT_TXE_EMPTY << MXC_F_I2C_STAT_TXE_POS) |
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#define | MXC_F_I2C_STAT_TXF_POS 4 |
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#define | MXC_F_I2C_STAT_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STAT_TXF_POS)) |
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#define | MXC_V_I2C_STAT_TXF_NOT_FULL ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_TXF_NOT_FULL (MXC_V_I2C_STAT_TXF_NOT_FULL << MXC_F_I2C_STAT_TXF_POS) |
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#define | MXC_V_I2C_STAT_TXF_FULL ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_TXF_FULL (MXC_V_I2C_STAT_TXF_FULL << MXC_F_I2C_STAT_TXF_POS) |
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#define | MXC_F_I2C_STAT_CKMD_POS 5 |
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#define | MXC_F_I2C_STAT_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STAT_CKMD_POS)) |
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#define | MXC_V_I2C_STAT_CKMD_SCL_NOT_ACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STAT_CKMD_SCL_NOT_ACTIVE (MXC_V_I2C_STAT_CKMD_SCL_NOT_ACTIVE << MXC_F_I2C_STAT_CKMD_POS) |
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#define | MXC_V_I2C_STAT_CKMD_SCL_ACTIVE ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STAT_CKMD_SCL_ACTIVE (MXC_V_I2C_STAT_CKMD_SCL_ACTIVE << MXC_F_I2C_STAT_CKMD_POS) |
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#define | MXC_F_I2C_INT_FL0_DONEI_POS 0 |
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#define | MXC_F_I2C_INT_FL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONEI_POS)) |
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#define | MXC_V_I2C_INT_FL0_DONEI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_DONEI_INACTIVE (MXC_V_I2C_INT_FL0_DONEI_INACTIVE << MXC_F_I2C_INT_FL0_DONEI_POS) |
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#define | MXC_V_I2C_INT_FL0_DONEI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_DONEI_PENDING (MXC_V_I2C_INT_FL0_DONEI_PENDING << MXC_F_I2C_INT_FL0_DONEI_POS) |
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#define | MXC_F_I2C_INT_FL0_IRXMI_POS 1 |
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#define | MXC_F_I2C_INT_FL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_IRXMI_POS)) |
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#define | MXC_V_I2C_INT_FL0_IRXMI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_IRXMI_INACTIVE (MXC_V_I2C_INT_FL0_IRXMI_INACTIVE << MXC_F_I2C_INT_FL0_IRXMI_POS) |
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#define | MXC_V_I2C_INT_FL0_IRXMI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_IRXMI_PENDING (MXC_V_I2C_INT_FL0_IRXMI_PENDING << MXC_F_I2C_INT_FL0_IRXMI_POS) |
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#define | MXC_F_I2C_INT_FL0_GCI_POS 2 |
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#define | MXC_F_I2C_INT_FL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GCI_POS)) |
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#define | MXC_V_I2C_INT_FL0_GCI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_GCI_INACTIVE (MXC_V_I2C_INT_FL0_GCI_INACTIVE << MXC_F_I2C_INT_FL0_GCI_POS) |
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#define | MXC_V_I2C_INT_FL0_GCI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_GCI_PENDING (MXC_V_I2C_INT_FL0_GCI_PENDING << MXC_F_I2C_INT_FL0_GCI_POS) |
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#define | MXC_F_I2C_INT_FL0_AMI_POS 3 |
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#define | MXC_F_I2C_INT_FL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_AMI_POS)) |
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#define | MXC_V_I2C_INT_FL0_AMI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_AMI_INACTIVE (MXC_V_I2C_INT_FL0_AMI_INACTIVE << MXC_F_I2C_INT_FL0_AMI_POS) |
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#define | MXC_V_I2C_INT_FL0_AMI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_AMI_PENDING (MXC_V_I2C_INT_FL0_AMI_PENDING << MXC_F_I2C_INT_FL0_AMI_POS) |
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#define | MXC_F_I2C_INT_FL0_RXTHI_POS 4 |
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#define | MXC_F_I2C_INT_FL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RXTHI_POS)) |
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#define | MXC_V_I2C_INT_FL0_RXTHI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_RXTHI_INACTIVE (MXC_V_I2C_INT_FL0_RXTHI_INACTIVE << MXC_F_I2C_INT_FL0_RXTHI_POS) |
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#define | MXC_V_I2C_INT_FL0_RXTHI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_RXTHI_PENDING (MXC_V_I2C_INT_FL0_RXTHI_PENDING << MXC_F_I2C_INT_FL0_RXTHI_POS) |
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#define | MXC_F_I2C_INT_FL0_TXTHI_POS 5 |
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#define | MXC_F_I2C_INT_FL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TXTHI_POS)) |
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#define | MXC_V_I2C_INT_FL0_TXTHI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_TXTHI_INACTIVE (MXC_V_I2C_INT_FL0_TXTHI_INACTIVE << MXC_F_I2C_INT_FL0_TXTHI_POS) |
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#define | MXC_V_I2C_INT_FL0_TXTHI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_TXTHI_PENDING (MXC_V_I2C_INT_FL0_TXTHI_PENDING << MXC_F_I2C_INT_FL0_TXTHI_POS) |
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#define | MXC_F_I2C_INT_FL0_STOPI_POS 6 |
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#define | MXC_F_I2C_INT_FL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOPI_POS)) |
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#define | MXC_V_I2C_INT_FL0_STOPI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_STOPI_INACTIVE (MXC_V_I2C_INT_FL0_STOPI_INACTIVE << MXC_F_I2C_INT_FL0_STOPI_POS) |
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#define | MXC_V_I2C_INT_FL0_STOPI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_STOPI_PENDING (MXC_V_I2C_INT_FL0_STOPI_PENDING << MXC_F_I2C_INT_FL0_STOPI_POS) |
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#define | MXC_F_I2C_INT_FL0_ADRACKI_POS 7 |
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#define | MXC_F_I2C_INT_FL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADRACKI_POS)) |
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#define | MXC_V_I2C_INT_FL0_ADRACKI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_ADRACKI_INACTIVE (MXC_V_I2C_INT_FL0_ADRACKI_INACTIVE << MXC_F_I2C_INT_FL0_ADRACKI_POS) |
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#define | MXC_V_I2C_INT_FL0_ADRACKI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_ADRACKI_PENDING (MXC_V_I2C_INT_FL0_ADRACKI_PENDING << MXC_F_I2C_INT_FL0_ADRACKI_POS) |
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#define | MXC_F_I2C_INT_FL0_ARBERI_POS 8 |
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#define | MXC_F_I2C_INT_FL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARBERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_ARBERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_ARBERI_INACTIVE (MXC_V_I2C_INT_FL0_ARBERI_INACTIVE << MXC_F_I2C_INT_FL0_ARBERI_POS) |
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#define | MXC_V_I2C_INT_FL0_ARBERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_ARBERI_PENDING (MXC_V_I2C_INT_FL0_ARBERI_PENDING << MXC_F_I2C_INT_FL0_ARBERI_POS) |
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#define | MXC_F_I2C_INT_FL0_TOERI_POS 9 |
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#define | MXC_F_I2C_INT_FL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TOERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_TOERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_TOERI_INACTIVE (MXC_V_I2C_INT_FL0_TOERI_INACTIVE << MXC_F_I2C_INT_FL0_TOERI_POS) |
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#define | MXC_V_I2C_INT_FL0_TOERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_TOERI_PENDING (MXC_V_I2C_INT_FL0_TOERI_PENDING << MXC_F_I2C_INT_FL0_TOERI_POS) |
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#define | MXC_F_I2C_INT_FL0_ADRERI_POS 10 |
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#define | MXC_F_I2C_INT_FL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADRERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_ADRERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_ADRERI_INACTIVE (MXC_V_I2C_INT_FL0_ADRERI_INACTIVE << MXC_F_I2C_INT_FL0_ADRERI_POS) |
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#define | MXC_V_I2C_INT_FL0_ADRERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_ADRERI_PENDING (MXC_V_I2C_INT_FL0_ADRERI_PENDING << MXC_F_I2C_INT_FL0_ADRERI_POS) |
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#define | MXC_F_I2C_INT_FL0_DATAERI_POS 11 |
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#define | MXC_F_I2C_INT_FL0_DATAERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATAERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_DATAERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_DATAERI_INACTIVE (MXC_V_I2C_INT_FL0_DATAERI_INACTIVE << MXC_F_I2C_INT_FL0_DATAERI_POS) |
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#define | MXC_V_I2C_INT_FL0_DATAERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_DATAERI_PENDING (MXC_V_I2C_INT_FL0_DATAERI_PENDING << MXC_F_I2C_INT_FL0_DATAERI_POS) |
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#define | MXC_F_I2C_INT_FL0_DNRERI_POS 12 |
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#define | MXC_F_I2C_INT_FL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DNRERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_DNRERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_DNRERI_INACTIVE (MXC_V_I2C_INT_FL0_DNRERI_INACTIVE << MXC_F_I2C_INT_FL0_DNRERI_POS) |
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#define | MXC_V_I2C_INT_FL0_DNRERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_DNRERI_PENDING (MXC_V_I2C_INT_FL0_DNRERI_PENDING << MXC_F_I2C_INT_FL0_DNRERI_POS) |
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#define | MXC_F_I2C_INT_FL0_STRTERI_POS 13 |
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#define | MXC_F_I2C_INT_FL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STRTERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_STRTERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_STRTERI_INACTIVE (MXC_V_I2C_INT_FL0_STRTERI_INACTIVE << MXC_F_I2C_INT_FL0_STRTERI_POS) |
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#define | MXC_V_I2C_INT_FL0_STRTERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_STRTERI_PENDING (MXC_V_I2C_INT_FL0_STRTERI_PENDING << MXC_F_I2C_INT_FL0_STRTERI_POS) |
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#define | MXC_F_I2C_INT_FL0_STOPERI_POS 14 |
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#define | MXC_F_I2C_INT_FL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOPERI_POS)) |
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#define | MXC_V_I2C_INT_FL0_STOPERI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_STOPERI_INACTIVE (MXC_V_I2C_INT_FL0_STOPERI_INACTIVE << MXC_F_I2C_INT_FL0_STOPERI_POS) |
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#define | MXC_V_I2C_INT_FL0_STOPERI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_STOPERI_PENDING (MXC_V_I2C_INT_FL0_STOPERI_PENDING << MXC_F_I2C_INT_FL0_STOPERI_POS) |
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#define | MXC_F_I2C_INT_FL0_TXLOI_POS 15 |
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#define | MXC_F_I2C_INT_FL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TXLOI_POS)) |
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#define | MXC_V_I2C_INT_FL0_TXLOI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL0_TXLOI_INACTIVE (MXC_V_I2C_INT_FL0_TXLOI_INACTIVE << MXC_F_I2C_INT_FL0_TXLOI_POS) |
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#define | MXC_V_I2C_INT_FL0_TXLOI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL0_TXLOI_PENDING (MXC_V_I2C_INT_FL0_TXLOI_PENDING << MXC_F_I2C_INT_FL0_TXLOI_POS) |
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#define | MXC_F_I2C_INT_EN0_DONEIE_POS 0 |
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#define | MXC_F_I2C_INT_EN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONEIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_DONEIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_DONEIE_DIS (MXC_V_I2C_INT_EN0_DONEIE_DIS << MXC_F_I2C_INT_EN0_DONEIE_POS) |
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#define | MXC_V_I2C_INT_EN0_DONEIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_DONEIE_EN (MXC_V_I2C_INT_EN0_DONEIE_EN << MXC_F_I2C_INT_EN0_DONEIE_POS) |
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#define | MXC_F_I2C_INT_EN0_IRXMIE_POS 1 |
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#define | MXC_F_I2C_INT_EN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_IRXMIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_IRXMIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_IRXMIE_DIS (MXC_V_I2C_INT_EN0_IRXMIE_DIS << MXC_F_I2C_INT_EN0_IRXMIE_POS) |
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#define | MXC_V_I2C_INT_EN0_IRXMIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_IRXMIE_EN (MXC_V_I2C_INT_EN0_IRXMIE_EN << MXC_F_I2C_INT_EN0_IRXMIE_POS) |
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#define | MXC_F_I2C_INT_EN0_GCIE_POS 2 |
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#define | MXC_F_I2C_INT_EN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GCIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_GCIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_GCIE_DIS (MXC_V_I2C_INT_EN0_GCIE_DIS << MXC_F_I2C_INT_EN0_GCIE_POS) |
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#define | MXC_V_I2C_INT_EN0_GCIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_GCIE_EN (MXC_V_I2C_INT_EN0_GCIE_EN << MXC_F_I2C_INT_EN0_GCIE_POS) |
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#define | MXC_F_I2C_INT_EN0_AMIE_POS 3 |
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#define | MXC_F_I2C_INT_EN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_AMIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_AMIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_AMIE_DIS (MXC_V_I2C_INT_EN0_AMIE_DIS << MXC_F_I2C_INT_EN0_AMIE_POS) |
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#define | MXC_V_I2C_INT_EN0_AMIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_AMIE_EN (MXC_V_I2C_INT_EN0_AMIE_EN << MXC_F_I2C_INT_EN0_AMIE_POS) |
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#define | MXC_F_I2C_INT_EN0_RXTHIE_POS 4 |
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#define | MXC_F_I2C_INT_EN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RXTHIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_RXTHIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_RXTHIE_DIS (MXC_V_I2C_INT_EN0_RXTHIE_DIS << MXC_F_I2C_INT_EN0_RXTHIE_POS) |
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#define | MXC_V_I2C_INT_EN0_RXTHIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_RXTHIE_EN (MXC_V_I2C_INT_EN0_RXTHIE_EN << MXC_F_I2C_INT_EN0_RXTHIE_POS) |
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#define | MXC_F_I2C_INT_EN0_TXTHIE_POS 5 |
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#define | MXC_F_I2C_INT_EN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TXTHIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_TXTHIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_TXTHIE_DIS (MXC_V_I2C_INT_EN0_TXTHIE_DIS << MXC_F_I2C_INT_EN0_TXTHIE_POS) |
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#define | MXC_V_I2C_INT_EN0_TXTHIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_TXTHIE_EN (MXC_V_I2C_INT_EN0_TXTHIE_EN << MXC_F_I2C_INT_EN0_TXTHIE_POS) |
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#define | MXC_F_I2C_INT_EN0_STOPIE_POS 6 |
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#define | MXC_F_I2C_INT_EN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOPIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_STOPIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_STOPIE_DIS (MXC_V_I2C_INT_EN0_STOPIE_DIS << MXC_F_I2C_INT_EN0_STOPIE_POS) |
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#define | MXC_V_I2C_INT_EN0_STOPIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_STOPIE_EN (MXC_V_I2C_INT_EN0_STOPIE_EN << MXC_F_I2C_INT_EN0_STOPIE_POS) |
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#define | MXC_F_I2C_INT_EN0_ADRACKIE_POS 7 |
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#define | MXC_F_I2C_INT_EN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADRACKIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_ADRACKIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_ADRACKIE_DIS (MXC_V_I2C_INT_EN0_ADRACKIE_DIS << MXC_F_I2C_INT_EN0_ADRACKIE_POS) |
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#define | MXC_V_I2C_INT_EN0_ADRACKIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_ADRACKIE_EN (MXC_V_I2C_INT_EN0_ADRACKIE_EN << MXC_F_I2C_INT_EN0_ADRACKIE_POS) |
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#define | MXC_F_I2C_INT_EN0_ARBERIE_POS 8 |
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#define | MXC_F_I2C_INT_EN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARBERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_ARBERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_ARBERIE_DIS (MXC_V_I2C_INT_EN0_ARBERIE_DIS << MXC_F_I2C_INT_EN0_ARBERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_ARBERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_ARBERIE_EN (MXC_V_I2C_INT_EN0_ARBERIE_EN << MXC_F_I2C_INT_EN0_ARBERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_TOERIE_POS 9 |
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#define | MXC_F_I2C_INT_EN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TOERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_TOERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_TOERIE_DIS (MXC_V_I2C_INT_EN0_TOERIE_DIS << MXC_F_I2C_INT_EN0_TOERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_TOERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_TOERIE_EN (MXC_V_I2C_INT_EN0_TOERIE_EN << MXC_F_I2C_INT_EN0_TOERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_ADRERIE_POS 10 |
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#define | MXC_F_I2C_INT_EN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADRERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_ADRERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_ADRERIE_DIS (MXC_V_I2C_INT_EN0_ADRERIE_DIS << MXC_F_I2C_INT_EN0_ADRERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_ADRERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_ADRERIE_EN (MXC_V_I2C_INT_EN0_ADRERIE_EN << MXC_F_I2C_INT_EN0_ADRERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_DATAERIE_POS 11 |
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#define | MXC_F_I2C_INT_EN0_DATAERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATAERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_DATAERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_DATAERIE_DIS (MXC_V_I2C_INT_EN0_DATAERIE_DIS << MXC_F_I2C_INT_EN0_DATAERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_DATAERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_DATAERIE_EN (MXC_V_I2C_INT_EN0_DATAERIE_EN << MXC_F_I2C_INT_EN0_DATAERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_DNRERIE_POS 12 |
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#define | MXC_F_I2C_INT_EN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DNRERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_DNRERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_DNRERIE_DIS (MXC_V_I2C_INT_EN0_DNRERIE_DIS << MXC_F_I2C_INT_EN0_DNRERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_DNRERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_DNRERIE_EN (MXC_V_I2C_INT_EN0_DNRERIE_EN << MXC_F_I2C_INT_EN0_DNRERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_STRTERIE_POS 13 |
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#define | MXC_F_I2C_INT_EN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STRTERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_STRTERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_STRTERIE_DIS (MXC_V_I2C_INT_EN0_STRTERIE_DIS << MXC_F_I2C_INT_EN0_STRTERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_STRTERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_STRTERIE_EN (MXC_V_I2C_INT_EN0_STRTERIE_EN << MXC_F_I2C_INT_EN0_STRTERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_STOPERIE_POS 14 |
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#define | MXC_F_I2C_INT_EN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOPERIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_STOPERIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_STOPERIE_DIS (MXC_V_I2C_INT_EN0_STOPERIE_DIS << MXC_F_I2C_INT_EN0_STOPERIE_POS) |
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#define | MXC_V_I2C_INT_EN0_STOPERIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_STOPERIE_EN (MXC_V_I2C_INT_EN0_STOPERIE_EN << MXC_F_I2C_INT_EN0_STOPERIE_POS) |
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#define | MXC_F_I2C_INT_EN0_TXLOIE_POS 15 |
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#define | MXC_F_I2C_INT_EN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TXLOIE_POS)) |
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#define | MXC_V_I2C_INT_EN0_TXLOIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN0_TXLOIE_DIS (MXC_V_I2C_INT_EN0_TXLOIE_DIS << MXC_F_I2C_INT_EN0_TXLOIE_POS) |
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#define | MXC_V_I2C_INT_EN0_TXLOIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN0_TXLOIE_EN (MXC_V_I2C_INT_EN0_TXLOIE_EN << MXC_F_I2C_INT_EN0_TXLOIE_POS) |
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#define | MXC_F_I2C_INT_FL1_RXOFI_POS 0 |
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#define | MXC_F_I2C_INT_FL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RXOFI_POS)) |
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#define | MXC_V_I2C_INT_FL1_RXOFI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL1_RXOFI_INACTIVE (MXC_V_I2C_INT_FL1_RXOFI_INACTIVE << MXC_F_I2C_INT_FL1_RXOFI_POS) |
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#define | MXC_V_I2C_INT_FL1_RXOFI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL1_RXOFI_PENDING (MXC_V_I2C_INT_FL1_RXOFI_PENDING << MXC_F_I2C_INT_FL1_RXOFI_POS) |
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#define | MXC_F_I2C_INT_FL1_TXUFI_POS 1 |
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#define | MXC_F_I2C_INT_FL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TXUFI_POS)) |
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#define | MXC_V_I2C_INT_FL1_TXUFI_INACTIVE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_FL1_TXUFI_INACTIVE (MXC_V_I2C_INT_FL1_TXUFI_INACTIVE << MXC_F_I2C_INT_FL1_TXUFI_POS) |
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#define | MXC_V_I2C_INT_FL1_TXUFI_PENDING ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_FL1_TXUFI_PENDING (MXC_V_I2C_INT_FL1_TXUFI_PENDING << MXC_F_I2C_INT_FL1_TXUFI_POS) |
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#define | MXC_F_I2C_INT_EN1_RXOFIE_POS 0 |
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#define | MXC_F_I2C_INT_EN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RXOFIE_POS)) |
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#define | MXC_V_I2C_INT_EN1_RXOFIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN1_RXOFIE_DIS (MXC_V_I2C_INT_EN1_RXOFIE_DIS << MXC_F_I2C_INT_EN1_RXOFIE_POS) |
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#define | MXC_V_I2C_INT_EN1_RXOFIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN1_RXOFIE_EN (MXC_V_I2C_INT_EN1_RXOFIE_EN << MXC_F_I2C_INT_EN1_RXOFIE_POS) |
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#define | MXC_F_I2C_INT_EN1_TXUFIE_POS 1 |
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#define | MXC_F_I2C_INT_EN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TXUFIE_POS)) |
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#define | MXC_V_I2C_INT_EN1_TXUFIE_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_INT_EN1_TXUFIE_DIS (MXC_V_I2C_INT_EN1_TXUFIE_DIS << MXC_F_I2C_INT_EN1_TXUFIE_POS) |
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#define | MXC_V_I2C_INT_EN1_TXUFIE_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_INT_EN1_TXUFIE_EN (MXC_V_I2C_INT_EN1_TXUFIE_EN << MXC_F_I2C_INT_EN1_TXUFIE_POS) |
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#define | MXC_F_I2C_FIFO_LEN_RXLEN_POS 0 |
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#define | MXC_F_I2C_FIFO_LEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RXLEN_POS)) |
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#define | MXC_F_I2C_FIFO_LEN_TXLEN_POS 8 |
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#define | MXC_F_I2C_FIFO_LEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TXLEN_POS)) |
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#define | MXC_F_I2C_RX_CTRL0_DNR_POS 0 |
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#define | MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) |
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#define | MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) |
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#define | MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_RX_CTRL0_DNR_DONT_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) |
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#define | MXC_F_I2C_RX_CTRL0_RXFSH_POS 7 |
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#define | MXC_F_I2C_RX_CTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS)) |
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#define | MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RXFSH_POS) |
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#define | MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_RX_CTRL0_RXFSH_FLUSH (MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH << MXC_F_I2C_RX_CTRL0_RXFSH_POS) |
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#define | MXC_F_I2C_RX_CTRL0_RXTH_POS 8 |
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#define | MXC_F_I2C_RX_CTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS)) |
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#define | MXC_F_I2C_RX_CTRL1_RXCNT_POS 0 |
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#define | MXC_F_I2C_RX_CTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RXCNT_POS)) |
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#define | MXC_F_I2C_RX_CTRL1_RXFIFO_POS 8 |
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#define | MXC_F_I2C_RX_CTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RXFIFO_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TXPRELD_POS 0 |
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#define | MXC_F_I2C_TX_CTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TXPRELD_POS)) |
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#define | MXC_V_I2C_TX_CTRL0_TXPRELD_NORMAL ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_TX_CTRL0_TXPRELD_NORMAL (MXC_V_I2C_TX_CTRL0_TXPRELD_NORMAL << MXC_F_I2C_TX_CTRL0_TXPRELD_POS) |
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#define | MXC_V_I2C_TX_CTRL0_TXPRELD_PRELOAD ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_TX_CTRL0_TXPRELD_PRELOAD (MXC_V_I2C_TX_CTRL0_TXPRELD_PRELOAD << MXC_F_I2C_TX_CTRL0_TXPRELD_POS) |
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#define | MXC_F_I2C_TX_CTRL0_TXFSH_POS 7 |
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#define | MXC_F_I2C_TX_CTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TXFSH_POS)) |
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#define | MXC_V_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TXFSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TXFSH_POS) |
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#define | MXC_V_I2C_TX_CTRL0_TXFSH_FLUSH ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_TX_CTRL0_TXFSH_FLUSH (MXC_V_I2C_TX_CTRL0_TXFSH_FLUSH << MXC_F_I2C_TX_CTRL0_TXFSH_POS) |
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#define | MXC_F_I2C_TX_CTRL0_TXTH_POS 8 |
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#define | MXC_F_I2C_TX_CTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TXTH_POS)) |
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#define | MXC_F_I2C_TX_CTRL1_TXRDY_POS 0 |
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#define | MXC_F_I2C_TX_CTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TXRDY_POS)) |
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#define | MXC_V_I2C_TX_CTRL1_TXRDY_NOT_READY ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_TX_CTRL1_TXRDY_NOT_READY (MXC_V_I2C_TX_CTRL1_TXRDY_NOT_READY << MXC_F_I2C_TX_CTRL1_TXRDY_POS) |
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#define | MXC_V_I2C_TX_CTRL1_TXRDY_READY ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_TX_CTRL1_TXRDY_READY (MXC_V_I2C_TX_CTRL1_TXRDY_READY << MXC_F_I2C_TX_CTRL1_TXRDY_POS) |
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#define | MXC_F_I2C_TX_CTRL1_TXLAST_POS 1 |
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#define | MXC_F_I2C_TX_CTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TXLAST_POS)) |
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#define | MXC_V_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST (MXC_V_I2C_TX_CTRL1_TXLAST_PAUSE_ON_LAST << MXC_F_I2C_TX_CTRL1_TXLAST_POS) |
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#define | MXC_V_I2C_TX_CTRL1_TXLAST_END_ON_LAST ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_TX_CTRL1_TXLAST_END_ON_LAST (MXC_V_I2C_TX_CTRL1_TXLAST_END_ON_LAST << MXC_F_I2C_TX_CTRL1_TXLAST_POS) |
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#define | MXC_F_I2C_TX_CTRL1_TXFIFO_POS 8 |
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#define | MXC_F_I2C_TX_CTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TXFIFO_POS)) |
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#define | MXC_F_I2C_FIFO_DATA_POS 0 |
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#define | MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) |
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#define | MXC_F_I2C_MSTR_MODE_START_POS 0 |
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#define | MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) |
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#define | MXC_V_I2C_MSTR_MODE_START_START ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_MSTR_MODE_START_START (MXC_V_I2C_MSTR_MODE_START_START << MXC_F_I2C_MSTR_MODE_START_POS) |
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#define | MXC_F_I2C_MSTR_MODE_RESTART_POS 1 |
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#define | MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) |
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#define | MXC_V_I2C_MSTR_MODE_RESTART_RESTART ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_MSTR_MODE_RESTART_RESTART (MXC_V_I2C_MSTR_MODE_RESTART_RESTART << MXC_F_I2C_MSTR_MODE_RESTART_POS) |
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#define | MXC_F_I2C_MSTR_MODE_STOP_POS 2 |
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#define | MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) |
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#define | MXC_V_I2C_MSTR_MODE_STOP_STOP ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_MSTR_MODE_STOP_STOP (MXC_V_I2C_MSTR_MODE_STOP_STOP << MXC_F_I2C_MSTR_MODE_STOP_POS) |
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#define | MXC_F_I2C_MSTR_MODE_SEA_POS 7 |
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#define | MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) |
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#define | MXC_V_I2C_MSTR_MODE_SEA_7BIT_ADDR ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_MSTR_MODE_SEA_7BIT_ADDR (MXC_V_I2C_MSTR_MODE_SEA_7BIT_ADDR << MXC_F_I2C_MSTR_MODE_SEA_POS) |
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#define | MXC_V_I2C_MSTR_MODE_SEA_10BIT_ADDR ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_MSTR_MODE_SEA_10BIT_ADDR (MXC_V_I2C_MSTR_MODE_SEA_10BIT_ADDR << MXC_F_I2C_MSTR_MODE_SEA_POS) |
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#define | MXC_F_I2C_CLK_LO_SCL_LO_POS 0 |
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#define | MXC_F_I2C_CLK_LO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_SCL_LO_POS)) |
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#define | MXC_F_I2C_CLK_HI_SCL_HI_POS 0 |
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#define | MXC_F_I2C_CLK_HI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_SCL_HI_POS)) |
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#define | MXC_F_I2C_TIMEOUT_TO_POS 0 |
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#define | MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) |
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#define | MXC_F_I2C_SLV_ADDR_SLA_POS 0 |
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#define | MXC_F_I2C_SLV_ADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLV_ADDR_SLA_POS)) |
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#define | MXC_F_I2C_SLV_ADDR_EA_POS 15 |
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#define | MXC_F_I2C_SLV_ADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLV_ADDR_EA_POS)) |
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#define | MXC_V_I2C_SLV_ADDR_EA_7BIT_ADDR ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_SLV_ADDR_EA_7BIT_ADDR (MXC_V_I2C_SLV_ADDR_EA_7BIT_ADDR << MXC_F_I2C_SLV_ADDR_EA_POS) |
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#define | MXC_V_I2C_SLV_ADDR_EA_10BIT_ADDR ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_SLV_ADDR_EA_10BIT_ADDR (MXC_V_I2C_SLV_ADDR_EA_10BIT_ADDR << MXC_F_I2C_SLV_ADDR_EA_POS) |
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#define | MXC_F_I2C_DMA_TXEN_POS 0 |
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#define | MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) |
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#define | MXC_V_I2C_DMA_TXEN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_DMA_TXEN_DIS (MXC_V_I2C_DMA_TXEN_DIS << MXC_F_I2C_DMA_TXEN_POS) |
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#define | MXC_V_I2C_DMA_TXEN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_DMA_TXEN_EN (MXC_V_I2C_DMA_TXEN_EN << MXC_F_I2C_DMA_TXEN_POS) |
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#define | MXC_F_I2C_DMA_RXEN_POS 1 |
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#define | MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) |
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#define | MXC_V_I2C_DMA_RXEN_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_DMA_RXEN_DIS (MXC_V_I2C_DMA_RXEN_DIS << MXC_F_I2C_DMA_RXEN_POS) |
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#define | MXC_V_I2C_DMA_RXEN_EN ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_DMA_RXEN_EN (MXC_V_I2C_DMA_RXEN_EN << MXC_F_I2C_DMA_RXEN_POS) |
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