Xilinx AXI Verification IP (VIP)

Overview

The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added sequencer, monitor and wrapper class. [1]

Inheritance diagram for AMD AXI VIP

xil_voidxil_objectxil_reporterxil_componentxil_agent-emptyxil_analysis_port#+writeinput T+getoutput Txil_driver#-emptyxil_monitor-emptyxil_axi_slv_mem_model#axi_vif_mem_proxy#axi_monitor#axi_mst_wr_driver#axi_mst_rd_driver#axi_slv_wr_driver#axi_slv_rd_driver#axi_mst_agent#axi_slv_agent#axi_slv_mem_agent#axi_passthrough_agent#axi_passthrough_mem_agent#

Aggregation diagram for AMD AXI VIP

xil_analysis_port#+writeinput T+getoutput Txil_axi_slv_mem_model#axi_vif_mem_proxy#axi_monitor#axi_mst_wr_driver#axi_mst_rd_driver#axi_slv_wr_driver#axi_slv_rd_driver#axi_mst_agent#axi_slv_agent#axi_slv_mem_agent#axi_passthrough_agent#axi_passthrough_mem_agent#

Components

ADI AXI Agent (VIP)

Has a master, slave and passthrough variant. Encapsulates the AMD AXI VIP, ADI AXI Master and/or Slave Sequencers and the ADI AXI Monitor. Provides functions to start, stop and run the classes within.

ADI AXI Master Sequencer (VIP)

The ADI AXI Master Sequencer provides functions to easily read, write and verify data on a specified address. It is preconfigured to support only AXI4Lite transactions.

ADI AXI Slave Sequencer (VIP)

The ADI AXI Slave Sequencer provides functions to easily read, write and verify data from a memory.

ADI AXI Monitor (VIP)

The ADI AXI Monitor provides functions to monitor an AXI interface, collect data transmitted and broadcast it to other classes using a publisher-subscriber pattern.

References

[1] “AXI Verification IP LogiCORE IP Product Guide (PG267)”, Xilinx, 2019