AD7606

Overview

The purpose of this testbench is to validate the serial interface functionality of the projects/ad7606x_fmc reference design.

The entire HDL documentation can be found here AD7606x-FMC HDL project.

Block design

The testbench block design includes part of the AD7606x-FMC HDL reference design, along with VIPs used for clocking, reset, PS and DDR simulations.

Block diagram

The data path and clock domains are depicted in the below diagram:

Configuration parameters and modes

The following parameters of this project that can be configured:

• DEV_CONFIG: defines the device: Options: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18

• EXT_CLK: defines the usage of an external clock: Options: 0 - without external clock, 1 - with external clock

• INTF: defines the interface type: Options: 0 - Parallel, 1 - Serial

• NUM_OF_SDI: defines the number of MOSI lines of the SPI interface: Options: 1 - Interleaved mode, 2 - 1 lane per channel, 4 - 2 lanes per channel, 8 - 4 lanes per channel

Configuration files

The following configuration files are available:

Configuration mode	Parameters
	DEV_CONFIG	EXT_CLK	INTF	NUM_OF_SDI
cfg1	0	0	0	1
cfg2	1	0	0	1
cfg3	2	0	0	1

Tests

The following test program file is available:

Test program	Usage
test_program	Tests the serial interface capabilities.

Available configurations & tests combinations

The test program is compatible with all of the above mentioned configurations.

CPU/Memory interconnect addresses

Below are the CPU/Memory interconnect addresses used in this project:

Instance	Address
spi_ad7616_axi_regmap	0x44A0_0000
axi_ad7606x_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
ad7606_pwm_gen	0x44B0_0000

Interrupts

Below are the Programmable Logic interrupts used in this project:

Instance name	HDL
axi_ad7606_dma	13
spi_ad7606	12

Test stimulus

The test program is structured into several tests as follows:

Environment bringup

The steps of the environment bringup are:

• Create the environment

• Start the environment

• Start the clocks

• Assert the resets

Sanity test

This test is used to check the communication with the AXI REGMAP module of the AD7606 SPI Engine interface, by reading the core VERSION register, along with writing and reading the SCRATCH register.

Simple configuration test

The adc_config_SIMPLE_test is used for verifying the mode 0 of the ADC.

The steps of this test are:

• Get the ADC common core out of reset

• Set & read the ADC_CONFIG WR & CTRL registers of the ADC_COMMON

• Read data on the rx_db_o port

• Set HDL config mode 0

CRC configuration test

The adc_config_CRC_test is used for verifying the mode 1 of the ADC.

The steps of this test are:

• Get the ADC common core out of reset

• Set CRC and static data setup

• Set & read the ADC_CONFIG WR & CTRL registers of the ADC_COMMON

• Read data on the rx_db_o port

• Set HDL config mode 1

Status configuration test

The adc_config_STATUS_test is used for verifying the mode 2 of the ADC.

The steps of this test are:

• Get the ADC common core out of reset

• Set STATUS and static data setup

• Set & read the ADC_CONFIG WR & CTRL registers of the ADC_COMMON

• Read data on the rx_db_o port

• Set HDL config mode 2

Status CRC configuration test

The adc_config_STATUS_CRC_test is used for verifying the mode 3 of the ADC.

The steps of this test are:

• Get the ADC common core out of reset

• Set CRC and static data setup

• Set STATUS and static data setup

• Set & read the ADC_CONFIG WR & CTRL registers of the ADC_COMMON

• Read data on the rx_db_o port

• Set HDL config mode 3

Stop the environment

• Stop the clocks

Building the testbench

The testbench is built upon ADI’s generic HDL reference design framework. ADI does not distribute compiled files of these projects so they must be built from the sources available here and here, with the specified hierarchy described Set up the Testbenches repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

Example 1

Build all the possible combinations of tests and configurations, using only the command line.

user@analog:~$

cd testbenches/project/ad7606x

user@analog:~/testbenches/project/ad7606x$

make

Example 2

Build all the possible combinations of tests and configurations, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/ad7606x

user@analog:~/testbenches/project/ad7606x$

make MODE=gui

Example 3

Build a particular combination of test and configuration, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/ad7606x

user@analog:~/testbenches/project/ad7606x$

make MODE=gui CFG=cfg1 TST=test_program

The built projects can be found in the runs folder, where each configuration specific build has it’s own folder named after the configuration file’s name. Example: if the following command was run for a single configuration in the clean folder (no runs folder available):

make CFG=cfg1

Then the subfolder under runs name will be:

cfg1

Resources

HDL related dependencies forming the DUT

IP name	Source code link	Documentation link
SYNC_BITS	library/util_cdc/sync_bits.v **	—
AD_EDGE_DETECT	library/common/ad_edge_detect.v	—
AXI_AD7606x	library/axi_ad7606x *	[Wiki]
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine **	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution **	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect **	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload **	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—
UTIL_CPACK2	library/util_pack/util_cpack2 *	here

Legend

• * instantiated only for INTF=0 (parallel interface)

• ** instantiated only for INTF=1 (serial interface)

Testbenches related dependencies

Common with most testbenches:

SV dependency name	Source code link	Documentation link
LOGGER_PKG	library/utilities/logger_pkg.sv	—
M_AXI_SEQUENCER	library/vip/amd/m_axi_sequencer.sv	—
REG_ACCESSOR	library/regmaps/reg_accessor.sv	—
S_AXI_SEQUENCER	library/vip/amd/s_axi_sequencer.sv	—
TEST_HARNESS_ENV	library/utilities/test_harness_env.sv	Test Harness
UTILS	library/utilities/utils.svh	—
WATCHDOG	library/drivers/common/watchdog.sv	Watchdog

Testbench specific dependencies:

SV dependency name	Source code link	Documentation link
ADI_REGMAP_ADC_PKG	library/regmaps/adi_regmap_adc_pkg.sv	—
ADI_REGMAP_COMMON_PKG	library/regmaps/adi_regmap_common_pkg.sv	—
ADI_REGMAP_DMAC_PKG	library/regmaps/adi_regmap_dmac_pkg.	—
ADI_REGMAP_PKG	library/regmaps/adi_regmap_pkg.sv	—
ADI_REGMAP_PWM_GEN_PKG	library/regmaps/adi_regmap_pwm_gen_pkg.sv	—
DMA_TRANS	library/drivers/dmac/dma_trans.sv	—
DMAC_API	library/drivers/dmac/dmac_api.sv	—
M_AXIS_SEQUENCER	library/vip/amd/m_axis_sequencer.sv	—
S_AXIS_SEQUENCER	library/vip/amd/s_axis_sequencer.sv	—

More information

• ADI Testbenches User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.