AD463x
Overview
The purpose of this testbench is to validate the serial interface functionality of the projects/ad4630_fmc reference design.
The entire HDL documentation can be found here AD4630-FMC HDL project.
Block design
The testbench block design includes part of the AD4630-FMC HDL reference design, along with VIPs used for clocking, reset, PS and DDR simulations.
Block diagram
The data path and clock domains are depicted in the below diagram:
Configuration parameters and modes
The following parameters of this project that can be configured:
CLK_MODE: defines clocking mode of the device’s digital interface: Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
NUM_OF_SDI: defines the number of MOSI lines of the SPI interface: Options: 1 - Interleaved mode, 2 - 1 lane per channel, 4 - 2 lanes per channel, 8 - 4 lanes per channel
CAPTURE_ZONE: defines the capture zone of the next sample. There are two capture zones: 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns, 2 - from the next consecutive CNV positive edge +20ns until the second next consecutive CNV positive edge -20ns
DDR_EN: defines the type of data transfer. In echo and master clock mode the SDI lines can have Single or Double Data Rates. Options: 0 - MISO runs on SDR, 1 - MISO runs on DDR.
Configuration files
The following configuration files are available:
Configuration mode
Parameters
CLK_MODE
NUM_OF_SDI
CAPTURE_ZONE
DDR_EN
cfg_cm0_sdi2_cz1_ddr0
0
2
1
0
cfg_cm0_sdi2_cz2_ddr0
0
2
2
0
cfg_cm0_sdi4_cz2_ddr0
0
4
2
0
cfg_cm0_sdi8_cz2_ddr0
0
8
2
0
cfg_cm1_sdi1_cz2_ddr0
1
1
2
0
cfg_cm1_sdi2_cz2_ddr0
1
2
2
0
cfg_cm1_sdi2_cz2_ddr1
1
2
2
1
cfg_cm1_sdi4_cz2_ddr0
1
4
2
0
cfg_cm1_sdi4_cz2_ddr1
1
4
2
1
cfg_cm1_sdi8_cz2_ddr0
1
8
2
0
cfg_cm1_sdi8_cz2_ddr1
1
8
2
1
Tests
The following test program file is available:
Test program |
Usage |
|---|---|
test_program |
Tests the serial interface capabilities. |
Available configurations & tests combinations
The test program is compatible with all of the above mentioned configurations.
Clock scheme
The design supports the following interface and clock modes both in SDR and DDR:
Mode |
1 Lane per channel |
2 Lane per channel |
4 lane per channel |
|---|---|---|---|
SPI mode |
yes |
yes |
yes |
Echo Clock mode |
yes |
yes |
yes |
CPU/Memory interconnect addresses
Below are the CPU/Memory interconnect addresses used in this project:
Instance |
Address |
|---|---|
spi_ad463x_axi_regmap |
0x44A0_0000 |
axi_ad463x_dma |
0x44A3_0000 |
spi_clkgen |
0x44A7_0000 |
cnv_generator |
0x44B0_0000 |
sync_generator |
0x44C0_0000 |
Interrupts
Below are the Programmable Logic interrupts used in this project:
Instance name |
HDL |
|---|---|
axi_ad463x_dma |
13 |
spi_ad463x |
12 |
Test stimulus
The test program is structured into several tests as follows:
Environment bringup
The steps of the environment bringup are:
Create the environment
Start the environment
Start the clocks
Assert the resets
Sanity test
This test is used to check the communication with the AXI REGMAP module of the AD463X SPI Engine interface, by reading the core VERSION register, along with writing and reading the SCRATCH register.
FIFO SPI test
The FIFO SPI test verifies the simple serial transfers, made through the Execution module.
The steps of this test are:
Start the SPI clock generator (axi_clkgen)
Configure the conversion signal generator (axi_pwmgen)
Enable SPI Engine & configure the Execution module
Set up the interrupts
Generate a FIFO transaction
Capture and compare the results, using the PEEK register of the AXI SPI Engine
Offload SPI test
The Offload SPI test verifies the Offload module functionality.
The steps of this test are:
Configure the DMA
Configure the Offload module
Start the Offload module
Capture and compare the Offload SDI data
Stop the environment
Stop the clocks
Building the testbench
The testbench is built upon ADI’s generic HDL reference design framework. ADI does not distribute compiled files of these projects so they must be built from the sources available here and here, with the specified hierarchy described Set up the Testbenches repository. To get the source you must clone the HDL repository, and then build the project as follows:.
Linux/Cygwin/WSL
Example 1
Build all the possible combinations of tests and configurations, using only the command line.
user@analog:~$
cd testbenches/project/ad463x
user@analog:~/testbenches/project/ad463x$
make
Example 2
Build all the possible combinations of tests and configurations, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.
user@analog:~$
cd testbenches/project/ad463x
user@analog:~/testbenches/project/ad463x$
make MODE=gui
Example 3
Build a particular combination of test and configuration, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.
user@analog:~$
cd testbenches/project/ad463x
user@analog:~/testbenches/project/ad463x$
make MODE=gui CFG=cfg_cm0_sdi2_cz1_ddr0 TST=test_program
The built projects can be found in the runs folder, where each configuration
specific build has it’s own folder named after the configuration file’s name.
Example: if the following command was run for a single configuration in the
clean folder (no runs folder available):
make CFG=cfg_cm0_sdi2_cz1_ddr0
Then the subfolder under runs name will be:
cfg_cm0_sdi2_cz1_ddr0
Resources
More information
Support
Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.
It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.